1/*	$NetBSD: amdgpu_dm_crc.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $	*/
2
3/*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
29#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
30
31struct drm_crtc;
32struct dm_crtc_state;
33
34enum amdgpu_dm_pipe_crc_source {
35	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
36	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
37	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
38	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
39	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
40	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
41	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
42};
43
44static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
45{
46	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
47	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
48}
49
50/* amdgpu_dm_crc.c */
51#ifdef CONFIG_DEBUG_FS
52int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
53					struct dm_crtc_state *dm_crtc_state,
54					enum amdgpu_dm_pipe_crc_source source);
55int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
56int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
57				     const char *src_name,
58				     size_t *values_cnt);
59const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
60						  size_t *count);
61void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
62#else
63#define amdgpu_dm_crtc_set_crc_source NULL
64#define amdgpu_dm_crtc_verify_crc_source NULL
65#define amdgpu_dm_crtc_get_crc_sources NULL
66#define amdgpu_dm_crtc_handle_crc_irq(x)
67#endif
68
69#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
70