1/*	$NetBSD: amdgpu_dm_crc.c,v 1.3 2021/12/26 21:00:14 riastradh Exp $	*/
2
3/*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#include <sys/cdefs.h>
29__KERNEL_RCSID(0, "$NetBSD: amdgpu_dm_crc.c,v 1.3 2021/12/26 21:00:14 riastradh Exp $");
30
31#include <drm/drm_crtc.h>
32#include <drm/drm_vblank.h>
33
34#include "amdgpu.h"
35#include "amdgpu_dm.h"
36#include "dc.h"
37
38static const char *const pipe_crc_sources[] = {
39	"none",
40	"crtc",
41	"crtc dither",
42	"dprx",
43	"dprx dither",
44	"auto",
45};
46
47static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
48{
49	if (!source || !strcmp(source, "none"))
50		return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
51	if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
52		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
53	if (!strcmp(source, "dprx"))
54		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
55	if (!strcmp(source, "crtc dither"))
56		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
57	if (!strcmp(source, "dprx dither"))
58		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
59
60	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
61}
62
63static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
64{
65	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
66	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
67}
68
69static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
70{
71	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
72	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
73}
74
75static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
76{
77	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
78	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
79	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
80}
81
82const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
83						  size_t *count)
84{
85	*count = ARRAY_SIZE(pipe_crc_sources);
86	return pipe_crc_sources;
87}
88
89int
90amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
91				 size_t *values_cnt)
92{
93	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
94
95	if (source < 0) {
96		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
97				 src_name, crtc->index);
98		return -EINVAL;
99	}
100
101	*values_cnt = 3;
102	return 0;
103}
104
105int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
106					struct dm_crtc_state *dm_crtc_state,
107					enum amdgpu_dm_pipe_crc_source source)
108{
109	struct amdgpu_device *adev = crtc->dev->dev_private;
110	struct dc_stream_state *stream_state = dm_crtc_state->stream;
111	bool enable = amdgpu_dm_is_valid_crc_source(source);
112	int ret = 0;
113
114	/* Configuration will be deferred to stream enable. */
115	if (!stream_state)
116		return 0;
117
118	mutex_lock(&adev->dm.dc_lock);
119
120	/* Enable CRTC CRC generation if necessary. */
121	if (dm_is_crc_source_crtc(source)) {
122		if (!dc_stream_configure_crc(stream_state->ctx->dc,
123					     stream_state, enable, enable)) {
124			ret = -EINVAL;
125			goto unlock;
126		}
127	}
128
129	/* Configure dithering */
130	if (!dm_need_crc_dither(source)) {
131		dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
132		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
133					    DYN_EXPANSION_DISABLE);
134	} else {
135		dc_stream_set_dither_option(stream_state,
136					    DITHER_OPTION_DEFAULT);
137		dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
138					    DYN_EXPANSION_AUTO);
139	}
140
141unlock:
142	mutex_unlock(&adev->dm.dc_lock);
143
144	return ret;
145}
146
147int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
148{
149	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
150	struct drm_crtc_commit *commit;
151	struct dm_crtc_state *crtc_state;
152	struct drm_dp_aux *aux = NULL;
153	bool enable = false;
154	bool enabled = false;
155	int ret = 0;
156
157	if (source < 0) {
158		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
159				 src_name, crtc->index);
160		return -EINVAL;
161	}
162
163	ret = drm_modeset_lock(&crtc->mutex, NULL);
164	if (ret)
165		return ret;
166
167	spin_lock(&crtc->commit_lock);
168	commit = list_first_entry_or_null(&crtc->commit_list,
169					  struct drm_crtc_commit, commit_entry);
170	if (commit)
171		drm_crtc_commit_get(commit);
172	spin_unlock(&crtc->commit_lock);
173
174	if (commit) {
175		/*
176		 * Need to wait for all outstanding programming to complete
177		 * in commit tail since it can modify CRC related fields and
178		 * hardware state. Since we're holding the CRTC lock we're
179		 * guaranteed that no other commit work can be queued off
180		 * before we modify the state below.
181		 */
182		ret = wait_for_completion_interruptible_timeout(
183			&commit->hw_done, 10 * HZ);
184		if (ret)
185			goto cleanup;
186	}
187
188	enable = amdgpu_dm_is_valid_crc_source(source);
189	crtc_state = to_dm_crtc_state(crtc->state);
190
191	/*
192	 * USER REQ SRC | CURRENT SRC | BEHAVIOR
193	 * -----------------------------
194	 * None         | None        | Do nothing
195	 * None         | CRTC        | Disable CRTC CRC, set default to dither
196	 * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
197	 * None         | CRTC DITHER | Disable CRTC CRC
198	 * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
199	 * CRTC         | XXXX        | Enable CRTC CRC, no dither
200	 * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
201	 * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
202	 * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
203	 */
204	if (dm_is_crc_source_dprx(source) ||
205	    (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
206	     dm_is_crc_source_dprx(crtc_state->crc_src))) {
207		struct amdgpu_dm_connector *aconn = NULL;
208		struct drm_connector *connector;
209		struct drm_connector_list_iter conn_iter;
210
211		drm_connector_list_iter_begin(crtc->dev, &conn_iter);
212		drm_for_each_connector_iter(connector, &conn_iter) {
213			if (!connector->state || connector->state->crtc != crtc)
214				continue;
215
216			aconn = to_amdgpu_dm_connector(connector);
217			break;
218		}
219		drm_connector_list_iter_end(&conn_iter);
220
221		if (!aconn) {
222			DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
223			ret = -EINVAL;
224			goto cleanup;
225		}
226
227		aux = &aconn->dm_dp_aux.aux;
228
229		if (!aux) {
230			DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
231			ret = -EINVAL;
232			goto cleanup;
233		}
234	}
235
236	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
237		ret = -EINVAL;
238		goto cleanup;
239	}
240
241	/*
242	 * Reading the CRC requires the vblank interrupt handler to be
243	 * enabled. Keep a reference until CRC capture stops.
244	 */
245	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
246	if (!enabled && enable) {
247		ret = drm_crtc_vblank_get(crtc);
248		if (ret)
249			goto cleanup;
250
251		if (dm_is_crc_source_dprx(source)) {
252			if (drm_dp_start_crc(aux, crtc)) {
253				DRM_DEBUG_DRIVER("dp start crc failed\n");
254				ret = -EINVAL;
255				goto cleanup;
256			}
257		}
258	} else if (enabled && !enable) {
259		drm_crtc_vblank_put(crtc);
260		if (dm_is_crc_source_dprx(source)) {
261			if (drm_dp_stop_crc(aux)) {
262				DRM_DEBUG_DRIVER("dp stop crc failed\n");
263				ret = -EINVAL;
264				goto cleanup;
265			}
266		}
267	}
268
269	crtc_state->crc_src = source;
270
271	/* Reset crc_skipped on dm state */
272	crtc_state->crc_skip_count = 0;
273
274cleanup:
275	if (commit)
276		drm_crtc_commit_put(commit);
277
278	drm_modeset_unlock(&crtc->mutex);
279
280	return ret;
281}
282
283/**
284 * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
285 * @crtc: DRM CRTC object.
286 *
287 * This function should be called at the end of a vblank, when the fb has been
288 * fully processed through the pipe.
289 */
290void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
291{
292	struct dm_crtc_state *crtc_state;
293	struct dc_stream_state *stream_state;
294	uint32_t crcs[3];
295
296	if (crtc == NULL)
297		return;
298
299	crtc_state = to_dm_crtc_state(crtc->state);
300	stream_state = crtc_state->stream;
301
302	/* Early return if CRC capture is not enabled. */
303	if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
304		return;
305
306	/*
307	 * Since flipping and crc enablement happen asynchronously, we - more
308	 * often than not - will be returning an 'uncooked' crc on first frame.
309	 * Probably because hw isn't ready yet. For added security, skip the
310	 * first two CRC values.
311	 */
312	if (crtc_state->crc_skip_count < 2) {
313		crtc_state->crc_skip_count += 1;
314		return;
315	}
316
317	if (dm_is_crc_source_crtc(crtc_state->crc_src)) {
318		if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
319				       &crcs[0], &crcs[1], &crcs[2]))
320			return;
321
322		spin_lock(&crtc->dev->event_lock);
323		drm_crtc_add_crc_entry(crtc, true,
324				       drm_crtc_accurate_vblank_count(crtc), crcs);
325		spin_unlock(&crtc->dev->event_lock);
326	}
327}
328