kfd_pm4_headers.h revision 1.2 
1/*	$NetBSD: kfd_pm4_headers.h,v 1.2 2018/08/27 04:58:20 riastradh Exp $	*/
2
3/*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef KFD_PM4_HEADERS_H_
27#define KFD_PM4_HEADERS_H_
28
29#ifndef PM4_MES_HEADER_DEFINED
30#define PM4_MES_HEADER_DEFINED
31union PM4_MES_TYPE_3_HEADER {
32	struct {
33		uint32_t reserved1:8;	/* < reserved */
34		uint32_t opcode:8;	/* < IT opcode */
35		uint32_t count:14;	/* < number of DWORDs - 1
36					 * in the information body.
37					 */
38		uint32_t type:2;	/* < packet identifier.
39					 * It should be 3 for type 3 packets
40					 */
41	};
42	uint32_t u32all;
43};
44#endif /* PM4_MES_HEADER_DEFINED */
45
46/* --------------------MES_SET_RESOURCES-------------------- */
47
48#ifndef PM4_MES_SET_RESOURCES_DEFINED
49#define PM4_MES_SET_RESOURCES_DEFINED
50enum set_resources_queue_type_enum {
51	queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
52	queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
53	queue_type__mes_set_resources__hsa_debug_interface_queue = 4
54};
55
56struct pm4_set_resources {
57	union {
58		union PM4_MES_TYPE_3_HEADER header;	/* header */
59		uint32_t ordinal1;
60	};
61
62	union {
63		struct {
64			uint32_t vmid_mask:16;
65			uint32_t unmap_latency:8;
66			uint32_t reserved1:5;
67			enum set_resources_queue_type_enum queue_type:3;
68		} bitfields2;
69		uint32_t ordinal2;
70	};
71
72	uint32_t queue_mask_lo;
73	uint32_t queue_mask_hi;
74	uint32_t gws_mask_lo;
75	uint32_t gws_mask_hi;
76
77	union {
78		struct {
79			uint32_t oac_mask:16;
80			uint32_t reserved2:16;
81		} bitfields7;
82		uint32_t ordinal7;
83	};
84
85	union {
86		struct {
87			uint32_t gds_heap_base:6;
88			uint32_t reserved3:5;
89			uint32_t gds_heap_size:6;
90			uint32_t reserved4:15;
91		} bitfields8;
92		uint32_t ordinal8;
93	};
94
95};
96#endif
97
98/*--------------------MES_RUN_LIST-------------------- */
99
100#ifndef PM4_MES_RUN_LIST_DEFINED
101#define PM4_MES_RUN_LIST_DEFINED
102
103struct pm4_runlist {
104	union {
105		union PM4_MES_TYPE_3_HEADER header;	/* header */
106		uint32_t ordinal1;
107	};
108
109	union {
110		struct {
111			uint32_t reserved1:2;
112			uint32_t ib_base_lo:30;
113		} bitfields2;
114		uint32_t ordinal2;
115	};
116
117	union {
118		struct {
119			uint32_t ib_base_hi:16;
120			uint32_t reserved2:16;
121		} bitfields3;
122		uint32_t ordinal3;
123	};
124
125	union {
126		struct {
127			uint32_t ib_size:20;
128			uint32_t chain:1;
129			uint32_t offload_polling:1;
130			uint32_t reserved3:1;
131			uint32_t valid:1;
132			uint32_t reserved4:8;
133		} bitfields4;
134		uint32_t ordinal4;
135	};
136
137};
138#endif
139
140/*--------------------MES_MAP_PROCESS-------------------- */
141
142#ifndef PM4_MES_MAP_PROCESS_DEFINED
143#define PM4_MES_MAP_PROCESS_DEFINED
144
145struct pm4_map_process {
146	union {
147		union PM4_MES_TYPE_3_HEADER header;	/* header */
148		uint32_t ordinal1;
149	};
150
151	union {
152		struct {
153			uint32_t pasid:16;
154			uint32_t reserved1:8;
155			uint32_t diq_enable:1;
156			uint32_t process_quantum:7;
157		} bitfields2;
158		uint32_t ordinal2;
159	};
160
161	union {
162		struct {
163			uint32_t page_table_base:28;
164			uint32_t reserved3:4;
165		} bitfields3;
166		uint32_t ordinal3;
167	};
168
169	uint32_t sh_mem_bases;
170	uint32_t sh_mem_ape1_base;
171	uint32_t sh_mem_ape1_limit;
172	uint32_t sh_mem_config;
173	uint32_t gds_addr_lo;
174	uint32_t gds_addr_hi;
175
176	union {
177		struct {
178			uint32_t num_gws:6;
179			uint32_t reserved4:2;
180			uint32_t num_oac:4;
181			uint32_t reserved5:4;
182			uint32_t gds_size:6;
183			uint32_t num_queues:10;
184		} bitfields10;
185		uint32_t ordinal10;
186	};
187
188};
189#endif
190
191/*--------------------MES_MAP_QUEUES--------------------*/
192
193#ifndef PM4_MES_MAP_QUEUES_DEFINED
194#define PM4_MES_MAP_QUEUES_DEFINED
195enum map_queues_queue_sel_enum {
196	queue_sel__mes_map_queues__map_to_specified_queue_slots = 0,
197	queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1,
198	queue_sel__mes_map_queues__enable_process_queues = 2
199};
200
201enum map_queues_vidmem_enum {
202	vidmem__mes_map_queues__uses_no_video_memory = 0,
203	vidmem__mes_map_queues__uses_video_memory = 1
204};
205
206enum map_queues_alloc_format_enum {
207	alloc_format__mes_map_queues__one_per_pipe = 0,
208	alloc_format__mes_map_queues__all_on_one_pipe = 1
209};
210
211enum map_queues_engine_sel_enum {
212	engine_sel__mes_map_queues__compute = 0,
213	engine_sel__mes_map_queues__sdma0 = 2,
214	engine_sel__mes_map_queues__sdma1 = 3
215};
216
217struct pm4_map_queues {
218	union {
219		union PM4_MES_TYPE_3_HEADER header;	/* header */
220		uint32_t ordinal1;
221	};
222
223	union {
224		struct {
225			uint32_t reserved1:4;
226			enum map_queues_queue_sel_enum queue_sel:2;
227			uint32_t reserved2:2;
228			uint32_t vmid:4;
229			uint32_t reserved3:4;
230			enum map_queues_vidmem_enum vidmem:2;
231			uint32_t reserved4:6;
232			enum map_queues_alloc_format_enum alloc_format:2;
233			enum map_queues_engine_sel_enum engine_sel:3;
234			uint32_t num_queues:3;
235		} bitfields2;
236		uint32_t ordinal2;
237	};
238
239	struct {
240		union {
241			struct {
242				uint32_t is_static:1;
243				uint32_t reserved5:1;
244				uint32_t doorbell_offset:21;
245				uint32_t reserved6:3;
246				uint32_t queue:6;
247			} bitfields3;
248			uint32_t ordinal3;
249		};
250
251		uint32_t mqd_addr_lo;
252		uint32_t mqd_addr_hi;
253		uint32_t wptr_addr_lo;
254		uint32_t wptr_addr_hi;
255
256	} mes_map_queues_ordinals[1];	/* 1..N of these ordinal groups */
257
258};
259#endif
260
261/*--------------------MES_QUERY_STATUS--------------------*/
262
263#ifndef PM4_MES_QUERY_STATUS_DEFINED
264#define PM4_MES_QUERY_STATUS_DEFINED
265enum query_status_interrupt_sel_enum {
266	interrupt_sel__mes_query_status__completion_status = 0,
267	interrupt_sel__mes_query_status__process_status = 1,
268	interrupt_sel__mes_query_status__queue_status = 2
269};
270
271enum query_status_command_enum {
272	command__mes_query_status__interrupt_only = 0,
273	command__mes_query_status__fence_only_immediate = 1,
274	command__mes_query_status__fence_only_after_write_ack = 2,
275	command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
276};
277
278enum query_status_engine_sel_enum {
279	engine_sel__mes_query_status__compute = 0,
280	engine_sel__mes_query_status__sdma0_queue = 2,
281	engine_sel__mes_query_status__sdma1_queue = 3
282};
283
284struct pm4_query_status {
285	union {
286		union PM4_MES_TYPE_3_HEADER header;	/* header */
287		uint32_t ordinal1;
288	};
289
290	union {
291		struct {
292			uint32_t context_id:28;
293			enum query_status_interrupt_sel_enum interrupt_sel:2;
294			enum query_status_command_enum command:2;
295		} bitfields2;
296		uint32_t ordinal2;
297	};
298
299	union {
300		struct {
301			uint32_t pasid:16;
302			uint32_t reserved1:16;
303		} bitfields3a;
304		struct {
305			uint32_t reserved2:2;
306			uint32_t doorbell_offset:21;
307			uint32_t reserved3:3;
308			enum query_status_engine_sel_enum engine_sel:3;
309			uint32_t reserved4:3;
310		} bitfields3b;
311		uint32_t ordinal3;
312	};
313
314	uint32_t addr_lo;
315	uint32_t addr_hi;
316	uint32_t data_lo;
317	uint32_t data_hi;
318};
319#endif
320
321/*--------------------MES_UNMAP_QUEUES--------------------*/
322
323#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
324#define PM4_MES_UNMAP_QUEUES_DEFINED
325enum unmap_queues_action_enum {
326	action__mes_unmap_queues__preempt_queues = 0,
327	action__mes_unmap_queues__reset_queues = 1,
328	action__mes_unmap_queues__disable_process_queues = 2
329};
330
331enum unmap_queues_queue_sel_enum {
332	queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
333	queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
334	queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2,
335	queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3
336};
337
338enum unmap_queues_engine_sel_enum {
339	engine_sel__mes_unmap_queues__compute = 0,
340	engine_sel__mes_unmap_queues__sdma0 = 2,
341	engine_sel__mes_unmap_queues__sdma1 = 3
342};
343
344struct pm4_unmap_queues {
345	union {
346		union PM4_MES_TYPE_3_HEADER header;	/* header */
347		uint32_t ordinal1;
348	};
349
350	union {
351		struct {
352			enum unmap_queues_action_enum action:2;
353			uint32_t reserved1:2;
354			enum unmap_queues_queue_sel_enum queue_sel:2;
355			uint32_t reserved2:20;
356			enum unmap_queues_engine_sel_enum engine_sel:3;
357			uint32_t num_queues:3;
358		} bitfields2;
359		uint32_t ordinal2;
360	};
361
362	union {
363		struct {
364			uint32_t pasid:16;
365			uint32_t reserved3:16;
366		} bitfields3a;
367		struct {
368			uint32_t reserved4:2;
369			uint32_t doorbell_offset0:21;
370			uint32_t reserved5:9;
371		} bitfields3b;
372		uint32_t ordinal3;
373	};
374
375	union {
376		struct {
377			uint32_t reserved6:2;
378			uint32_t doorbell_offset1:21;
379			uint32_t reserved7:9;
380		} bitfields4;
381		uint32_t ordinal4;
382	};
383
384	union {
385		struct {
386			uint32_t reserved8:2;
387			uint32_t doorbell_offset2:21;
388			uint32_t reserved9:9;
389		} bitfields5;
390		uint32_t ordinal5;
391	};
392
393	union {
394		struct {
395			uint32_t reserved10:2;
396			uint32_t doorbell_offset3:21;
397			uint32_t reserved11:9;
398		} bitfields6;
399		uint32_t ordinal6;
400	};
401
402};
403#endif
404
405enum {
406	CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
407};
408
409#endif /* KFD_PM4_HEADERS_H_ */
410