1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#ifndef _I915_DRV_H_ 31#define _I915_DRV_H_ 32 33#include "i915_reg.h" 34 35/* General customization: 36 */ 37 38#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 39 40#define DRIVER_NAME "i915" 41#define DRIVER_DESC "Intel Graphics" 42#define DRIVER_DATE "20080730" 43 44enum pipex { 45 PIPE_A = 0, 46 PIPE_B, 47}; 48 49#define I915_NUM_PIPE 2 50 51/* Interface history: 52 * 53 * 1.1: Original. 54 * 1.2: Add Power Management 55 * 1.3: Add vblank support 56 * 1.4: Fix cmdbuffer path, add heap destroy 57 * 1.5: Add vblank pipe configuration 58 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 59 * - Support vertical blank on secondary display pipe 60 */ 61#define DRIVER_MAJOR 1 62#define DRIVER_MINOR 6 63#define DRIVER_PATCHLEVEL 0 64 65#define WATCH_COHERENCY 0 66#define WATCH_BUF 0 67#define WATCH_EXEC 0 68#define WATCH_LRU 0 69#define WATCH_RELOC 0 70#define WATCH_INACTIVE 0 71#define WATCH_PWRITE 0 72 73typedef struct _drm_i915_ring_buffer { 74 int tail_mask; 75 unsigned long Size; 76 u8 *virtual_start; 77 int head; 78 int tail; 79 int space; 80 drm_local_map_t map; 81 struct drm_gem_object *ring_obj; 82} drm_i915_ring_buffer_t; 83 84struct mem_block { 85 struct mem_block *next; 86 struct mem_block *prev; 87 int start; 88 int size; 89 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 90}; 91 92struct opregion_header; 93struct opregion_acpi; 94struct opregion_swsci; 95struct opregion_asle; 96 97struct intel_opregion { 98 struct opregion_header *header; 99 struct opregion_acpi *acpi; 100 struct opregion_swsci *swsci; 101 struct opregion_asle *asle; 102 int enabled; 103}; 104 105typedef struct drm_i915_private { 106 struct drm_device *dev; 107 108 drm_local_map_t *sarea; 109 drm_local_map_t *mmio_map; 110 111 drm_i915_sarea_t *sarea_priv; 112 drm_i915_ring_buffer_t ring; 113 114 drm_dma_handle_t *status_page_dmah; 115 void *hw_status_page; 116 dma_addr_t dma_status_page; 117 uint32_t counter; 118 unsigned int status_gfx_addr; 119 drm_local_map_t hws_map; 120 struct drm_gem_object *hws_obj; 121 122 unsigned int cpp; 123 int back_offset; 124 int front_offset; 125 int current_page; 126 int page_flipping; 127 128 wait_queue_head_t irq_queue; 129 atomic_t irq_received; 130 /** Protects user_irq_refcount and irq_mask_reg */ 131 DRM_SPINTYPE user_irq_lock; 132 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 133 int user_irq_refcount; 134 /** Cached value of IER to avoid reads in updating the bitfield */ 135 u32 irq_mask_reg; 136 u32 pipestat[2]; 137 138 int tex_lru_log_granularity; 139 int allow_batchbuffer; 140 struct mem_block *agp_heap; 141 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 142 int vblank_pipe; 143 144 struct intel_opregion opregion; 145 146 /* Register state */ 147 u8 saveLBB; 148 u32 saveDSPACNTR; 149 u32 saveDSPBCNTR; 150 u32 saveDSPARB; 151 u32 savePIPEACONF; 152 u32 savePIPEBCONF; 153 u32 savePIPEASRC; 154 u32 savePIPEBSRC; 155 u32 saveFPA0; 156 u32 saveFPA1; 157 u32 saveDPLL_A; 158 u32 saveDPLL_A_MD; 159 u32 saveHTOTAL_A; 160 u32 saveHBLANK_A; 161 u32 saveHSYNC_A; 162 u32 saveVTOTAL_A; 163 u32 saveVBLANK_A; 164 u32 saveVSYNC_A; 165 u32 saveBCLRPAT_A; 166 u32 savePIPEASTAT; 167 u32 saveDSPASTRIDE; 168 u32 saveDSPASIZE; 169 u32 saveDSPAPOS; 170 u32 saveDSPAADDR; 171 u32 saveDSPASURF; 172 u32 saveDSPATILEOFF; 173 u32 savePFIT_PGM_RATIOS; 174 u32 saveBLC_PWM_CTL; 175 u32 saveBLC_PWM_CTL2; 176 u32 saveFPB0; 177 u32 saveFPB1; 178 u32 saveDPLL_B; 179 u32 saveDPLL_B_MD; 180 u32 saveHTOTAL_B; 181 u32 saveHBLANK_B; 182 u32 saveHSYNC_B; 183 u32 saveVTOTAL_B; 184 u32 saveVBLANK_B; 185 u32 saveVSYNC_B; 186 u32 saveBCLRPAT_B; 187 u32 savePIPEBSTAT; 188 u32 saveDSPBSTRIDE; 189 u32 saveDSPBSIZE; 190 u32 saveDSPBPOS; 191 u32 saveDSPBADDR; 192 u32 saveDSPBSURF; 193 u32 saveDSPBTILEOFF; 194 u32 saveVGA0; 195 u32 saveVGA1; 196 u32 saveVGA_PD; 197 u32 saveVGACNTRL; 198 u32 saveADPA; 199 u32 saveLVDS; 200 u32 savePP_ON_DELAYS; 201 u32 savePP_OFF_DELAYS; 202 u32 saveDVOA; 203 u32 saveDVOB; 204 u32 saveDVOC; 205 u32 savePP_ON; 206 u32 savePP_OFF; 207 u32 savePP_CONTROL; 208 u32 savePP_DIVISOR; 209 u32 savePFIT_CONTROL; 210 u32 save_palette_a[256]; 211 u32 save_palette_b[256]; 212 u32 saveFBC_CFB_BASE; 213 u32 saveFBC_LL_BASE; 214 u32 saveFBC_CONTROL; 215 u32 saveFBC_CONTROL2; 216 u32 saveIER; 217 u32 saveIIR; 218 u32 saveIMR; 219 u32 saveCACHE_MODE_0; 220 u32 saveD_STATE; 221 u32 saveCG_2D_DIS; 222 u32 saveMI_ARB_STATE; 223 u32 saveSWF0[16]; 224 u32 saveSWF1[16]; 225 u32 saveSWF2[3]; 226 u8 saveMSR; 227 u8 saveSR[8]; 228 u8 saveGR[25]; 229 u8 saveAR_INDEX; 230 u8 saveAR[21]; 231 u8 saveDACMASK; 232 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 233 u8 saveCR[37]; 234 struct { 235 /** 236 * List of objects currently involved in rendering from the 237 * ringbuffer. 238 * 239 * A reference is held on the buffer while on this list. 240 */ 241 struct list_head active_list; 242 243 /** 244 * List of objects which are not in the ringbuffer but which 245 * still have a write_domain which needs to be flushed before 246 * unbinding. 247 * 248 * A reference is held on the buffer while on this list. 249 */ 250 struct list_head flushing_list; 251 252 /** 253 * LRU list of objects which are not in the ringbuffer and 254 * are ready to unbind, but are still in the GTT. 255 * 256 * A reference is not held on the buffer while on this list, 257 * as merely being GTT-bound shouldn't prevent its being 258 * freed, and we'll pull it off the list in the free path. 259 */ 260 struct list_head inactive_list; 261 262 /** 263 * List of breadcrumbs associated with GPU requests currently 264 * outstanding. 265 */ 266 struct list_head request_list; 267 uint32_t next_gem_seqno; 268 269 /** 270 * Waiting sequence number, if any 271 */ 272 uint32_t waiting_gem_seqno; 273 274 /** 275 * Last seq seen at irq time 276 */ 277 uint32_t irq_gem_seqno; 278 279 /** 280 * Flag if the X Server, and thus DRM, is not currently in 281 * control of the device. 282 * 283 * This is set between LeaveVT and EnterVT. It needs to be 284 * replaced with a semaphore. It also needs to be 285 * transitioned away from for kernel modesetting. 286 */ 287 int suspended; 288 289 /** 290 * Flag if the hardware appears to be wedged. 291 * 292 * This is set when attempts to idle the device timeout. 293 * It prevents command submission from occuring and makes 294 * every pending request fail 295 */ 296 int wedged; 297 298 /** Bit 6 swizzling required for X tiling */ 299 uint32_t bit_6_swizzle_x; 300 /** Bit 6 swizzling required for Y tiling */ 301 uint32_t bit_6_swizzle_y; 302 } mm; 303} drm_i915_private_t; 304 305enum intel_chip_family { 306 CHIP_I8XX = 0x01, 307 CHIP_I9XX = 0x02, 308 CHIP_I915 = 0x04, 309 CHIP_I965 = 0x08, 310}; 311 312/** driver private structure attached to each drm_gem_object */ 313struct drm_i915_gem_object { 314 struct drm_gem_object *obj; 315 316 /** Current space allocated to this object in the GTT, if any. */ 317 struct drm_mm_node *gtt_space; 318 319 /** This object's place on the active/flushing/inactive lists */ 320 struct list_head list; 321 322 /** 323 * This is set if the object is on the active or flushing lists 324 * (has pending rendering), and is not set if it's on inactive (ready 325 * to be unbound). 326 */ 327 int active; 328 329 /** 330 * This is set if the object has been written to since last bound 331 * to the GTT 332 */ 333 int dirty; 334 335 /** AGP memory structure for our GTT binding. */ 336 DRM_AGP_MEM *agp_mem; 337 338 struct page **page_list; 339 340 /** 341 * Current offset of the object in GTT space. 342 * 343 * This is the same as gtt_space->start 344 */ 345 uint32_t gtt_offset; 346 347 /** Boolean whether this object has a valid gtt offset. */ 348 int gtt_bound; 349 350 /** How many users have pinned this object in GTT space */ 351 int pin_count; 352 353 /** Breadcrumb of last rendering to the buffer. */ 354 uint32_t last_rendering_seqno; 355 356 /** Current tiling mode for the object. */ 357 uint32_t tiling_mode; 358 359 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 360 uint32_t agp_type; 361 362 /** 363 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 364 * GEM_DOMAIN_CPU is not in the object's read domain. 365 */ 366 uint8_t *page_cpu_valid; 367}; 368 369/** 370 * Request queue structure. 371 * 372 * The request queue allows us to note sequence numbers that have been emitted 373 * and may be associated with active buffers to be retired. 374 * 375 * By keeping this list, we can avoid having to do questionable 376 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 377 * an emission time with seqnos for tracking how far ahead of the GPU we are. 378 */ 379struct drm_i915_gem_request { 380 /** GEM sequence number associated with this request. */ 381 uint32_t seqno; 382 383 /** Time at which this request was emitted, in jiffies. */ 384 unsigned long emitted_jiffies; 385 386 /** Cache domains that were flushed at the start of the request. */ 387 uint32_t flush_domains; 388 389 struct list_head list; 390}; 391 392struct drm_i915_file_private { 393 struct { 394 uint32_t last_gem_seqno; 395 uint32_t last_gem_throttle_seqno; 396 } mm; 397}; 398 399extern struct drm_ioctl_desc i915_ioctls[]; 400extern int i915_max_ioctl; 401 402 /* i915_dma.c */ 403extern void i915_kernel_lost_context(struct drm_device * dev); 404extern int i915_driver_load(struct drm_device *, unsigned long flags); 405extern int i915_driver_unload(struct drm_device *); 406extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 407extern void i915_driver_lastclose(struct drm_device * dev); 408extern void i915_driver_preclose(struct drm_device *dev, 409 struct drm_file *file_priv); 410extern void i915_driver_postclose(struct drm_device *dev, 411 struct drm_file *file_priv); 412extern int i915_driver_device_is_agp(struct drm_device * dev); 413extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 414 unsigned long arg); 415extern int i915_emit_box(struct drm_device *dev, 416 struct drm_clip_rect __user *boxes, 417 int i, int DR1, int DR4); 418 419/* i915_irq.c */ 420extern int i915_irq_emit(struct drm_device *dev, void *data, 421 struct drm_file *file_priv); 422extern int i915_irq_wait(struct drm_device *dev, void *data, 423 struct drm_file *file_priv); 424void i915_user_irq_get(struct drm_device *dev); 425void i915_user_irq_put(struct drm_device *dev); 426 427extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 428extern void i915_driver_irq_preinstall(struct drm_device * dev); 429extern int i915_driver_irq_postinstall(struct drm_device *dev); 430extern void i915_driver_irq_uninstall(struct drm_device * dev); 431extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 432 struct drm_file *file_priv); 433extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 434 struct drm_file *file_priv); 435extern int i915_enable_vblank(struct drm_device *dev, unsigned int crtc); 436extern void i915_disable_vblank(struct drm_device *dev, unsigned int crtc); 437extern u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int crtc); 438extern u32 gm45_get_vblank_counter(struct drm_device *dev, unsigned int crtc); 439extern int i915_vblank_swap(struct drm_device *dev, void *data, 440 struct drm_file *file_priv); 441 442void 443i915_enable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask); 444 445void 446i915_disable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask); 447 448 449/* i915_mem.c */ 450extern int i915_mem_alloc(struct drm_device *dev, void *data, 451 struct drm_file *file_priv); 452extern int i915_mem_free(struct drm_device *dev, void *data, 453 struct drm_file *file_priv); 454extern int i915_mem_init_heap(struct drm_device *dev, void *data, 455 struct drm_file *file_priv); 456extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 457 struct drm_file *file_priv); 458extern void i915_mem_takedown(struct mem_block **heap); 459extern void i915_mem_release(struct drm_device * dev, 460 struct drm_file *file_priv, struct mem_block *heap); 461#ifdef I915_HAVE_GEM 462/* i915_gem.c */ 463int i915_gem_init_ioctl(struct drm_device *dev, void *data, 464 struct drm_file *file_priv); 465int i915_gem_create_ioctl(struct drm_device *dev, void *data, 466 struct drm_file *file_priv); 467int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 468 struct drm_file *file_priv); 469int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 470 struct drm_file *file_priv); 471int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 472 struct drm_file *file_priv); 473int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 474 struct drm_file *file_priv); 475int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 476 struct drm_file *file_priv); 477int i915_gem_execbuffer(struct drm_device *dev, void *data, 478 struct drm_file *file_priv); 479int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 480 struct drm_file *file_priv); 481int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 482 struct drm_file *file_priv); 483int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 484 struct drm_file *file_priv); 485int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 486 struct drm_file *file_priv); 487int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 488 struct drm_file *file_priv); 489int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *file_priv); 491int i915_gem_set_tiling(struct drm_device *dev, void *data, 492 struct drm_file *file_priv); 493int i915_gem_get_tiling(struct drm_device *dev, void *data, 494 struct drm_file *file_priv); 495void i915_gem_load(struct drm_device *dev); 496int i915_gem_proc_init(struct drm_minor *minor); 497void i915_gem_proc_cleanup(struct drm_minor *minor); 498int i915_gem_init_object(struct drm_gem_object *obj); 499void i915_gem_free_object(struct drm_gem_object *obj); 500int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 501void i915_gem_object_unpin(struct drm_gem_object *obj); 502void i915_gem_lastclose(struct drm_device *dev); 503uint32_t i915_get_gem_seqno(struct drm_device *dev); 504void i915_gem_retire_requests(struct drm_device *dev); 505void i915_gem_retire_work_handler(struct work_struct *work); 506void i915_gem_clflush_object(struct drm_gem_object *obj); 507 508/* i915_gem_tiling.c */ 509void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 510 511/* i915_gem_debug.c */ 512void i915_gem_dump_object(struct drm_gem_object *obj, int len, 513 const char *where, uint32_t mark); 514#if WATCH_INACTIVE 515void i915_verify_inactive(struct drm_device *dev, char *file, int line); 516#else 517#define i915_verify_inactive(dev, file, line) 518#endif 519void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 520void i915_gem_dump_object(struct drm_gem_object *obj, int len, 521 const char *where, uint32_t mark); 522void i915_dump_lru(struct drm_device *dev, const char *where); 523#endif /* I915_HAVE_GEM */ 524 525/* i915_suspend.c */ 526extern int i915_save_state(struct drm_device *dev); 527extern int i915_restore_state(struct drm_device *dev); 528 529/* i915_opregion.c */ 530extern int intel_opregion_init(struct drm_device *dev); 531extern void intel_opregion_free(struct drm_device *dev); 532extern void opregion_asle_intr(struct drm_device *dev); 533extern void opregion_enable_asle(struct drm_device *dev); 534 535/** 536 * Lock test for when it's just for synchronization of ring access. 537 * 538 * In that case, we don't need to do it when GEM is initialized as nobody else 539 * has access to the ring. 540 */ 541#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 542 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 543 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 544} while (0) 545 546#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 547#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 548#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 549#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 550#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 551#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 552 553#define I915_VERBOSE 0 554 555#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 556 volatile char *virt; 557 558#define BEGIN_LP_RING(n) do { \ 559 if (I915_VERBOSE) \ 560 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 561 if (dev_priv->ring.space < (n)*4) \ 562 i915_wait_ring(dev, (n)*4, __func__); \ 563 outcount = 0; \ 564 outring = dev_priv->ring.tail; \ 565 ringmask = dev_priv->ring.tail_mask; \ 566 virt = dev_priv->ring.virtual_start; \ 567} while (0) 568 569#define OUT_RING(n) do { \ 570 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 571 *(volatile unsigned int *)(virt + outring) = (n); \ 572 outcount++; \ 573 outring += 4; \ 574 outring &= ringmask; \ 575} while (0) 576 577#define ADVANCE_LP_RING() do { \ 578 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 579 dev_priv->ring.tail = outring; \ 580 dev_priv->ring.space -= outcount * 4; \ 581 I915_WRITE(PRB0_TAIL, outring); \ 582} while(0) 583 584/** 585 * Reads a dword out of the status page, which is written to from the command 586 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 587 * MI_STORE_DATA_IMM. 588 * 589 * The following dwords have a reserved meaning: 590 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 591 * 0x04: ring 0 head pointer 592 * 0x05: ring 1 head pointer (915-class) 593 * 0x06: ring 2 head pointer (915-class) 594 * 0x10-0x1b: Context status DWords (GM45) 595 * 0x1f: Last written status offset. (GM45) 596 * 597 * The area from dword 0x20 to 0x3ff is available for driver usage. 598 */ 599#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 600#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 601#define I915_GEM_HWS_INDEX 0x20 602#define I915_BREADCRUMB_INDEX 0x21 603 604extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 605 606#define IS_I830(dev) ((dev)->pci_device == 0x3577) 607#define IS_845G(dev) ((dev)->pci_device == 0x2562) 608#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 609#define IS_I855(dev) ((dev)->pci_device == 0x3582) 610#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 611 612#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 613#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 614#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 615#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 616 (dev)->pci_device == 0x27AE) 617#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 618 (dev)->pci_device == 0x2982 || \ 619 (dev)->pci_device == 0x2992 || \ 620 (dev)->pci_device == 0x29A2 || \ 621 (dev)->pci_device == 0x2A02 || \ 622 (dev)->pci_device == 0x2A12 || \ 623 (dev)->pci_device == 0x2A42 || \ 624 (dev)->pci_device == 0x2E02 || \ 625 (dev)->pci_device == 0x2E12 || \ 626 (dev)->pci_device == 0x2E22) 627 628#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 629 630#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 631 632#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 633 (dev)->pci_device == 0x2E12 || \ 634 (dev)->pci_device == 0x2E22) 635 636#define IS_IGDG(dev) ((dev)->pci_device == 0xA001) 637#define IS_IGDGM(dev) ((dev)->pci_device == 0xA011) 638#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 639 640#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 641 (dev)->pci_device == 0x29B2 || \ 642 (dev)->pci_device == 0x29D2 || \ 643 IS_IGD(dev)) 644 645#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 646 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 647 648#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 649 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 650 IS_IGD(dev)) 651 652#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 653 654#define PRIMARY_RINGBUFFER_SIZE (128*1024) 655 656#endif 657