xhcivar.h revision 1.9 
1/*	$NetBSD: xhcivar.h,v 1.9 2018/04/09 16:21:11 jakllsch Exp $	*/
2
3/*
4 * Copyright (c) 2013 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _DEV_USB_XHCIVAR_H_
30#define _DEV_USB_XHCIVAR_H_
31
32#include <sys/pool.h>
33
34#define XHCI_XFER_NTRB	20
35
36struct xhci_xfer {
37	struct usbd_xfer xx_xfer;
38	struct usb_task xx_abort_task;
39	struct xhci_trb xx_trb[XHCI_XFER_NTRB];
40};
41
42#define XHCI_BUS2SC(bus)	((bus)->ub_hcpriv)
43#define XHCI_PIPE2SC(pipe)	XHCI_BUS2SC((pipe)->up_dev->ud_bus)
44#define XHCI_XFER2SC(xfer)	XHCI_BUS2SC((xfer)->ux_bus)
45#define XHCI_XFER2BUS(xfer)	((xfer)->ux_bus)
46#define XHCI_XPIPE2SC(d)	XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
47
48#define XHCI_XFER2XXFER(xfer)	((struct xhci_xfer *)(xfer))
49
50struct xhci_ring {
51	usb_dma_t xr_dma;
52	kmutex_t xr_lock;
53	struct xhci_trb * xr_trb;
54	void **xr_cookies;
55	u_int xr_ntrb;			/* number of elements for above */
56	u_int xr_ep;			/* enqueue pointer */
57	u_int xr_cs;			/* cycle state */
58	bool is_halted;
59};
60
61struct xhci_endpoint {
62	struct xhci_ring xe_tr;		/* transfer ring */
63};
64
65struct xhci_slot {
66	usb_dma_t xs_dc_dma;		/* device context page */
67	usb_dma_t xs_ic_dma;		/* input context page */
68	struct xhci_endpoint xs_ep[32]; /* endpoints */
69	u_int xs_idx;			/* slot index */
70};
71
72struct xhci_softc {
73	device_t sc_dev;
74	device_t sc_child;
75	device_t sc_child2;
76	bus_size_t sc_ios;
77	bus_space_tag_t sc_iot;
78	bus_space_handle_t sc_ioh;	/* Base */
79	bus_space_handle_t sc_cbh;	/* Capability Base */
80	bus_space_handle_t sc_obh;	/* Operational Base */
81	bus_space_handle_t sc_rbh;	/* Runtime Base */
82	bus_space_handle_t sc_dbh;	/* Doorbell Registers */
83	struct usbd_bus sc_bus;		/* USB 3 bus */
84	struct usbd_bus sc_bus2;	/* USB 2 bus */
85
86	kmutex_t sc_lock;
87	kmutex_t sc_intr_lock;
88	kcondvar_t sc_softwake_cv;
89
90	pool_cache_t sc_xferpool;
91
92	bus_size_t sc_pgsz;		/* xHCI page size */
93	uint32_t sc_ctxsz;
94	int sc_maxslots;
95	int sc_maxintrs;
96	int sc_maxspbuf;
97
98	/*
99	 * Port routing and root hub - xHCI 4.19.7
100	 */
101	int sc_maxports;		/* number of controller ports */
102
103	uint8_t *sc_ctlrportbus;	/* a bus bit per port */
104
105	int *sc_ctlrportmap;
106	int *sc_rhportmap[2];
107	int sc_rhportcount[2];
108	struct usbd_xfer *sc_intrxfer[2];
109
110
111	struct xhci_slot * sc_slots;
112
113	struct xhci_ring sc_cr;		/* command ring */
114	struct xhci_ring sc_er;		/* event ring */
115
116	usb_dma_t sc_eventst_dma;
117	usb_dma_t sc_dcbaa_dma;
118	usb_dma_t sc_spbufarray_dma;
119	usb_dma_t *sc_spbuf_dma;
120
121	kcondvar_t sc_cmdbusy_cv;
122	kcondvar_t sc_command_cv;
123	bus_addr_t sc_command_addr;
124	struct xhci_trb sc_result_trb;
125	bool sc_resultpending;
126
127	bool sc_ac64;
128	bool sc_dying;
129
130	void (*sc_vendor_init)(struct xhci_softc *);
131	int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
132
133	int sc_quirks;
134#define XHCI_QUIRK_INTEL	__BIT(0) /* Intel xhci chip */
135#define XHCI_DEFERRED_START	__BIT(1)
136};
137
138int	xhci_init(struct xhci_softc *);
139void	xhci_start(struct xhci_softc *);
140int	xhci_intr(void *);
141int	xhci_detach(struct xhci_softc *, int);
142int	xhci_activate(device_t, enum devact);
143void	xhci_childdet(device_t, device_t);
144bool	xhci_suspend(device_t, const pmf_qual_t *);
145bool	xhci_resume(device_t, const pmf_qual_t *);
146bool	xhci_shutdown(device_t, int);
147
148#define XHCI_TRANSFER_RING_TRBS 256
149
150#endif /* _DEV_USB_XHCIVAR_H_ */
151