xhcivar.h revision 1.19 
1/*	$NetBSD: xhcivar.h,v 1.19 2021/05/23 21:12:28 riastradh Exp $	*/
2
3/*
4 * Copyright (c) 2013 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _DEV_USB_XHCIVAR_H_
30#define _DEV_USB_XHCIVAR_H_
31
32#include <sys/pool.h>
33
34#define XHCI_MAX_DCI	31
35
36struct xhci_soft_trb {
37	uint64_t trb_0;
38	uint32_t trb_2;
39	uint32_t trb_3;
40};
41
42struct xhci_xfer {
43	struct usbd_xfer xx_xfer;
44	struct xhci_soft_trb *xx_trb;
45	u_int xx_ntrb;
46	u_int xx_isoc_done;
47};
48
49#define XHCI_BUS2SC(bus)	((bus)->ub_hcpriv)
50#define XHCI_PIPE2SC(pipe)	XHCI_BUS2SC((pipe)->up_dev->ud_bus)
51#define XHCI_XFER2SC(xfer)	XHCI_BUS2SC((xfer)->ux_bus)
52#define XHCI_XFER2BUS(xfer)	((xfer)->ux_bus)
53#define XHCI_XPIPE2SC(d)	XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
54
55#define XHCI_XFER2XXFER(xfer)	((struct xhci_xfer *)(xfer))
56
57struct xhci_ring {
58	usb_dma_t xr_dma;
59	kmutex_t xr_lock;
60	struct xhci_trb * xr_trb;
61	void **xr_cookies;
62	u_int xr_ntrb;			/* number of elements for above */
63	u_int xr_ep;			/* enqueue pointer */
64	u_int xr_cs;			/* cycle state */
65	bool is_halted;
66};
67
68struct xhci_slot {
69	usb_dma_t xs_dc_dma;		/* device context page */
70	usb_dma_t xs_ic_dma;		/* input context page */
71	struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1];
72					/* transfer rings */
73	u_int xs_idx;			/* slot index */
74};
75
76struct xhci_softc {
77	device_t sc_dev;
78	device_t sc_child;
79	device_t sc_child2;
80	bus_size_t sc_ios;
81	bus_space_tag_t sc_iot;
82	bus_space_handle_t sc_ioh;	/* Base */
83	bus_space_handle_t sc_cbh;	/* Capability Base */
84	bus_space_handle_t sc_obh;	/* Operational Base */
85	bus_space_handle_t sc_rbh;	/* Runtime Base */
86	bus_space_handle_t sc_dbh;	/* Doorbell Registers */
87	struct usbd_bus sc_bus;		/* USB 3 bus */
88	struct usbd_bus sc_bus2;	/* USB 2 bus */
89
90	kmutex_t sc_lock;
91	kmutex_t sc_intr_lock;
92
93	pool_cache_t sc_xferpool;
94
95	bus_size_t sc_pgsz;		/* xHCI page size */
96	uint32_t sc_ctxsz;
97	int sc_maxslots;
98	int sc_maxintrs;
99	int sc_maxspbuf;
100
101	/*
102	 * Port routing and root hub - xHCI 4.19.7
103	 */
104	int sc_maxports;		/* number of controller ports */
105
106	uint8_t *sc_ctlrportbus;	/* a bus bit per port */
107
108	int *sc_ctlrportmap;
109	int *sc_rhportmap[2];
110	int sc_rhportcount[2];
111	struct usbd_xfer *sc_intrxfer[2];
112
113
114	struct xhci_slot * sc_slots;
115
116	struct xhci_ring *sc_cr;	/* command ring */
117	struct xhci_ring *sc_er;	/* event ring */
118
119	usb_dma_t sc_eventst_dma;
120	usb_dma_t sc_dcbaa_dma;
121	usb_dma_t sc_spbufarray_dma;
122	usb_dma_t *sc_spbuf_dma;
123
124	kcondvar_t sc_cmdbusy_cv;
125	kcondvar_t sc_command_cv;
126	bus_addr_t sc_command_addr;
127	struct xhci_soft_trb sc_result_trb;
128	bool sc_resultpending;
129
130	bool sc_dying;
131	struct lwp *sc_suspender;
132
133	void (*sc_vendor_init)(struct xhci_softc *);
134	int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
135
136	int sc_quirks;
137#define XHCI_QUIRK_INTEL	__BIT(0) /* Intel xhci chip */
138#define XHCI_DEFERRED_START	__BIT(1)
139	uint32_t sc_hcc;		/* copy of HCCPARAMS1 */
140	uint32_t sc_hcc2;		/* copy of HCCPARAMS2 */
141
142	struct xhci_registers {
143		uint32_t	usbcmd;
144		uint32_t	dnctrl;
145		uint64_t	dcbaap;
146		uint32_t	config;
147		uint32_t	erstsz0;
148		uint64_t	erstba0;
149		uint64_t	erdp0;
150		uint32_t	iman0;
151		uint32_t	imod0;
152	} sc_regs;
153};
154
155int	xhci_init(struct xhci_softc *);
156void	xhci_start(struct xhci_softc *);
157int	xhci_intr(void *);
158int	xhci_detach(struct xhci_softc *, int);
159int	xhci_activate(device_t, enum devact);
160void	xhci_childdet(device_t, device_t);
161bool	xhci_suspend(device_t, const pmf_qual_t *);
162bool	xhci_resume(device_t, const pmf_qual_t *);
163bool	xhci_shutdown(device_t, int);
164
165#define XHCI_TRANSFER_RING_TRBS 256
166
167#endif /* _DEV_USB_XHCIVAR_H_ */
168