1/* $NetBSD: xhcireg.h,v 1.24 2024/02/10 09:21:53 andvar Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#ifndef _DEV_USB_XHCIREG_H_ 29#define _DEV_USB_XHCIREG_H_ 30 31/* XHCI PCI config registers */ 32#define PCI_CBMEM 0x10 /* configuration base MEM */ 33#define PCI_INTERFACE_XHCI 0x30 34 35#define PCI_USBREV 0x60 /* RO USB protocol revision */ 36#define PCI_USBREV_MASK 0xFF 37#define PCI_USBREV_3_0 0x30 /* USB 3.0 */ 38#define PCI_USBREV_3_1 0x31 /* USB 3.1 */ 39 40#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 41 42#define PCI_XHCI_INTEL_XUSB2PR 0xd0 /* Intel USB2 Port Routing */ 43#define PCI_XHCI_INTEL_USB2PRM 0xd4 /* Intel USB2 Port Routing Mask */ 44#define PCI_XHCI_INTEL_USB3_PSSEN 0xd8 /* Intel USB3 Port SuperSpeed Enable */ 45#define PCI_XHCI_INTEL_USB3PRM 0xdc /* Intel USB3 Port Routing Mask */ 46 47/* XHCI capability registers */ 48#define XHCI_CAPLENGTH 0x00 /* RO capability - 1 byte */ 49#define XHCI_HCIVERSION 0x02 /* RO version - 2 bytes */ 50#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 51#define XHCI_HCIVERSION_0_96 0x0096 /* xHCI version 0.96 */ 52#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 53#define XHCI_HCIVERSION_1_1 0x0110 /* xHCI version 1.1 */ 54#define XHCI_HCIVERSION_1_2 0x0120 /* xHCI version 1.2 */ 55 56#define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */ 57#define XHCI_HCS1_MAXSLOTS_MASK __BITS(7, 0) 58#define XHCI_HCS1_MAXSLOTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXSLOTS_MASK) 59#define XHCI_HCS1_MAXINTRS_MASK __BITS(18, 8) 60#define XHCI_HCS1_MAXINTRS(x) __SHIFTOUT((x), XHCI_HCS1_MAXINTRS_MASK) 61#define XHCI_HCS1_MAXPORTS_MASK __BITS(31, 24) 62#define XHCI_HCS1_MAXPORTS(x) __SHIFTOUT((x), XHCI_HCS1_MAXPORTS_MASK) 63 64#define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */ 65#define XHCI_HCS2_IST_MASK __BITS(3, 0) 66#define XHCI_HCS2_IST(x) __SHIFTOUT((x), XHCI_HCS2_IST_MASK) 67#define XHCI_HCS2_ERSTMAX_MASK __BITS(7, 4) 68#define XHCI_HCS2_ERSTMAX(x) __SHIFTOUT((x), XHCI_HCS2_ERSTMAX_MASK) 69#define XHCI_HCS2_SPBUFHI_MASK __BITS(25, 21) 70#define XHCI_HCS2_SPR_MASK __BIT(26) 71#define XHCI_HCS2_SPR(x) __SHIFTOUT((x), XHCI_HCS2_SPR_MASK) 72#define XHCI_HCS2_SPBUFLO_MASK __BITS(31, 27) 73#define XHCI_HCS2_MAXSPBUF(x) \ 74 (__SHIFTOUT((x), XHCI_HCS2_SPBUFHI_MASK) << 5) | \ 75 (__SHIFTOUT((x), XHCI_HCS2_SPBUFLO_MASK)) 76 77#define XHCI_HCSPARAMS3 0x0c /* RO structural parameters 3 */ 78#define XHCI_HCS3_U1_DEL_MASK __BITS(7, 0) 79#define XHCI_HCS3_U1_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U1_DEL_MASK) 80#define XHCI_HCS3_U2_DEL_MASK __BITS(15, 8) 81#define XHCI_HCS3_U2_DEL(x) __SHIFTOUT((x), XHCI_HCS3_U2_DEL_MASK) 82 83#define XHCI_HCCPARAMS 0x10 /* RO capability parameters */ 84#define XHCI_HCC_AC64(x) __SHIFTOUT((x), __BIT(0)) /* 64-bit capable */ 85#define XHCI_HCC_BNC(x) __SHIFTOUT((x), __BIT(1)) /* BW negotiation */ 86#define XHCI_HCC_CSZ(x) __SHIFTOUT((x), __BIT(2)) /* context size */ 87#define XHCI_HCC_PPC(x) __SHIFTOUT((x), __BIT(3)) /* port power control */ 88#define XHCI_HCC_PIND(x) __SHIFTOUT((x), __BIT(4)) /* port indicators */ 89#define XHCI_HCC_LHRC(x) __SHIFTOUT((x), __BIT(5)) /* light HC reset */ 90#define XHCI_HCC_LTC(x) __SHIFTOUT((x), __BIT(6)) /* latency tolerance msg */ 91#define XHCI_HCC_NSS(x) __SHIFTOUT((x), __BIT(7)) /* no secondary sid */ 92#define XHCI_HCC_PAE(x) __SHIFTOUT((x), __BIT(8)) /* Parse All Event Data */ 93#define XHCI_HCC_SPC(x) __SHIFTOUT((x), __BIT(9)) /* Short packet */ 94#define XHCI_HCC_SEC(x) __SHIFTOUT((x), __BIT(10)) /* Stopped EDTLA */ 95#define XHCI_HCC_CFC(x) __SHIFTOUT((x), __BIT(11)) /* Contiguous Frame ID */ 96#define XHCI_HCC_MAXPSASIZE_MASK __BITS(15, 12) /* max pri. stream array size */ 97#define XHCI_HCC_MAXPSASIZE(x) __SHIFTOUT((x), XHCI_HCC_MAXPSASIZE_MASK) 98#define XHCI_HCC_XECP_MASK __BITS(31, 16) /* extended capabilities pointer */ 99#define XHCI_HCC_XECP(x) __SHIFTOUT((x), XHCI_HCC_XECP_MASK) 100 101#define XHCI_DBOFF 0x14 /* RO doorbell offset */ 102#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 103#define XHCI_HCCPARAMS2 0x1c /* RO capability parameters 2 */ 104#define XHCI_HCC2_U3C(x) __SHIFTOUT((x), __BIT(0)) /* U3 Entry capable */ 105#define XHCI_HCC2_CMC(x) __SHIFTOUT((x), __BIT(1)) /* CEC MaxExLatTooLg */ 106#define XHCI_HCC2_FSC(x) __SHIFTOUT((x), __BIT(2)) /* Foce Save Context */ 107#define XHCI_HCC2_CTC(x) __SHIFTOUT((x), __BIT(3)) /* Compliance Transc */ 108#define XHCI_HCC2_LEC(x) __SHIFTOUT((x), __BIT(4)) /* Large ESIT Payload */ 109#define XHCI_HCC2_CIC(x) __SHIFTOUT((x), __BIT(5)) /* Configuration Inf */ 110#define XHCI_HCC2_ETC(x) __SHIFTOUT((x), __BIT(6)) /* Extended TBC */ 111#define XHCI_HCC2_ETC_TSC(x) __SHIFTOUT((x), __BIT(7)) /* ExtTBC TRB Status */ 112#define XHCI_HCC2_GSC(x) __SHIFTOUT((x), __BIT(8)) /* Get/Set Extended Property */ 113#define XHCI_HCC2_VTC(x) __SHIFTOUT((x), __BIT(9)) /* Virt. Based Trust */ 114 115#define XHCI_VTIOSOFF 0x20 /* RO Virtualization Base Trusted IO Offset */ 116 117/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 118#define XHCI_USBCMD 0x00 /* XHCI command */ 119#define XHCI_CMD_RS __BIT(0) /* RW Run/Stop */ 120#define XHCI_CMD_HCRST __BIT(1) /* RW Host Controller Reset */ 121#define XHCI_CMD_INTE __BIT(2) /* RW Interrupter Enable */ 122#define XHCI_CMD_HSEE __BIT(3) /* RW Host System Error Enable */ 123#define XHCI_CMD_LHCRST __BIT(7) /* RO/RW Light Host Controller Reset */ 124#define XHCI_CMD_CSS __BIT(8) /* RW Controller Save State */ 125#define XHCI_CMD_CRS __BIT(9) /* RW Controller Restore State */ 126#define XHCI_CMD_EWE __BIT(10) /* RW Enable Wrap Event */ 127#define XHCI_CMD_EU3S __BIT(11) /* RW Enable U3 MFINDEX Stop */ 128#define XHCI_CMD_CME __BIT(13) /* RW CEM Enable */ 129#define XHCI_CMD_ETE __BIT(14) /* RW Extended TBC Enable */ 130#define XHCI_CMD_TSC_EN __BIT(15) /* RW Extended TBC TRB Status Enable */ 131#define XHCI_CMD_VTIOE __BIT(16) /* RW VTIO Enable */ 132 133#define XHCI_WAIT_CNR 100 /* in 1ms */ 134#define XHCI_WAIT_HCRST 100 /* in 1ms */ 135#define XHCI_WAIT_RSS 100 /* in 1ms */ 136#define XHCI_WAIT_SSS 100 /* in 1ms */ 137#define XHCI_WAIT_PLS_U0 100 /* in 1ms */ 138#define XHCI_WAIT_PLS_U3 10 /* in 1ms */ 139 140#define XHCI_USBSTS 0x04 /* XHCI status */ 141#define XHCI_STS_HCH __BIT(0) /* RO - Host Controller Halted */ 142#define XHCI_STS_RSVDZ0 __BIT(1) /* RsvdZ - 1:1 */ 143#define XHCI_STS_HSE __BIT(2) /* RW - Host System Error */ 144#define XHCI_STS_EINT __BIT(3) /* RW - Event Interrupt */ 145#define XHCI_STS_PCD __BIT(4) /* RW - Port Change Detect */ 146#define XHCI_STS_RSVDZ1 __BITS(7, 5) /* RsvdZ - 7:5 */ 147#define XHCI_STS_SSS __BIT(8) /* RO - Save State Status */ 148#define XHCI_STS_RSS __BIT(9) /* RO - Restore State Status */ 149#define XHCI_STS_SRE __BIT(10) /* RW - Save/Restore Error */ 150#define XHCI_STS_CNR __BIT(11) /* RO - Controller Not Ready */ 151#define XHCI_STS_HCE __BIT(12) /* RO - Host Controller Error */ 152#define XHCI_STS_RSVDP0 __BITS(13, 31) /* RsvdP - 31:13 */ 153 154#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 155#define XHCI_PAGESIZE_4K __BIT(0) /* 4K Page Size */ 156#define XHCI_PAGESIZE_8K __BIT(1) /* 8K Page Size */ 157#define XHCI_PAGESIZE_16K __BIT(2) /* 16K Page Size */ 158#define XHCI_PAGESIZE_32K __BIT(3) /* 32K Page Size */ 159#define XHCI_PAGESIZE_64K __BIT(4) /* 64K Page Size */ 160#define XHCI_PAGESIZE_128K __BIT(5) /* 128K Page Size */ 161#define XHCI_PAGESIZE_256K __BIT(6) /* 256K Page Size */ 162#define XHCI_PAGESIZE_512K __BIT(7) /* 512K Page Size */ 163#define XHCI_PAGESIZE_1M __BIT(8) /* 1M Page Size */ 164#define XHCI_PAGESIZE_2M __BIT(9) /* 2M Page Size */ 165/* ... extends to 128M */ 166 167#define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 168#define XHCI_DNCTRL_MASK(n) __BIT((n)) 169 170/* 5.4.5 Command Ring Control Register */ 171#define XHCI_CRCR 0x18 /* XHCI command ring control */ 172#define XHCI_CRCR_LO_RCS __BIT(0) /* RW - consumer cycle state */ 173#define XHCI_CRCR_LO_CS __BIT(1) /* RW - command stop */ 174#define XHCI_CRCR_LO_CA __BIT(2) /* RW - command abort */ 175#define XHCI_CRCR_LO_CRR __BIT(3) /* RW - command ring running */ 176#define XHCI_CRCR_LO_MASK __BITS(31, 6) 177 178#define XHCI_CRCR_HI 0x1c /* XHCI command ring control */ 179 180/* 5.4.6 Device Context Base Address Array Pointer Registers */ 181#define XHCI_DCBAAP 0x30 /* XHCI dev context BA pointer */ 182#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 183 184/* 5.4.7 Configure Register */ 185#define XHCI_CONFIG 0x38 186#define XHCI_CONFIG_SLOTS_MASK __BITS(7, 0) /* RW - number of device slots enabled */ 187#define XHCI_CONFIG_U3E __BIT(8) /* RW - U3 Entry Enable */ 188#define XHCI_CONFIG_CIE __BIT(9) /* RW - Configuration Information Enable */ 189 190/* 5.4.8 XHCI port status registers */ 191#define XHCI_PORTSC(n) (0x3f0 + (0x10 * (n))) /* XHCI port status */ 192#define XHCI_PS_CCS __BIT(0) /* RO - current connect status */ 193#define XHCI_PS_PED __BIT(1) /* RW - port enabled / disabled */ 194#define XHCI_PS_OCA __BIT(3) /* RO - over current active */ 195#define XHCI_PS_PR __BIT(4) /* RW - port reset */ 196#define XHCI_PS_PLS_MASK __BITS(8, 5) /* RW - port link state */ 197#define XHCI_PS_PLS_GET(x) __SHIFTOUT((x), XHCI_PS_PLS_MASK) /* RW - port link state */ 198#define XHCI_PS_PLS_SET(x) __SHIFTIN((x), XHCI_PS_PLS_MASK) /* RW - port link state */ 199 200#define XHCI_PS_PLS_SETU0 0 201#define XHCI_PS_PLS_SETU2 2 202#define XHCI_PS_PLS_SETU3 3 203#define XHCI_PS_PLS_SETDISC 5 204#define XHCI_PS_PLS_SETCOMP 10 205#define XHCI_PS_PLS_SETRESUME 15 206 207#define XHCI_PS_PLS_U0 0 208#define XHCI_PS_PLS_U1 1 209#define XHCI_PS_PLS_U2 2 210#define XHCI_PS_PLS_U3 3 211#define XHCI_PS_PLS_DISABLED 4 212#define XHCI_PS_PLS_RXDETECT 5 213#define XHCI_PS_PLS_INACTIVE 6 214#define XHCI_PS_PLS_POLLING 7 215#define XHCI_PS_PLS_RECOVERY 8 216#define XHCI_PS_PLS_HOTRESET 9 217#define XHCI_PS_PLS_COMPLIANCE 10 218#define XHCI_PS_PLS_TEST 11 219#define XHCI_PS_PLS_RESUME 15 220 221#define XHCI_PS_PP __BIT(9) /* RW - port power */ 222#define XHCI_PS_SPEED_MASK __BITS(13, 10) /* RO - port speed */ 223#define XHCI_PS_SPEED_GET(x) __SHIFTOUT((x), XHCI_PS_SPEED_MASK) 224#define XHCI_PS_SPEED_FS 1 225#define XHCI_PS_SPEED_LS 2 226#define XHCI_PS_SPEED_HS 3 227#define XHCI_PS_SPEED_SS 4 228#define XHCI_PS_PIC_MASK __BITS(15, 14) /* RW - port indicator */ 229#define XHCI_PS_PIC_GET(x) __SHIFTOUT((x), XHCI_PS_PIC_MASK) 230#define XHCI_PS_PIC_SET(x) __SHIFTIN((x), XHCI_PS_PIC_MASK) 231#define XHCI_PS_LWS __BIT(16) /* RW - port link state write strobe */ 232#define XHCI_PS_CSC __BIT(17) /* RW - connect status change */ 233#define XHCI_PS_PEC __BIT(18) /* RW - port enable/disable change */ 234#define XHCI_PS_WRC __BIT(19) /* RW - warm port reset change */ 235#define XHCI_PS_OCC __BIT(20) /* RW - over-current change */ 236#define XHCI_PS_PRC __BIT(21) /* RW - port reset change */ 237#define XHCI_PS_PLC __BIT(22) /* RW - port link state change */ 238#define XHCI_PS_CEC __BIT(23) /* RW - config error change */ 239#define XHCI_PS_CAS __BIT(24) /* RO - cold attach status */ 240#define XHCI_PS_WCE __BIT(25) /* RW - wake on connect enable */ 241#define XHCI_PS_WDE __BIT(26) /* RW - wake on disconnect enable */ 242#define XHCI_PS_WOE __BIT(27) /* RW - wake on over-current enable */ 243#define XHCI_PS_DR __BIT(30) /* RO - device removable */ 244#define XHCI_PS_WPR __BIT(31) /* RW - warm port reset */ 245#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 246 247/* 5.4.9 Port PM Status and Control Register */ 248#define XHCI_PORTPMSC(n) (0x3f4 + (0x10 * (n))) /* XHCI status and control */ 249/* 5.4.9.1 */ 250#define XHCI_PM3_U1TO_MASK __BITS(7, 0) /* RW - U1 timeout */ 251#define XHCI_PM3_U1TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U1TO_MASK) 252#define XHCI_PM3_U1TO_SET(x) __SHIFTIN((x), XHCI_PM3_U1TO_MASK) 253#define XHCI_PM3_U2TO_MASK __BITS(15, 8) /* RW - U2 timeout */ 254#define XHCI_PM3_U2TO_GET(x) __SHIFTOUT((x), XHCI_PM3_U2TO_MASK) 255#define XHCI_PM3_U2TO_SET(x) __SHIFTIN((x), XHCI_PM3_U2TO_MASK) 256#define XHCI_PM3_FLA __BIT(16) /* RW - Force Link PM Accept */ 257 258/* 5.4.9.2 */ 259#define XHCI_PM2_L1S_MASK __BITS(2, 0) /* RO - L1 status */ 260#define XHCI_PM2_L1S_GET(x) __SHIFTOUT((x), XHCI_PM2_L1S_MASK) 261#define XHCI_PM2_RWE __BIT(3) /* RW - remote wakeup enable */ 262#define XHCI_PM2_BESL_MASK __BITS(7, 4) /* RW - Best Effort Service Latency */ 263#define XHCI_PM2_BESL_GET(x) __SHIFTOUT((x), XHCI_PM2_BESL_MASK) 264#define XHCI_PM2_BESL_SET(x) __SHIFTIN((x), XHCI_PM2_BESL_MASK) 265#define XHCI_PM2_L1SLOT_MASK __BITS(15, 8) /* RW - L1 device slot */ 266#define XHCI_PM2_L1SLOT_GET(x) __SHIFTOUT((x), XHCI_PM2_L1SLOT_MASK) 267#define XHCI_PM2_L1SLOT_SET(x) __SHIFTIN((x), XHCI_PM2_L1SLOT_MASK) 268#define XHCI_PM2_HLE __BIT(16) /* RW - hardware LPM enable */ 269#define XHCI_PM2_PTC_MASK __BITS(31, 28) /* RW - port test control */ 270#define XHCI_PM2_PTC_GET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK) 271#define XHCI_PM2_PTC_SET(x) __SHIFTOUT((x), XHCI_PM2_PTC_MASK) 272 273/* 5.4.10 Port Link Info Register */ 274#define XHCI_PORTLI(n) (0x3f8 + (0x10 * (n))) /* XHCI port link info */ 275/* 5.4.10.1 */ 276#define XHCI_PLI3_ERR_MASK __BITS(15, 0) /* RW - port link errors */ 277#define XHCI_PLI3_ERR_GET(x) __SHIFTOUT((x), XHCI_PLI3_ERR_MASK) 278#define XHCI_PLI3_RLC_MASK __BITS(19, 16) /* RO - Rx Lane Count */ 279#define XHCI_PLI3_RLC_GET __SHIFTOUT((x), XHCI_PLI3_RLC_MASK) 280#define XHCI_PLI3_TLC_MASK __BITS(23, 20) /* RO - Tx Lane Count */ 281#define XHCI_PLI3_TLC_GET __SHIFTOUT((x), XHCI_PLI3_TLC_MASK) 282 283/* 5.4.11 */ 284#define XHCI_PORTHLPMC(n) (0x3fc + (0x10 * (n))) /* XHCI port hardware LPM control */ 285/* 5.4.11.1 */ 286#define XHCI_PLMC3_LSEC_MASK __BITS(15, 0) /* RW - Link Soft Error Count */ 287#define XHCI_PLMC3_LSEC_GET(x) __SHIFTOUT((x), XHCI_PLMC3_LSEC_MASK) 288 289/* 5.5.1 */ 290/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 291#define XHCI_MFINDEX 0x0000 292#define XHCI_MFINDEX_MASK __BITS(13, 0) /* RO - microframe index */ 293#define XHCI_MFINDEX_GET(x) __SHIFTOUT((x), XHCI_MFINDEX_MASK) 294 295/* 5.5.2 Interrupter Register set */ 296/* 5.5.2.1 interrupt management */ 297#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) 298#define XHCI_IMAN_INTR_PEND __BIT(0) /* RW - interrupt pending */ 299#define XHCI_IMAN_INTR_ENA __BIT(1) /* RW - interrupt enable */ 300 301/* 5.5.2.2 Interrupter Moderation */ 302#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 303#define XHCI_IMOD_IVAL_MASK __BITS(15,0) /* 250ns unit */ 304#define XHCI_IMOD_IVAL_GET(x) __SHIFTOUT((x), XHCI_IMOD_IVAL_MASK) 305#define XHCI_IMOD_IVAL_SET(x) __SHIFTIN((x), XHCI_IMOD_IVAL_MASK) 306#define XHCI_IMOD_ICNT_MASK __BITS(31, 16) /* 250ns unit */ 307#define XHCI_IMOD_ICNT_GET(x) __SHIFTOUT((x), XHCI_IMOD_ICNT_MASK) 308#define XHCI_IMOD_ICNT_SET(x) __SHIFTIN((x), XHCI_IMOD_ICNT_MASK) 309#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */ 310#define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/sec for LynxPoint */ 311 312/* 5.5.2.3 Event Ring */ 313/* 5.5.2.3.1 Event Ring Segment Table Size */ 314#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 315#define XHCI_ERSTS_MASK __BITS(15, 0) /* Event Ring Segment Table Size */ 316#define XHCI_ERSTS_GET(x) __SHIFTOUT((x), XHCI_ERSTS_MASK) 317#define XHCI_ERSTS_SET(x) __SHIFTIN((x), XHCI_ERSTS_MASK) 318 319/* 5.5.2.3.2 Event Ring Segment Table Base Address Register */ 320#define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) 321#define XHCI_ERSTBA_MASK __BIT(31,6) /* RW - segment base address (low) */ 322#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 323 324/* 5.5.2.3.3 Event Ring Dequeue Pointer */ 325#define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) 326#define XHCI_ERDP_DESI_MASK __BITS(2,0) /* RO - dequeue segment index */ 327#define XHCI_ERDP_GET_DESI(x) __SHIFTOUT(x), XHCI_ERDP_DESI_MASK) 328#define XHCI_ERDP_BUSY __BIT(3) /* RW - event handler busy */ 329#define XHCI_ERDP_PTRLO_MASK __BIT(31,4) /* RW - dequeue pointer (low) */ 330#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) 331 332/* 5.6 XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 333#define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 334#define XHCI_DB_TARGET_MASK __BITS(7, 0) /* RW - doorbell target */ 335#define XHCI_DB_TARGET_GET(x) __SHIFTOUT((x), XHCI_DB_TARGET_MASK) 336#define XHCI_DB_TARGET_SET(x) __SHIFTIN((x), XHCI_DB_TARGET_MASK) 337#define XHCI_DB_SID_MASK __BITS(31, 16) /* RW - doorbell stream ID */ 338#define XHCI_DB_SID_GET(x) __SHIFTOUT((x), XHCI_DB_SID_MASK) 339#define XHCI_DB_SID_SET(x) __SHIFTIN((x), XHCI_DB_SID_MASK) 340 341/* 7 xHCI Extendeded capabilities */ 342#define XHCI_XECP_ID_MASK __BITS(7, 0) 343#define XHCI_XECP_ID(x) __SHIFTOUT((x), XHCI_XECP_ID_MASK) 344#define XHCI_XECP_NEXT_MASK __BITS(15, 8) 345#define XHCI_XECP_NEXT(x) __SHIFTOUT((x), XHCI_XECP_NEXT_MASK) 346 347/* XHCI extended capability ID's */ 348#define XHCI_ID_USB_LEGACY 0x0001 /* USB Legacy Support */ 349#define XHCI_XECP_USBLEGSUP 0x0000 /* Legacy Support Capability Reg */ 350#define XHCI_XECP_USBLEGCTLSTS 0x0004 /* Legacy Support Ctrl & Status Reg */ 351#define XHCI_ID_PROTOCOLS 0x0002 /* Supported Protocol */ 352#define XHCI_ID_POWER_MGMT 0x0003 /* Extended Power Management */ 353#define XHCI_ID_VIRTUALIZATION 0x0004 /* I/O Virtualization */ 354#define XHCI_ID_MSG_IRQ 0x0005 /* Message Interrupt */ 355#define XHCI_ID_USB_LOCAL_MEM 0x0006 /* Local Memory */ 356#define XHCI_ID_USB_DEBUG 0x000A /* USB Debug Capability */ 357#define XHCI_ID_XMSG_IRQ 0x0011 /* Extended Message Interrupt */ 358 359/* 7.1 xHCI legacy support */ 360#define XHCI_XECP_BIOS_SEM 0x0002 361#define XHCI_XECP_OS_SEM 0x0003 362 363/* 7.2 xHCI Supported Protocol Capability */ 364#define XHCI_XECP_USBID 0x20425355 365 366#define XHCI_XECP_SP_W0_MINOR_MASK __BITS(23, 16) 367#define XHCI_XECP_SP_W0_MINOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MINOR_MASK) 368#define XHCI_XECP_SP_W0_MAJOR_MASK __BITS(31, 24) 369#define XHCI_XECP_SP_W0_MAJOR(x) __SHIFTOUT((x), XHCI_XECP_SP_W0_MAJOR_MASK) 370 371#define XHCI_XECP_SP_W8_CPO_MASK __BITS(7, 0) 372#define XHCI_XECP_SP_W8_CPO(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPO_MASK) 373#define XHCI_XECP_SP_W8_CPC_MASK __BITS(15, 8) 374#define XHCI_XECP_SP_W8_CPC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_CPC_MASK) 375#define XHCI_XECP_SP_W8_PD_MASK __BITS(27, 16) 376#define XHCI_XECP_SP_W8_PD(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PD_MASK) 377#define XHCI_XECP_SP_W8_PSIC_MASK __BITS(31, 28) 378#define XHCI_XECP_SP_W8_PSIC(x) __SHIFTOUT((x), XHCI_XECP_SP_W8_PSIC_MASK) 379 380#define XHCI_PAGE_SIZE(sc) ((sc)->sc_pgsz) 381 382/* Chapter 6, Table 49 */ 383#define XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN 64 384#define XHCI_DEVICE_CONTEXT_ALIGN 64 385#define XHCI_INPUT_CONTROL_CONTEXT_ALIGN 64 386#define XHCI_SLOT_CONTEXT_ALIGN 32 387#define XHCI_ENDPOINT_CONTEXT_ALIGN 32 388#define XHCI_STREAM_CONTEXT_ALIGN 16 389#define XHCI_STREAM_ARRAY_ALIGN 16 390#define XHCI_TRANSFER_RING_SEGMENTS_ALIGN 16 391#define XHCI_COMMAND_RING_SEGMENTS_ALIGN 64 392#define XHCI_EVENT_RING_SEGMENTS_ALIGN 64 393#define XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN 64 394#define XHCI_SCRATCHPAD_BUFFER_ARRAY_ALIGN 64 395#define XHCI_SCRATCHPAD_BUFFERS_ALIGN XHCI_PAGE_SIZE 396 397#define XHCI_ERSTE_ALIGN 16 398#define XHCI_TRB_ALIGN 16 399 400struct xhci_trb { 401 uint64_t trb_0; 402 uint32_t trb_2; 403#define XHCI_TRB_2_ERROR_MASK __BITS(31, 24) 404#define XHCI_TRB_2_ERROR_GET(x) __SHIFTOUT((x), XHCI_TRB_2_ERROR_MASK) 405#define XHCI_TRB_2_ERROR_SET(x) __SHIFTIN((x), XHCI_TRB_2_ERROR_MASK) 406 407#define XHCI_TRB_2_TDSZ_MASK __BITS(21, 17) /* TD Size */ 408#define XHCI_TRB_2_TDSZ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_TDSZ_MASK) 409#define XHCI_TRB_2_TDSZ_SET(x) __SHIFTIN((x), XHCI_TRB_2_TDSZ_MASK) 410#define XHCI_TRB_2_REM_MASK __BITS(23, 0) 411#define XHCI_TRB_2_REM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_REM_MASK) 412#define XHCI_TRB_2_REM_SET(x) __SHIFTIN((x), XHCI_TRB_2_REM_MASK) 413 414#define XHCI_TRB_2_BYTES_MASK __BITS(16, 0) 415#define XHCI_TRB_2_BYTES_GET(x) __SHIFTOUT((x), XHCI_TRB_2_BYTES_MASK) 416#define XHCI_TRB_2_BYTES_SET(x) __SHIFTIN((x), XHCI_TRB_2_BYTES_MASK) 417#define XHCI_TRB_2_IRQ_MASK __BITS(31, 22) 418#define XHCI_TRB_2_IRQ_GET(x) __SHIFTOUT((x), XHCI_TRB_2_IRQ_MASK) 419#define XHCI_TRB_2_IRQ_SET(x) __SHIFTIN((x), XHCI_TRB_2_IRQ_MASK) 420#define XHCI_TRB_2_STREAM_MASK __BITS(31, 16) 421#define XHCI_TRB_2_STREAM_GET(x) __SHIFTOUT((x), XHCI_TRB_2_STREAM_MASK) 422#define XHCI_TRB_2_STREAM_SET(x) __SHIFTIN((x), XHCI_TRB_2_STREAM_MASK) 423 uint32_t trb_3; 424#define XHCI_TRB_3_TYPE_MASK __BITS(15, 10) 425#define XHCI_TRB_3_TYPE_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TYPE_MASK) 426#define XHCI_TRB_3_TYPE_SET(x) __SHIFTIN((x), XHCI_TRB_3_TYPE_MASK) 427#define XHCI_TRB_3_CYCLE_BIT __BIT(0) 428#define XHCI_TRB_3_TC_BIT __BIT(1) /* command ring only */ 429#define XHCI_TRB_3_ENT_BIT __BIT(1) /* transfer ring only */ 430#define XHCI_TRB_3_ISP_BIT __BIT(2) 431#define XHCI_TRB_3_NSNOOP_BIT __BIT(3) 432#define XHCI_TRB_3_CHAIN_BIT __BIT(4) 433#define XHCI_TRB_3_IOC_BIT __BIT(5) 434#define XHCI_TRB_3_IDT_BIT __BIT(6) 435#define XHCI_TRB_3_TBC_MASK __BITS(8, 7) 436#define XHCI_TRB_3_TBC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TBC_MASK) 437#define XHCI_TRB_3_TBC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TBC_MASK) 438#define XHCI_TRB_3_BEI_BIT __BIT(9) 439#define XHCI_TRB_3_DCEP_BIT __BIT(9) 440#define XHCI_TRB_3_PRSV_BIT __BIT(9) 441#define XHCI_TRB_3_BSR_BIT __BIT(9) 442 443#define XHCI_TRB_3_TRT_MASK __BITS(17, 16) 444#define XHCI_TRB_3_TRT_NONE __SHIFTIN(0U, XHCI_TRB_3_TRT_MASK) 445#define XHCI_TRB_3_TRT_OUT __SHIFTIN(2U, XHCI_TRB_3_TRT_MASK) 446#define XHCI_TRB_3_TRT_IN __SHIFTIN(3U, XHCI_TRB_3_TRT_MASK) 447#define XHCI_TRB_3_DIR_IN __BIT(16) 448#define XHCI_TRB_3_TLBPC_MASK __BITS(19, 16) 449#define XHCI_TRB_3_TLBPC_GET(x) __SHIFTOUT((x), XHCI_TRB_3_TLBPC_MASK) 450#define XHCI_TRB_3_TLBPC_SET(x) __SHIFTIN((x), XHCI_TRB_3_TLBPC_MASK) 451#define XHCI_TRB_3_EP_MASK __BITS(20, 16) 452#define XHCI_TRB_3_EP_GET(x) __SHIFTOUT((x), XHCI_TRB_3_EP_MASK) 453#define XHCI_TRB_3_EP_SET(x) __SHIFTIN((x), XHCI_TRB_3_EP_MASK) 454#define XHCI_TRB_3_FRID_MASK __BITS(30, 20) 455#define XHCI_TRB_3_FRID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_FRID_MASK) 456#define XHCI_TRB_3_FRID_SET(x) __SHIFTIN((x), XHCI_TRB_3_FRID_MASK) 457#define XHCI_TRB_3_ISO_SIA_BIT __BIT(31) 458#define XHCI_TRB_3_SUSP_EP_BIT __BIT(23) 459#define XHCI_TRB_3_VFID_MASK __BITS(23, 16) 460#define XHCI_TRB_3_VFID_GET(x) __SHIFTOUT((x), XHCI_TRB_3_VFID_MASK) 461#define XHCI_TRB_3_VFID_SET(x) __SHIFTIN((x), XHCI_TRB_3_VFID_MASK) 462#define XHCI_TRB_3_SLOT_MASK __BITS(31, 24) 463#define XHCI_TRB_3_SLOT_GET(x) __SHIFTOUT((x), XHCI_TRB_3_SLOT_MASK) 464#define XHCI_TRB_3_SLOT_SET(x) __SHIFTIN((x), XHCI_TRB_3_SLOT_MASK) 465 466 /* Commands */ 467#define XHCI_TRB_TYPE_RESERVED 0x00 468#define XHCI_TRB_TYPE_NORMAL 0x01 469#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 470#define XHCI_TRB_TYPE_DATA_STAGE 0x03 471#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 472#define XHCI_TRB_TYPE_ISOCH 0x05 473#define XHCI_TRB_TYPE_LINK 0x06 474#define XHCI_TRB_TYPE_EVENT_DATA 0x07 475#define XHCI_TRB_TYPE_NOOP 0x08 476#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 477#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 478#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 479#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 480#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 481#define XHCI_TRB_TYPE_RESET_EP 0x0E 482#define XHCI_TRB_TYPE_STOP_EP 0x0F 483#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 484#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 485#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 486#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 487#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 488#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 489#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 490#define XHCI_TRB_TYPE_NOOP_CMD 0x17 491 492 /* Events */ 493#define XHCI_TRB_EVENT_TRANSFER 0x20 494#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 495#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 496#define XHCI_TRB_EVENT_BW_REQUEST 0x23 497#define XHCI_TRB_EVENT_DOORBELL 0x24 498#define XHCI_TRB_EVENT_HOST_CTRL 0x25 499#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 500#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 501 502 /* Error codes */ 503#define XHCI_TRB_ERROR_INVALID 0x00 504#define XHCI_TRB_ERROR_SUCCESS 0x01 505#define XHCI_TRB_ERROR_DATA_BUF 0x02 506#define XHCI_TRB_ERROR_BABBLE 0x03 507#define XHCI_TRB_ERROR_XACT 0x04 508#define XHCI_TRB_ERROR_TRB 0x05 509#define XHCI_TRB_ERROR_STALL 0x06 510#define XHCI_TRB_ERROR_RESOURCE 0x07 511#define XHCI_TRB_ERROR_BANDWIDTH 0x08 512#define XHCI_TRB_ERROR_NO_SLOTS 0x09 513#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 514#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 515#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 516#define XHCI_TRB_ERROR_SHORT_PKT 0x0D 517#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 518#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 519#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 520#define XHCI_TRB_ERROR_PARAMETER 0x11 521#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 522#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 523#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 524#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 525#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 526#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 527#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 528#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 529#define XHCI_TRB_ERROR_STOPPED 0x1A 530#define XHCI_TRB_ERROR_LENGTH 0x1B 531#define XHCI_TRB_ERROR_STOPPED_SHORT 0x1C 532#define XHCI_TRB_ERROR_BAD_MELAT 0x1D 533#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 534#define XHCI_TRB_ERROR_EVENT_LOST 0x20 535#define XHCI_TRB_ERROR_UNDEFINED 0x21 536#define XHCI_TRB_ERROR_INVALID_SID 0x22 537#define XHCI_TRB_ERROR_SEC_BW 0x23 538#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 539} __packed __aligned(XHCI_TRB_ALIGN); 540#define XHCI_TRB_SIZE sizeof(struct xhci_trb) 541 542/* 543 * 6.2.2 Slot context 544 */ 545#define XHCI_SCTX_0_ROUTE_MASK __BITS(19, 0) 546#define XHCI_SCTX_0_ROUTE_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_ROUTE_MASK) 547#define XHCI_SCTX_0_ROUTE_SET(x) __SHIFTIN((x), XHCI_SCTX_0_ROUTE_MASK) 548#define XHCI_SCTX_0_SPEED_MASK __BITS(23, 20) 549#define XHCI_SCTX_0_SPEED_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_SPEED_MASK) 550#define XHCI_SCTX_0_SPEED_SET(x) __SHIFTIN((x), XHCI_SCTX_0_SPEED_MASK) 551#define XHCI_SCTX_0_MTT_MASK __BIT(25) 552#define XHCI_SCTX_0_MTT_SET(x) __SHIFTIN((x), XHCI_SCTX_0_MTT_MASK) 553#define XHCI_SCTX_0_MTT_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_MTT_MASK) 554#define XHCI_SCTX_0_HUB_MASK __BIT(26) 555#define XHCI_SCTX_0_HUB_SET(x) __SHIFTIN((x), XHCI_SCTX_0_HUB_MASK) 556#define XHCI_SCTX_0_HUB_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_HUB_MASK) 557#define XHCI_SCTX_0_CTX_NUM_MASK __BITS(31, 27) 558#define XHCI_SCTX_0_CTX_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_0_CTX_NUM_MASK) 559#define XHCI_SCTX_0_CTX_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_0_CTX_NUM_MASK) 560 561#define XHCI_SCTX_1_MAX_EL_MASK __BITS(15, 0) 562#define XHCI_SCTX_1_MAX_EL_SET(x) __SHIFTIN((x), XHCI_SCTX_1_MAX_EL_MASK) 563#define XHCI_SCTX_1_MAX_EL_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_MAX_EL_MASK) 564#define XHCI_SCTX_1_RH_PORT_MASK __BITS(23, 16) 565#define XHCI_SCTX_1_RH_PORT_SET(x) __SHIFTIN((x), XHCI_SCTX_1_RH_PORT_MASK) 566#define XHCI_SCTX_1_RH_PORT_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_RH_PORT_MASK) 567#define XHCI_SCTX_1_NUM_PORTS_MASK __BITS(31, 24) 568#define XHCI_SCTX_1_NUM_PORTS_SET(x) __SHIFTIN((x), XHCI_SCTX_1_NUM_PORTS_MASK) 569#define XHCI_SCTX_1_NUM_PORTS_GET(x) __SHIFTOUT((x), XHCI_SCTX_1_NUM_PORTS_MASK) 570 571#define XHCI_SCTX_2_TT_HUB_SID_MASK __BITS(7, 0) 572#define XHCI_SCTX_2_TT_HUB_SID_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_HUB_SID_MASK) 573#define XHCI_SCTX_2_TT_HUB_SID_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_HUB_SID_MASK) 574#define XHCI_SCTX_2_TT_PORT_NUM_MASK __BITS(15, 8) 575#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_PORT_NUM_MASK) 576#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_PORT_NUM_MASK) 577#define XHCI_SCTX_2_TT_THINK_TIME_MASK __BITS(17, 16) 578#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) __SHIFTIN((x), XHCI_SCTX_2_TT_THINK_TIME_MASK) 579#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_TT_THINK_TIME_MASK) 580#define XHCI_SCTX_2_IRQ_TARGET_MASK __BITS(31, 22) 581#define XHCI_SCTX_2_IRQ_TARGET_SET(x) __SHIFTIN((x), XHCI_SCTX_2_IRQ_TARGET_MASK) 582#define XHCI_SCTX_2_IRQ_TARGET_GET(x) __SHIFTOUT((x), XHCI_SCTX_2_IRQ_TARGET_MASK) 583 584#define XHCI_SCTX_3_DEV_ADDR_MASK __BITS(7, 0) 585#define XHCI_SCTX_3_DEV_ADDR_SET(x) __SHIFTIN((x), XHCI_SCTX_3_DEV_ADDR_MASK) 586#define XHCI_SCTX_3_DEV_ADDR_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_DEV_ADDR_MASK) 587#define XHCI_SCTX_3_SLOT_STATE_MASK __BITS(31, 27) 588#define XHCI_SCTX_3_SLOT_STATE_SET(x) __SHIFTIN((x), XHCI_SCTX_3_SLOT_STATE_MASK) 589#define XHCI_SCTX_3_SLOT_STATE_GET(x) __SHIFTOUT((x), XHCI_SCTX_3_SLOT_STATE_MASK) 590#define XHCI_SLOTSTATE_DISABLED 0 /* disabled or enabled */ 591#define XHCI_SLOTSTATE_ENABLED 0 592#define XHCI_SLOTSTATE_DEFAULT 1 593#define XHCI_SLOTSTATE_ADDRESSED 2 594#define XHCI_SLOTSTATE_CONFIGURED 3 595 596/* 597 * 6.2.3 Endpoint Context 598 * */ 599#define XHCI_EPCTX_0_EPSTATE_MASK __BITS(2, 0) 600#define XHCI_EPCTX_0_EPSTATE_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_EPSTATE_MASK) 601#define XHCI_EPCTX_0_EPSTATE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_EPSTATE_MASK) 602#define XHCI_EPSTATE_DISABLED 0 603#define XHCI_EPSTATE_RUNNING 1 604#define XHCI_EPSTATE_HALTED 2 605#define XHCI_EPSTATE_STOPPED 3 606#define XHCI_EPSTATE_ERROR 4 607#define XHCI_EPCTX_0_MULT_MASK __BITS(9, 8) 608#define XHCI_EPCTX_0_MULT_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MULT_MASK) 609#define XHCI_EPCTX_0_MULT_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MULT_MASK) 610#define XHCI_EPCTX_0_MAXP_STREAMS_MASK __BITS(14, 10) 611#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK) 612#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAXP_STREAMS_MASK) 613#define XHCI_EPCTX_0_LSA_MASK __BIT(15) 614#define XHCI_EPCTX_0_LSA_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_LSA_MASK) 615#define XHCI_EPCTX_0_LSA_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_LSA_MASK) 616#define XHCI_EPCTX_0_IVAL_MASK __BITS(23, 16) 617#define XHCI_EPCTX_0_IVAL_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_IVAL_MASK) 618#define XHCI_EPCTX_0_IVAL_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_IVAL_MASK) 619#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK __BITS(31, 24) 620#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x) __SHIFTIN((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK) 621#define XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_GET(x) __SHIFTOUT((x), XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_MASK) 622 623#define XHCI_EPCTX_1_CERR_MASK __BITS(2, 1) 624#define XHCI_EPCTX_1_CERR_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_CERR_MASK) 625#define XHCI_EPCTX_1_CERR_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_CERR_MASK) 626#define XHCI_EPCTX_1_EPTYPE_MASK __BITS(5, 3) 627#define XHCI_EPCTX_1_EPTYPE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_EPTYPE_MASK) 628#define XHCI_EPCTX_1_EPTYPE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_EPTYPE_MASK) 629#define XHCI_EPCTX_1_HID_MASK __BIT(7) 630#define XHCI_EPCTX_1_HID_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_HID_MASK) 631#define XHCI_EPCTX_1_HID_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_HID_MASK) 632#define XHCI_EPCTX_1_MAXB_MASK __BITS(15, 8) 633#define XHCI_EPCTX_1_MAXB_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXB_MASK) 634#define XHCI_EPCTX_1_MAXB_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXB_MASK) 635#define XHCI_EPCTX_1_MAXP_SIZE_MASK __BITS(31, 16) 636#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) __SHIFTIN((x), XHCI_EPCTX_1_MAXP_SIZE_MASK) 637#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) __SHIFTOUT((x), XHCI_EPCTX_1_MAXP_SIZE_MASK) 638 639 640#define XHCI_EPCTX_2_DCS_MASK __BIT(0) 641#define XHCI_EPCTX_2_DCS_SET(x) __SHIFTIN((x), XHCI_EPCTX_2_DCS_MASK) 642#define XHCI_EPCTX_2_DCS_GET(x) __SHIFTOUT((x), XHCI_EPCTX_2_DCS_MASK) 643#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0ULL 644 645#define XHCI_EPCTX_4_AVG_TRB_LEN_MASK __BITS(15, 0) 646#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK) 647#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_AVG_TRB_LEN_MASK) 648#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK __BITS(16, 31) 649#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) __SHIFTIN((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK) 650#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) __SHIFTOUT((x), XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_MASK) 651#define XHCI_EPCTX_MEP_FS_INTR 64U 652#define XHCI_EPCTX_MEP_FS_ISOC (1*1024U) 653#define XHCI_EPCTX_MEP_HS_INTR (3*1024U) 654#define XHCI_EPCTX_MEP_HS_ISOC (3*1024U) 655#define XHCI_EPCTX_MEP_SS_INTR (3*1024U) 656#define XHCI_EPCTX_MEP_SS_ISOC (48*1024U) 657#define XHCI_EPCTX_MEP_SS_ISOC_LEC (16*1024*1024U - 1) 658 659 660#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 661 662#define XHCI_INCTX_0_DROP_MASK(n) __BIT((n)) 663 664#define XHCI_INCTX_1_ADD_MASK(n) __BIT((n)) 665 666 667struct xhci_erste { 668 uint64_t erste_0; /* 63:6 base */ 669 uint32_t erste_2; /* 15:0 trb count (16 to 4096) */ 670 uint32_t erste_3; /* RsvdZ */ 671} __packed __aligned(XHCI_ERSTE_ALIGN); 672#define XHCI_ERSTE_SIZE sizeof(struct xhci_erste) 673 674#endif /* _DEV_USB_XHCIREG_H_ */ 675