1/* $NetBSD: motgreg.h,v 1.2 2014/09/13 14:47:35 jmcneill Exp $ */ 2/* FreeBSD: head/sys/dev/usb/controller/musb_otg.h 267122 2014-06-05 18:23:51Z hselasky */ 3/*- 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * This header file defines the registers of the Mentor Graphics USB OnTheGo 30 * Inventra chip. 31 */ 32 33#ifndef _MUSB2_OTG_H_ 34#define _MUSB2_OTG_H_ 35 36#define MUSB2_MAX_DEVICES USB_MAX_DEVICES 37 38/* Common registers */ 39 40#define MUSB2_REG_FADDR 0x0000 /* function address register */ 41#define MUSB2_MASK_FADDR 0x7F 42 43#define MUSB2_REG_POWER 0x0001 /* power register */ 44#define MUSB2_MASK_SUSPM_ENA 0x01 45#define MUSB2_MASK_SUSPMODE 0x02 46#define MUSB2_MASK_RESUME 0x04 47#define MUSB2_MASK_RESET 0x08 48#define MUSB2_MASK_HSMODE 0x10 49#define MUSB2_MASK_HSENAB 0x20 50#define MUSB2_MASK_SOFTC 0x40 51#define MUSB2_MASK_ISOUPD 0x80 52 53/* Endpoint interrupt handling */ 54 55#define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */ 56#define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */ 57#define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */ 58#define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */ 59#define MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */ 60 61/* Common interrupt handling */ 62 63#define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */ 64#define MUSB2_MASK_ISUSP 0x01 65#define MUSB2_MASK_IRESUME 0x02 66#define MUSB2_MASK_IRESET 0x04 67#define MUSB2_MASK_IBABBLE 0x04 68#define MUSB2_MASK_ISOF 0x08 69#define MUSB2_MASK_ICONN 0x10 70#define MUSB2_MASK_IDISC 0x20 71#define MUSB2_MASK_ISESSRQ 0x40 72#define MUSB2_MASK_IVBUSERR 0x80 73 74#define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */ 75#define MUSB2_REG_FRAME 0x000C /* USB frame register */ 76#define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */ 77 78#define MUSB2_REG_EPINDEX 0x000E /* endpoint index register */ 79#define MUSB2_MASK_EPINDEX 0x0F 80 81#define MUSB2_REG_TESTMODE 0x000F /* test mode register */ 82#define MUSB2_MASK_TSE0_NAK 0x01 83#define MUSB2_MASK_TJ 0x02 84#define MUSB2_MASK_TK 0x04 85#define MUSB2_MASK_TPACKET 0x08 86#define MUSB2_MASK_TFORCE_HS 0x10 87#define MUSB2_MASK_TFORCE_LS 0x20 88#define MUSB2_MASK_TFIFO_ACC 0x40 89#define MUSB2_MASK_TFORCE_HC 0x80 90 91#define MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */ 92 93#define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR) 94#define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR) 95#define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */ 96#define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */ 97 98#define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR) 99#define MUSB2_MASK_CSRL_TXPKTRDY 0x01 100#define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02 101#define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */ 102#define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */ 103#define MUSB2_MASK_CSRL_TXFFLUSH 0x08 104#define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */ 105#define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */ 106#define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */ 107#define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */ 108#define MUSB2_MASK_CSRL_TXDT_CLR 0x40 109#define MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */ 110#define MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */ 111 112/* Device Side Mode */ 113#define MUSB2_MASK_CSR0L_RXPKTRDY 0x01 114#define MUSB2_MASK_CSR0L_TXPKTRDY 0x02 115#define MUSB2_MASK_CSR0L_SENTSTALL 0x04 116#define MUSB2_MASK_CSR0L_DATAEND 0x08 117#define MUSB2_MASK_CSR0L_SETUPEND 0x10 118#define MUSB2_MASK_CSR0L_SENDSTALL 0x20 119#define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40 120#define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80 121 122/* Host Side Mode */ 123#define MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02 124#define MUSB2_MASK_CSR0L_RXSTALL 0x04 125#define MUSB2_MASK_CSR0L_SETUPPKT 0x08 126#define MUSB2_MASK_CSR0L_ERROR 0x10 127#define MUSB2_MASK_CSR0L_REQPKT 0x20 128#define MUSB2_MASK_CSR0L_STATUSPKT 0x40 129#define MUSB2_MASK_CSR0L_NAKTIMO 0x80 130 131#define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR) 132#define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */ 133#define MUSB2_MASK_CSRH_TXDT_WREN 0x02 /* Host Mode */ 134#define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04 135#define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08 136#define MUSB2_MASK_CSRH_TXDMAREQENA 0x10 137#define MUSB2_MASK_CSRH_RXMODE 0x00 138#define MUSB2_MASK_CSRH_TXMODE 0x20 139#define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */ 140#define MUSB2_MASK_CSRH_TXAUTOSET 0x80 141 142#define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */ 143#define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */ 144#define MUSB2_MASK_CSR0H_DT_WREN 0x04 /* Host Side */ 145#define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */ 146 147#define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR) 148#define MUSB2_MASK_CSRL_RXPKTRDY 0x01 149#define MUSB2_MASK_CSRL_RXFIFOFULL 0x02 150#define MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */ 151#define MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */ 152#define MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */ 153#define MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */ 154#define MUSB2_MASK_CSRL_RXFFLUSH 0x10 155#define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */ 156#define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */ 157#define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */ 158#define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */ 159#define MUSB2_MASK_CSRL_RXDT_CLR 0x80 160 161#define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR) 162#define MUSB2_MASK_CSRH_RXINCOMP 0x01 163#define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */ 164#define MUSB2_MASK_CSRH_RXDT_WREN 0x04 /* Host Mode */ 165#define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08 166#define MUSB2_MASK_CSRH_RXNYET 0x10 167#define MUSB2_MASK_CSRH_RXDMAREQENA 0x20 168#define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */ 169#define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */ 170#define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80 171 172#define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR) 173#define MUSB2_MASK_RXCOUNT 0xFFFF 174 175#define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR) 176#define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR) 177 178/* Host Mode */ 179#define MUSB2_MASK_TI_SPEED 0xC0 180#define MUSB2_MASK_TI_SPEED_LO 0xC0 181#define MUSB2_MASK_TI_SPEED_FS 0x80 182#define MUSB2_MASK_TI_SPEED_HS 0x40 183#define MUSB2_MASK_TI_PROTO_CTRL 0x00 184#define MUSB2_MASK_TI_PROTO_ISOC 0x10 185#define MUSB2_MASK_TI_PROTO_BULK 0x20 186#define MUSB2_MASK_TI_PROTO_INTR 0x30 187#define MUSB2_MASK_TI_EP_NUM 0x0F 188 189#define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 190#define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR) 191#define MUSB2_MASK_NAKLIMIT 0xFF 192 193#define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR) 194#define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2**n bytes */ 195#define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2**n bytes */ 196 197#define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n))) 198 199#define MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR) /* EPN=0 */ 200#define MUSB2_MASK_CD_UTMI_DW 0x01 201#define MUSB2_MASK_CD_SOFTCONE 0x02 202#define MUSB2_MASK_CD_DYNFIFOSZ 0x04 203#define MUSB2_MASK_CD_HBTXE 0x08 204#define MUSB2_MASK_CD_HBRXE 0x10 205#define MUSB2_MASK_CD_BIGEND 0x20 206#define MUSB2_MASK_CD_MPTXE 0x40 207#define MUSB2_MASK_CD_MPRXE 0x80 208 209/* Various registers */ 210 211#define MUSB2_REG_DEVCTL 0x0060 212#define MUSB2_MASK_SESS 0x01 213#define MUSB2_MASK_HOSTREQ 0x02 214#define MUSB2_MASK_HOSTMD 0x04 215#define MUSB2_MASK_VBUS0 0x08 216#define MUSB2_MASK_VBUS1 0x10 217#define MUSB2_MASK_LSDEV 0x20 218#define MUSB2_MASK_FSDEV 0x40 219#define MUSB2_MASK_BDEV 0x80 220 221#define MUSB2_REG_MISC 0x0061 222#define MUSB2_MASK_RXEDMA 0x01 223#define MUSB2_MASK_TXEDMA 0x02 224 225#define MUSB2_REG_TXFIFOSZ 0x0062 226#define MUSB2_REG_RXFIFOSZ 0x0063 227#define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */ 228#define MUSB2_MASK_FIFOSZ 0x0F 229#define MUSB2_VAL_FIFOSZ(logx) ((logx) - 3) 230#define MUSB2_VAL_FIFOSZ_8 0 231#define MUSB2_VAL_FIFOSZ_16 1 232#define MUSB2_VAL_FIFOSZ_32 2 233#define MUSB2_VAL_FIFOSZ_64 3 234#define MUSB2_VAL_FIFOSZ_128 4 235#define MUSB2_VAL_FIFOSZ_256 5 236#define MUSB2_VAL_FIFOSZ_512 6 237#define MUSB2_VAL_FIFOSZ_1024 7 238#define MUSB2_VAL_FIFOSZ_2048 8 239#define MUSB2_VAL_FIFOSZ_4096 9 240 241#define MUSB2_REG_TXFIFOADD 0x0064 242#define MUSB2_REG_RXFIFOADD 0x0066 243#define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */ 244 245#define MUSB2_REG_VSTATUS 0x0068 246#define MUSB2_REG_VCONTROL 0x0068 247#define MUSB2_REG_HWVERS 0x006C 248#define MUSB2_REG_ULPI_BASE 0x0070 249 250#define MUSB2_REG_EPINFO 0x0078 251#define MUSB2_MASK_NRXEP 0xF0 252#define MUSB2_MASK_NTXEP 0x0F 253 254#define MUSB2_REG_RAMINFO 0x0079 255#define MUSB2_REG_LINKINFO 0x007A 256 257#define MUSB2_REG_VPLEN 0x007B 258#define MUSB2_MASK_VPLEN 0xFF 259 260#define MUSB2_REG_HS_EOF1 0x007C 261#define MUSB2_REG_FS_EOF1 0x007D 262#define MUSB2_REG_LS_EOF1 0x007E 263#define MUSB2_REG_SOFT_RST 0x007F 264#define MUSB2_MASK_SRST 0x01 265#define MUSB2_MASK_SRSTX 0x02 266 267#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n)) 268#define MUSB2_REG_RXDBDIS 0x0340 269#define MUSB2_REG_TXDBDIS 0x0342 270#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */ 271 272#define MUSB2_REG_CHIRPTO 0x0344 273#define MUSB2_REG_HSRESUM 0x0346 274 275/* Host Mode only registers */ 276 277#define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n))) 278#define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n))) 279#define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n))) 280#define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n))) 281#define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n))) 282#define MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n))) 283 284#define MUSB2_EP_MAX 16 /* maximum number of endpoints */ 285 286#endif /* _MUSB2_OTG_H_ */ 287