if_urtwnreg.h revision 1.9
1/* $NetBSD: if_urtwnreg.h,v 1.9 2016/10/12 02:56:45 nat Exp $ */ 2/* $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define URTWN_NOISE_FLOOR -95 21 22#define R92C_MAX_CHAINS 2 23 24/* Maximum number of output pipes is 3. */ 25#define R92C_MAX_EPOUT 3 26 27#define R92C_MAX_TX_PWR 0x3f 28 29#define R92C_PUBQ_NPAGES 231 30#define R92C_TXPKTBUF_COUNT 256 31#define R92C_TX_PAGE_COUNT 248 32#define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 33#define R88E_TXPKTBUF_COUNT 177 34#define R88E_TX_PAGE_COUNT 169 35#define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 36 37#define R92C_H2C_NBOX 4 38 39/* USB Requests. */ 40#define R92C_REQ_REGS 0x05 41 42/* 43 * MAC registers. 44 */ 45/* System Configuration. */ 46#define R92C_SYS_ISO_CTRL 0x000 47#define R92C_SYS_FUNC_EN 0x002 48#define R92C_APS_FSMCO 0x004 49#define R92C_SYS_CLKR 0x008 50#define R92C_AFE_MISC 0x010 51#define R92C_SPS0_CTRL 0x011 52#define R92C_SPS_OCP_CFG 0x018 53#define R92C_RSV_CTRL 0x01c 54#define R92C_RF_CTRL 0x01f 55#define R92C_LDOA15_CTRL 0x020 56#define R92C_LDOV12D_CTRL 0x021 57#define R92C_LDOHCI12_CTRL 0x022 58#define R92C_LPLDO_CTRL 0x023 59#define R92C_AFE_XTAL_CTRL 0x024 60#define R92C_AFE_PLL_CTRL 0x028 61#define R92C_EFUSE_CTRL 0x030 62#define R92C_EFUSE_TEST 0x034 63#define R92C_PWR_DATA 0x038 64#define R92C_CAL_TIMER 0x03c 65#define R92C_ACLK_MON 0x03e 66#define R92C_GPIO_MUXCFG 0x040 67#define R92C_GPIO_IO_SEL 0x042 68#define R92C_MAC_PINMUX_CFG 0x043 69#define R92C_GPIO_PIN_CTRL 0x044 70#define R92C_GPIO_INTM 0x048 71#define R92C_LEDCFG0 0x04c 72#define R92C_LEDCFG1 0x04d 73#define R92C_LEDCFG2 0x04e 74#define R92C_LEDCFG3 0x04f 75#define R92C_FSIMR 0x050 76#define R92C_FSISR 0x054 77#define R92C_HSIMR 0x058 78#define R92C_HSISR 0x05c 79#define R92C_MCUFWDL 0x080 80#define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 81#define R88E_HIMR 0x0b0 82#define R88E_HISR 0x0b4 83#define R88E_HIMRE 0x0b8 84#define R88E_HISRE 0x0bc 85#define R92C_EFUSE_ACCESS 0x0cf 86#define R92C_BIST_SCAN 0x0d0 87#define R92C_BIST_RPT 0x0d4 88#define R92C_BIST_ROM_RPT 0x0d8 89#define R92C_USB_SIE_INTF 0x0e0 90#define R92C_PCIE_MIO_INTF 0x0e4 91#define R92C_PCIE_MIO_INTD 0x0e8 92#define R92C_HPON_FSM 0x0ec 93#define R92C_SYS_CFG 0x0f0 94/* MAC General Configuration. */ 95#define R92C_CR 0x100 96#define R92C_MSR 0x102 97#define R92C_PBP 0x104 98#define R92C_TRXDMA_CTRL 0x10c 99#define R92C_TRXFF_BNDY 0x114 100#define R92C_TRXFF_STATUS 0x118 101#define R92C_RXFF_PTR 0x11c 102#define R92C_HIMR 0x120 103#define R92C_HISR 0x124 104#define R92C_HIMRE 0x128 105#define R92C_HISRE 0x12c 106#define R92C_CPWM 0x12f 107#define R92C_FWIMR 0x130 108#define R92C_FWISR 0x134 109#define R92C_PKTBUF_DBG_CTRL 0x140 110#define R92C_PKTBUF_DBG_DATA_L 0x144 111#define R92C_PKTBUF_DBG_DATA_H 0x148 112#define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 113#define R92C_TCUNIT_BASE 0x164 114#define R92C_MBIST_START 0x174 115#define R92C_MBIST_DONE 0x178 116#define R92C_MBIST_FAIL 0x17c 117#define R92C_C2HEVT_MSG_NORMAL 0x1a0 118#define R92C_C2HEVT_MSG_TEST 0x1b8 119#define R92C_C2HEVT_CLEAR 0x1bf 120#define R92C_MCUTST_1 0x1c0 121#define R92C_FMETHR 0x1c8 122#define R92C_HMETFR 0x1cc 123#define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 124#define R92C_LLT_INIT 0x1e0 125#define R92C_BB_ACCESS_CTRL 0x1e8 126#define R92C_BB_ACCESS_DATA 0x1ec 127#define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 128/* Tx DMA Configuration. */ 129#define R92C_RQPN 0x200 130#define R92C_FIFOPAGE 0x204 131#define R92C_TDECTRL 0x208 132#define R92C_TXDMA_OFFSET_CHK 0x20c 133#define R92C_TXDMA_STATUS 0x210 134#define R92C_RQPN_NPQ 0x214 135/* Rx DMA Configuration. */ 136#define R92C_RXDMA_AGG_PG_TH 0x280 137#define R92C_RXPKT_NUM 0x284 138#define R92C_RXDMA_STATUS 0x288 139/* Protocol Configuration. */ 140#define R92C_FWHW_TXQ_CTRL 0x420 141#define R92C_HWSEQ_CTRL 0x423 142#define R92C_TXPKTBUF_BCNQ_BDNY 0x424 143#define R92C_TXPKTBUF_MGQ_BDNY 0x425 144#define R92C_SPEC_SIFS 0x428 145#define R92C_RL 0x42a 146#define R92C_DARFRC 0x430 147#define R92C_RARFRC 0x438 148#define R92C_RRSR 0x440 149#define R92C_ARFR(i) (0x444 + (i) * 4) 150#define R92C_AGGLEN_LMT 0x458 151#define R92C_AMPDU_MIN_SPACE 0x45c 152#define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 153#define R92C_FAST_EDCA_CTRL 0x460 154#define R92C_RD_RESP_PKT_TH 0x463 155#define R92C_INIRTS_RATE_SEL 0x480 156#define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 157#define R92C_MAX_AGGR_NUM 0x4ca 158#define R92C_PROT_MODE_CTRL 0x4c8 159#define R92C_BAR_MODE_CTRL 0x4cc 160/* EDCA Configuration. */ 161#define R92C_EDCA_VO_PARAM 0x500 162#define R92C_EDCA_VI_PARAM 0x504 163#define R92C_EDCA_BE_PARAM 0x508 164#define R92C_EDCA_BK_PARAM 0x50c 165#define R92C_BCNTCFG 0x510 166#define R92C_PIFS 0x512 167#define R92C_RDG_PIFS 0x513 168#define R92C_SIFS_CCK 0x514 169#define R92C_SIFS_OFDM 0x516 170#define R92C_AGGR_BREAK_TIME 0x51a 171#define R92C_SLOT 0x51b 172#define R92C_TX_PTCL_CTRL 0x520 173#define R92C_TXPAUSE 0x522 174#define R92C_DIS_TXREQ_CLR 0x523 175#define R92C_RD_CTRL 0x524 176#define R92C_TBTT_PROHIBIT 0x540 177#define R92C_RD_NAV_NXT 0x544 178#define R92C_NAV_PROT_LEN 0x546 179#define R92C_BCN_CTRL 0x550 180#define R92C_USTIME_TSF 0x551 181#define R92C_MBID_NUM 0x552 182#define R92C_DUAL_TSF_RST 0x553 183#define R92C_BCN_INTERVAL 0x554 184#define R92C_DRVERLYINT 0x558 185#define R92C_BCNDMATIM 0x559 186#define R92C_ATIMWND 0x55a 187#define R92C_BCN_MAX_ERR 0x55d 188#define R92C_RXTSF_OFFSET_CCK 0x55e 189#define R92C_RXTSF_OFFSET_OFDM 0x55f 190#define R92C_TSFTR 0x560 191#define R92C_INIT_TSFTR 0x564 192#define R92C_PSTIMER 0x580 193#define R92C_TIMER0 0x584 194#define R92C_TIMER1 0x588 195#define R92C_ACMHWCTRL 0x5c0 196#define R92C_ACMRSTCTRL 0x5c1 197#define R92C_ACMAVG 0x5c2 198#define R92C_VO_ADMTIME 0x5c4 199#define R92C_VI_ADMTIME 0x5c6 200#define R92C_BE_ADMTIME 0x5c8 201#define R92C_EDCA_RANDOM_GEN 0x5cc 202#define R92C_SCH_TXCMD 0x5d0 203/* WMAC Configuration. */ 204#define R92C_APSD_CTRL 0x600 205#define R92C_BWOPMODE 0x603 206#define R92C_TCR 0x604 207#define R92C_RCR 0x608 208#define R92C_RX_PKT_LIMIT 0x60c 209#define R92C_RX_DLK_TIME 0x60d 210#define R92C_RX_DRVINFO_SZ 0x60f 211#define R92C_MACID 0x610 212#define R92C_BSSID 0x618 213#define R92C_MAR 0x620 214#define R92C_MBIDCAMCFG 0x628 215#define R92C_USTIME_EDCA 0x638 216#define R92C_MAC_SPEC_SIFS 0x63a 217#define R92C_R2T_SIFS 0x63c 218#define R92C_T2T_SIFS 0x63e 219#define R92C_ACKTO 0x640 220#define R92C_CTS2TO 0x641 221#define R92C_EIFS 0x642 222#define R92C_NAV_CTRL 0x650 223#define R92C_BACAMCMD 0x654 224#define R92C_BACAMCONTENT 0x658 225#define R92C_LBDLY 0x660 226#define R92C_FWDLY 0x661 227#define R92C_RXERR_RPT 0x664 228#define R92C_WMAC_TRXPTCL_CTL 0x668 229#define R92C_CAMCMD 0x670 230#define R92C_CAMWRITE 0x674 231#define R92C_CAMREAD 0x678 232#define R92C_CAMDBG 0x67c 233#define R92C_SECCFG 0x680 234#define R92C_WOW_CTRL 0x690 235#define R92C_PSSTATUS 0x691 236#define R92C_PS_RX_INFO 0x692 237#define R92C_LPNAV_CTRL 0x694 238#define R92C_WKFMCAM_CMD 0x698 239#define R92C_WKFMCAM_RWD 0x69c 240#define R92C_RXFLTMAP0 0x6a0 241#define R92C_RXFLTMAP1 0x6a2 242#define R92C_RXFLTMAP2 0x6a4 243#define R92C_BCN_PSR_RPT 0x6a8 244#define R92C_CALB32K_CTRL 0x6ac 245#define R92C_PKT_MON_CTRL 0x6b4 246#define R92C_BT_COEX_TABLE 0x6c0 247#define R92C_WMAC_RESP_TXINFO 0x6d8 248 249/* Bits for R92C_SYS_ISO_CTRL. */ 250#define R92C_SYS_ISO_CTRL_MD2PP 0x0001 251#define R92C_SYS_ISO_CTRL_UA2USB 0x0002 252#define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 253#define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 254#define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 255#define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 256#define R92C_SYS_ISO_CTRL_DIOP 0x0040 257#define R92C_SYS_ISO_CTRL_DIOE 0x0080 258#define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 259#define R92C_SYS_ISO_CTRL_DIOR 0x0200 260#define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 261#define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 262 263/* Bits for R92C_SYS_FUNC_EN. */ 264#define R92C_SYS_FUNC_EN_BBRSTB 0x0001 265#define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 266#define R92C_SYS_FUNC_EN_USBA 0x0004 267#define R92C_SYS_FUNC_EN_UPLL 0x0008 268#define R92C_SYS_FUNC_EN_USBD 0x0010 269#define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 270#define R92C_SYS_FUNC_EN_PCIEA 0x0040 271#define R92C_SYS_FUNC_EN_PPLL 0x0080 272#define R92C_SYS_FUNC_EN_PCIED 0x0100 273#define R92C_SYS_FUNC_EN_DIOE 0x0200 274#define R92C_SYS_FUNC_EN_CPUEN 0x0400 275#define R92C_SYS_FUNC_EN_DCORE 0x0800 276#define R92C_SYS_FUNC_EN_ELDR 0x1000 277#define R92C_SYS_FUNC_EN_DIO_RF 0x2000 278#define R92C_SYS_FUNC_EN_HWPDN 0x4000 279#define R92C_SYS_FUNC_EN_MREGEN 0x8000 280 281/* Bits for R92C_APS_FSMCO. */ 282#define R92C_APS_FSMCO_PFM_LDALL 0x00000001 283#define R92C_APS_FSMCO_PFM_ALDN 0x00000002 284#define R92C_APS_FSMCO_PFM_LDKP 0x00000004 285#define R92C_APS_FSMCO_PFM_WOWL 0x00000008 286#define R92C_APS_FSMCO_PDN_EN 0x00000010 287#define R92C_APS_FSMCO_PDN_PL 0x00000020 288#define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 289#define R92C_APS_FSMCO_APFM_OFF 0x00000200 290#define R92C_APS_FSMCO_APFM_RSM 0x00000400 291#define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 292#define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 293#define R92C_APS_FSMCO_APDM_MAC 0x00002000 294#define R92C_APS_FSMCO_APDM_HOST 0x00004000 295#define R92C_APS_FSMCO_APDM_HPDN 0x00008000 296#define R92C_APS_FSMCO_RDY_MACON 0x00010000 297#define R92C_APS_FSMCO_SUS_HOST 0x00020000 298#define R92C_APS_FSMCO_ROP_ALD 0x00100000 299#define R92C_APS_FSMCO_ROP_PWR 0x00200000 300#define R92C_APS_FSMCO_ROP_SPS 0x00400000 301#define R92C_APS_FSMCO_SOP_MRST 0x02000000 302#define R92C_APS_FSMCO_SOP_FUSE 0x04000000 303#define R92C_APS_FSMCO_SOP_ABG 0x08000000 304#define R92C_APS_FSMCO_SOP_AMB 0x10000000 305#define R92C_APS_FSMCO_SOP_RCK 0x20000000 306#define R92C_APS_FSMCO_SOP_A8M 0x40000000 307#define R92C_APS_FSMCO_XOP_BTCK 0x80000000 308 309/* Bits for R92C_SYS_CLKR. */ 310#define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 311#define R92C_SYS_CLKR_ANA8M 0x00000002 312#define R92C_SYS_CLKR_MACSLP 0x00000010 313#define R92C_SYS_CLKR_LOADER_EN 0x00000020 314#define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 315#define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 316#define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 317#define R92C_SYS_CLKR_SEC_EN 0x00000400 318#define R92C_SYS_CLKR_MAC_EN 0x00000800 319#define R92C_SYS_CLKR_SYS_EN 0x00001000 320#define R92C_SYS_CLKR_RING_EN 0x00002000 321 322/* Bits for R92C_RF_CTRL. */ 323#define R92C_RF_CTRL_EN 0x01 324#define R92C_RF_CTRL_RSTB 0x02 325#define R92C_RF_CTRL_SDMRSTB 0x04 326 327/* Bits for R92C_LDOV12D_CTRL. */ 328#define R92C_LDOV12D_CTRL_LDV12_EN 0x01 329 330/* Bits for R92C_AFE_XTAL_CTRL. */ 331#define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 332#define R92C_AFE_XTAL_CTRL_ADDR_S 11 333 334/* Bits for R92C_EFUSE_CTRL. */ 335#define R92C_EFUSE_CTRL_DATA_M 0x000000ff 336#define R92C_EFUSE_CTRL_DATA_S 0 337#define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 338#define R92C_EFUSE_CTRL_ADDR_S 8 339#define R92C_EFUSE_CTRL_VALID 0x80000000 340 341/* Bits for R92C_GPIO_MUXCFG. */ 342#define R92C_GPIO_MUXCFG_ENBT 0x0020 343 344/* Bits for R92C_LEDCFG0. */ 345#define R92C_LEDCFG0_DIS 0x08 346 347/* Bits for R92C_MCUFWDL. */ 348#define R92C_MCUFWDL_EN 0x00000001 349#define R92C_MCUFWDL_RDY 0x00000002 350#define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 351#define R92C_MCUFWDL_MACINI_RDY 0x00000008 352#define R92C_MCUFWDL_BBINI_RDY 0x00000010 353#define R92C_MCUFWDL_RFINI_RDY 0x00000020 354#define R92C_MCUFWDL_WINTINI_RDY 0x00000040 355#define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 356#define R92C_MCUFWDL_PAGE_M 0x00070000 357#define R92C_MCUFWDL_PAGE_S 16 358#define R92C_MCUFWDL_CPRST 0x00800000 359 360/* Bits for R88E_HIMR. */ 361#define R88E_HIMR_CPWM 0x00000100 362#define R88E_HIMR_CPWM2 0x00000200 363#define R88E_HIMR_TBDER 0x04000000 364#define R88E_HIMR_PSTIMEOUT 0x20000000 365 366/* Bits for R88E_HIMRE.*/ 367#define R88E_HIMRE_RXFOVW 0x00000100 368#define R88E_HIMRE_TXFOVW 0x00000200 369#define R88E_HIMRE_RXERR 0x00000400 370#define R88E_HIMRE_TXERR 0x00000800 371 372/* Bits for R92C_EFUSE_ACCESS. */ 373#define R92C_EFUSE_ACCESS_OFF 0x00 374#define R92C_EFUSE_ACCESS_ON 0x69 375 376/* Bits for R92C_HPON_FSM. */ 377#define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 378#define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 379#define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 380 381/* Bits for R92C_SYS_CFG. */ 382#define R92C_SYS_CFG_XCLK_VLD 0x00000001 383#define R92C_SYS_CFG_ACLK_VLD 0x00000002 384#define R92C_SYS_CFG_UCLK_VLD 0x00000004 385#define R92C_SYS_CFG_PCLK_VLD 0x00000008 386#define R92C_SYS_CFG_PCIRSTB 0x00000010 387#define R92C_SYS_CFG_V15_VLD 0x00000020 388#define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 389#define R92C_SYS_CFG_SIC_IDLE 0x00000100 390#define R92C_SYS_CFG_BD_MAC2 0x00000200 391#define R92C_SYS_CFG_BD_MAC1 0x00000400 392#define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 393#define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 394#define R92C_SYS_CFG_CHIP_VER_RTL_S 12 395#define R92C_SYS_CFG_BT_FUNC 0x00010000 396#define R92C_SYS_CFG_VENDOR_UMC 0x00080000 397#define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 398#define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 399#define R92C_SYS_CFG_TRP_BT_EN 0x01000000 400#define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 401#define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 402#define R92C_SYS_CFG_TYPE_92C 0x08000000 403 404/* Bits for R92C_CR. */ 405#define R92C_CR_HCI_TXDMA_EN 0x00000001 406#define R92C_CR_HCI_RXDMA_EN 0x00000002 407#define R92C_CR_TXDMA_EN 0x00000004 408#define R92C_CR_RXDMA_EN 0x00000008 409#define R92C_CR_PROTOCOL_EN 0x00000010 410#define R92C_CR_SCHEDULE_EN 0x00000020 411#define R92C_CR_MACTXEN 0x00000040 412#define R92C_CR_MACRXEN 0x00000080 413#define R92C_CR_ENSEC 0x00000200 414#define R92C_CR_CALTMR_EN 0x00000400 415#define R92C_CR_NETTYPE_S 16 416#define R92C_CR_NETTYPE_M 0x00030000 417#define R92C_CR_NETTYPE_NOLINK 0 418#define R92C_CR_NETTYPE_ADHOC 1 419#define R92C_CR_NETTYPE_INFRA 2 420#define R92C_CR_NETTYPE_AP 3 421 422/* Bits for R92C_MSR. */ 423#define R92C_MSR_NOLINK 0x00 424#define R92C_MSR_ADHOC 0x01 425#define R92C_MSR_INFRA 0x02 426#define R92C_MSR_AP 0x03 427#define R92C_MSR_MASK (~R92C_MSR_AP) 428 429/* Bits for R92C_PBP. */ 430#define R92C_PBP_PSRX_M 0x0f 431#define R92C_PBP_PSRX_S 0 432#define R92C_PBP_PSTX_M 0xf0 433#define R92C_PBP_PSTX_S 4 434#define R92C_PBP_64 0 435#define R92C_PBP_128 1 436#define R92C_PBP_256 2 437#define R92C_PBP_512 3 438#define R92C_PBP_1024 4 439 440/* Bits for R92C_TXPAUSE. */ 441#define TP_STOPBECON 0x40 442#define TP_STOPHIGH 0x20 443#define TP_STOPMGT 0x10 444#define TP_STOPVO 0x08 445#define TP_STOPVI 0x04 446#define TP_STOPBE 0x02 447#define TP_STOPBK 0x01 448#define TP_STOPALL 0x6f 449 450/* Bits for R92C_TRXDMA_CTRL. */ 451#define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 452#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 453#define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 454#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 455#define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 456#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 457#define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 458#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 459#define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 460#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 461#define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 462#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 463#define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 464#define R92C_TRXDMA_CTRL_QUEUE_LOW 1 465#define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 466#define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 467#define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 468/* Shortcuts. */ 469#define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 470#define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 471#define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 472#define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 473#define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 474#define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 475 476/* Bits for R92C_LLT_INIT. */ 477#define R92C_LLT_INIT_DATA_M 0x000000ff 478#define R92C_LLT_INIT_DATA_S 0 479#define R92C_LLT_INIT_ADDR_M 0x0000ff00 480#define R92C_LLT_INIT_ADDR_S 8 481#define R92C_LLT_INIT_OP_M 0xc0000000 482#define R92C_LLT_INIT_OP_S 30 483#define R92C_LLT_INIT_OP_NO_ACTIVE 0 484#define R92C_LLT_INIT_OP_WRITE 1 485 486/* Bits for R92C_RQPN. */ 487#define R92C_RQPN_HPQ_M 0x000000ff 488#define R92C_RQPN_HPQ_S 0 489#define R92C_RQPN_LPQ_M 0x0000ff00 490#define R92C_RQPN_LPQ_S 8 491#define R92C_RQPN_PUBQ_M 0x00ff0000 492#define R92C_RQPN_PUBQ_S 16 493#define R92C_RQPN_LD 0x80000000 494 495/* Bits for R92C_TDECTRL. */ 496#define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 497#define R92C_TDECTRL_BLK_DESC_NUM_S 4 498 499/* Bits for R92C_FWHW_TXQ_CTRL. */ 500#define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 501 502/* Bits for R92C_SPEC_SIFS. */ 503#define R92C_SPEC_SIFS_CCK_M 0x00ff 504#define R92C_SPEC_SIFS_CCK_S 0 505#define R92C_SPEC_SIFS_OFDM_M 0xff00 506#define R92C_SPEC_SIFS_OFDM_S 8 507 508/* Bits for R92C_RL. */ 509#define R92C_RL_LRL_M 0x003f 510#define R92C_RL_LRL_S 0 511#define R92C_RL_SRL_M 0x3f00 512#define R92C_RL_SRL_S 8 513 514/* Bits for R92C_RRSR. */ 515#define R92C_RRSR_RATE_BITMAP_M 0x000fffff 516#define R92C_RRSR_RATE_BITMAP_S 0 517#define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 518#define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 519#define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 520#define R92C_RRSR_SHORT 0x00800000 521 522/* Bits for R92C_EDCA_XX_PARAM. */ 523#define R92C_EDCA_PARAM_AIFS_M 0x000000ff 524#define R92C_EDCA_PARAM_AIFS_S 0 525#define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 526#define R92C_EDCA_PARAM_ECWMIN_S 8 527#define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 528#define R92C_EDCA_PARAM_ECWMAX_S 12 529#define R92C_EDCA_PARAM_TXOP_M 0xffff0000 530#define R92C_EDCA_PARAM_TXOP_S 16 531 532/* Bits for R92C_BCN_CTRL. */ 533#define R92C_BCN_CTRL_EN_MBSSID 0x02 534#define R92C_BCN_CTRL_TXBCN_RPT 0x04 535#define R92C_BCN_CTRL_EN_BCN 0x08 536#define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 537 538/* Bits for R92C_DRVERLYINT */ 539#define R92C_DRIVER_EARLY_INT_TIME 0x05 540 541/* Bits for R92C_BCNDMATIM */ 542#define R92C_DMA_ATIME_INT_TIME 0x02 543 544/* Bits for R92C_APSD_CTRL. */ 545#define R92C_APSD_CTRL_OFF 0x40 546#define R92C_APSD_CTRL_OFF_STATUS 0x80 547 548/* Bits for R92C_BWOPMODE. */ 549#define R92C_BWOPMODE_11J 0x01 550#define R92C_BWOPMODE_5G 0x02 551#define R92C_BWOPMODE_20MHZ 0x04 552 553/* Bits for R92C_RCR. */ 554#define R92C_RCR_AAP 0x00000001 // Accept all unicast packet 555#define R92C_RCR_APM 0x00000002 // Accept physical match packet 556#define R92C_RCR_AM 0x00000004 // Accept multicast packet 557#define R92C_RCR_AB 0x00000008 // Accept broadcast packet 558#define R92C_RCR_ADD3 0x00000010 // Accept address 3 match packet 559#define R92C_RCR_APWRMGT 0x00000020 // Accept power management packet 560#define R92C_RCR_CBSSID_DATA 0x00000040 // Accept BSSID match packet (Data) 561#define R92C_RCR_CBSSID_BCN 0x00000080 // Accept BSSID match packet (Rx beacon, probe rsp) 562#define R92C_RCR_ACRC32 0x00000100 // Accept CRC32 error packet 563#define R92C_RCR_AICV 0x00000200 // Accept ICV error packet 564#define R92C_RCR_ADF 0x00000800 // Accept data type frame 565#define R92C_RCR_ACF 0x00001000 // Accept control type frame 566#define R92C_RCR_AMF 0x00002000 // Accept management type frame 567#define R92C_RCR_HTC_LOC_CTRL 0x00004000 // MFC<--HTC=1 MFC-->HTC=0 568#define R92C_RCR_MFBEN 0x00400000 569#define R92C_RCR_LSIGEN 0x00800000 570#define R92C_RCR_ENMBID 0x01000000 // Enable Multiple BssId. 571#define R92C_RCR_APP_BA_SSN 0x08000000 // Accept BA SSN 572#define R92C_RCR_APP_PHYSTS 0x10000000 573#define R92C_RCR_APP_ICV 0x20000000 574#define R92C_RCR_APP_MIC 0x40000000 575#define R92C_RCR_APPFCS 0x80000000 // WMAC append FCS after payload 576 577/* Bits for R92C_CAMCMD. */ 578#define R92C_CAMCMD_ADDR_M 0x0000ffff 579#define R92C_CAMCMD_ADDR_S 0 580#define R92C_CAMCMD_WRITE 0x00010000 581#define R92C_CAMCMD_CLR 0x40000000 582#define R92C_CAMCMD_POLLING 0x80000000 583 584 585/* 586 * Baseband registers. 587 */ 588#define R92C_FPGA0_RFMOD 0x800 589#define R92C_FPGA0_TXINFO 0x804 590#define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 591#define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 592#define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 593#define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 594#define R92C_TXAGC_A_CCK1_MCS32 0xe08 595#define R92C_FPGA0_XA_HSSIPARAM1 0x820 596#define R92C_TXAGC_B_CCK1_55_MCS32 0x838 597#define R92C_FPGA0_XCD_SWITCHCTL 0x85c 598#define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 599#define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 600#define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 601#define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 602#define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 603#define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 604#define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 605#define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 606#define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 607#define R92C_FPGA0_ANAPARAM2 0x884 608#define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 609#define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 610#define R92C_FPGA1_RFMOD 0x900 611#define R92C_FPGA1_TXINFO 0x90c 612#define R92C_CCK0_SYSTEM 0xa00 613#define R92C_CCK0_AFESETTING 0xa04 614#define R92C_CONFIG_ANT_A 0xb68 615#define R92C_CONFIG_ANT_B 0xb6c 616#define R92C_OFDM0_TRXPATHENA 0xc04 617#define R92C_OFDM0_TRMUXPAR 0xc08 618#define R92C_OFDM0_XARXIQIMBALANCE 0xc14 619#define R92C_OFDM0_ECCATHRESHOLD 0xc4c 620#define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 621#define R92C_OFDM0_AGCPARAM1 0xc70 622#define R92C_OFDM0_AGCRSSITABLE 0xc78 623#define R92C_OFDM0_HTSTFAGC 0xc7c 624#define R92C_OFDM0_XATXIQIMBALANCE 0xc80 625#define R92C_OFDM0_XBTXIQIMBALANCE 0xc88 626#define R92C_OFDM0_XCTXIQIMBALANCE 0xc90 627#define R92C_OFDM0_XCTXAFE 0xc94 628#define R92C_OFDM0_XDTXAFE 0xc9c 629#define R92C_OFDM0_RXIQEXTANTA 0xca0 630#define R92C_OFDM1_LSTF 0xd00 631#define R92C_FPGA0_IQK 0xe28 632#define R92C_TX_IQK 0xe40 633#define R92C_RX_IQK 0xe44 634#define R92C_BLUETOOTH 0xe6c 635#define R92C_RX_WAIT_CCA 0xe70 636#define R92C_TX_CCK_RFON 0xe74 637#define R92C_TX_CCK_BBON 0xe78 638#define R92C_TX_OFDM_RFON 0xe7c 639#define R92C_TX_OFDM_BBON 0xe80 640#define R92C_TX_TO_RX 0xe84 641#define R92C_TX_TO_TX 0xe88 642#define R92C_RX_CCK 0xe8c 643#define R92C_RX_OFDM 0xed0 644#define R92C_RX_WAIT_RIFS 0xed4 645#define R92C_RX_TO_RX 0xed8 646#define R92C_STANDBY 0xedc 647#define R92C_SLEEP 0xee0 648#define R92C_PMPD_ANAEN 0xeec 649 650 651/* Bits for R92C_FPGA[01]_RFMOD. */ 652#define R92C_RFMOD_40MHZ 0x00000001 653#define R92C_RFMOD_JAPAN 0x00000002 654#define R92C_RFMOD_CCK_TXSC 0x00000030 655#define R92C_RFMOD_CCK_EN 0x01000000 656#define R92C_RFMOD_OFDM_EN 0x02000000 657 658/* Bits for R92C_HSSI_PARAM1(i). */ 659#define R92C_HSSI_PARAM1_PI 0x00000100 660 661/* Bits for R92C_HSSI_PARAM2(i). */ 662#define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 663#define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 664#define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 665#define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 666#define R92C_HSSI_PARAM2_READ_ADDR_S 23 667#define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 668 669/* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 670#define R92C_TXAGC_A_CCK1_M 0x0000ff00 671#define R92C_TXAGC_A_CCK1_S 8 672 673/* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 674#define R92C_TXAGC_B_CCK11_M 0x000000ff 675#define R92C_TXAGC_B_CCK11_S 0 676#define R92C_TXAGC_A_CCK2_M 0x0000ff00 677#define R92C_TXAGC_A_CCK2_S 8 678#define R92C_TXAGC_A_CCK55_M 0x00ff0000 679#define R92C_TXAGC_A_CCK55_S 16 680#define R92C_TXAGC_A_CCK11_M 0xff000000 681#define R92C_TXAGC_A_CCK11_S 24 682 683/* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 684#define R92C_TXAGC_B_CCK1_M 0x0000ff00 685#define R92C_TXAGC_B_CCK1_S 8 686#define R92C_TXAGC_B_CCK2_M 0x00ff0000 687#define R92C_TXAGC_B_CCK2_S 16 688#define R92C_TXAGC_B_CCK55_M 0xff000000 689#define R92C_TXAGC_B_CCK55_S 24 690 691/* Bits for R92C_TXAGC_RATE18_06(x). */ 692#define R92C_TXAGC_RATE06_M 0x000000ff 693#define R92C_TXAGC_RATE06_S 0 694#define R92C_TXAGC_RATE09_M 0x0000ff00 695#define R92C_TXAGC_RATE09_S 8 696#define R92C_TXAGC_RATE12_M 0x00ff0000 697#define R92C_TXAGC_RATE12_S 16 698#define R92C_TXAGC_RATE18_M 0xff000000 699#define R92C_TXAGC_RATE18_S 24 700 701/* Bits for R92C_TXAGC_RATE54_24(x). */ 702#define R92C_TXAGC_RATE24_M 0x000000ff 703#define R92C_TXAGC_RATE24_S 0 704#define R92C_TXAGC_RATE36_M 0x0000ff00 705#define R92C_TXAGC_RATE36_S 8 706#define R92C_TXAGC_RATE48_M 0x00ff0000 707#define R92C_TXAGC_RATE48_S 16 708#define R92C_TXAGC_RATE54_M 0xff000000 709#define R92C_TXAGC_RATE54_S 24 710 711/* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 712#define R92C_TXAGC_MCS00_M 0x000000ff 713#define R92C_TXAGC_MCS00_S 0 714#define R92C_TXAGC_MCS01_M 0x0000ff00 715#define R92C_TXAGC_MCS01_S 8 716#define R92C_TXAGC_MCS02_M 0x00ff0000 717#define R92C_TXAGC_MCS02_S 16 718#define R92C_TXAGC_MCS03_M 0xff000000 719#define R92C_TXAGC_MCS03_S 24 720 721/* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 722#define R92C_TXAGC_MCS04_M 0x000000ff 723#define R92C_TXAGC_MCS04_S 0 724#define R92C_TXAGC_MCS05_M 0x0000ff00 725#define R92C_TXAGC_MCS05_S 8 726#define R92C_TXAGC_MCS06_M 0x00ff0000 727#define R92C_TXAGC_MCS06_S 16 728#define R92C_TXAGC_MCS07_M 0xff000000 729#define R92C_TXAGC_MCS07_S 24 730 731/* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 732#define R92C_TXAGC_MCS08_M 0x000000ff 733#define R92C_TXAGC_MCS08_S 0 734#define R92C_TXAGC_MCS09_M 0x0000ff00 735#define R92C_TXAGC_MCS09_S 8 736#define R92C_TXAGC_MCS10_M 0x00ff0000 737#define R92C_TXAGC_MCS10_S 16 738#define R92C_TXAGC_MCS11_M 0xff000000 739#define R92C_TXAGC_MCS11_S 24 740 741/* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 742#define R92C_TXAGC_MCS12_M 0x000000ff 743#define R92C_TXAGC_MCS12_S 0 744#define R92C_TXAGC_MCS13_M 0x0000ff00 745#define R92C_TXAGC_MCS13_S 8 746#define R92C_TXAGC_MCS14_M 0x00ff0000 747#define R92C_TXAGC_MCS14_S 16 748#define R92C_TXAGC_MCS15_M 0xff000000 749#define R92C_TXAGC_MCS15_S 24 750 751/* Bits for R92C_LSSI_PARAM(i). */ 752#define R92C_LSSI_PARAM_DATA_M 0x000fffff 753#define R92C_LSSI_PARAM_DATA_S 0 754#define R92C_LSSI_PARAM_ADDR_M 0x03f00000 755#define R92C_LSSI_PARAM_ADDR_S 20 756#define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 757#define R88E_LSSI_PARAM_ADDR_S 20 758 759/* Bits for R92C_FPGA0_ANAPARAM2. */ 760#define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 761 762/* Bits for R92C_LSSI_READBACK(i). */ 763#define R92C_LSSI_READBACK_DATA_M 0x000fffff 764#define R92C_LSSI_READBACK_DATA_S 0 765 766/* Bits for R92C_OFDM0_AGCCORE1(i). */ 767#define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 768#define R92C_OFDM0_AGCCORE1_GAIN_S 0 769 770/* 771 * USB registers. 772 */ 773#define R92C_USB_INFO 0xfe17 774#define R92C_TEST_USB_TXQS 0xfe48 775#define R92C_USB_SPECIAL_OPTION 0xfe55 776#define R92C_USB_HCPWM 0xfe57 777#define R92C_USB_HRPWM 0xfe58 778#define R92C_USB_DMA_AGG_TO 0xfe5b 779#define R92C_USB_AGG_TO 0xfe5c 780#define R92C_USB_AGG_TH 0xfe5d 781#define R92C_USB_VID 0xfe60 782#define R92C_USB_PID 0xfe62 783#define R92C_USB_OPTIONAL 0xfe64 784#define R92C_USB_EP 0xfe65 785#define R92C_USB_PHY 0xfe68 /* XXX: linux-3.7.4(rtlwifi/rtl8192ce/reg.h) has 0xfe66 */ 786#define R92C_USB_MAC_ADDR 0xfe70 787#define R92C_USB_STRING 0xfe80 788 789/* Bits for R92C_USB_SPECIAL_OPTION. */ 790#define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 791#define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL 0x10 792 793/* Bits for R92C_USB_EP. */ 794#define R92C_USB_EP_HQ_M 0x000f 795#define R92C_USB_EP_HQ_S 0 796#define R92C_USB_EP_NQ_M 0x00f0 797#define R92C_USB_EP_NQ_S 4 798#define R92C_USB_EP_LQ_M 0x0f00 799#define R92C_USB_EP_LQ_S 8 800 801/* Bits for R92C_RD_CTRL. */ 802#define R92C_RD_CTRL_DIS_EDCA_CNT_DWN __BIT(11) 803 804/* 805 * Firmware base address. 806 */ 807#define R92C_FW_START_ADDR 0x1000 808#define R92C_FW_PAGE_SIZE 4096 809 810 811/* 812 * RF (6052) registers. 813 */ 814#define R92C_RF_AC 0x00 815#define R92C_RF_IQADJ_G(i) (0x01 + (i)) 816#define R92C_RF_POW_TRSW 0x05 817#define R92C_RF_GAIN_RX 0x06 818#define R92C_RF_GAIN_TX 0x07 819#define R92C_RF_TXM_IDAC 0x08 820#define R92C_RF_BS_IQGEN 0x0f 821#define R92C_RF_MODE1 0x10 822#define R92C_RF_MODE2 0x11 823#define R92C_RF_RX_AGC_HP 0x12 824#define R92C_RF_TX_AGC 0x13 825#define R92C_RF_BIAS 0x14 826#define R92C_RF_IPA 0x15 827#define R92C_RF_POW_ABILITY 0x17 828#define R92C_RF_CHNLBW 0x18 829#define R92C_RF_RX_G1 0x1a 830#define R92C_RF_RX_G2 0x1b 831#define R92C_RF_RX_BB2 0x1c 832#define R92C_RF_RX_BB1 0x1d 833#define R92C_RF_RCK1 0x1e 834#define R92C_RF_RCK2 0x1f 835#define R92C_RF_TX_G(i) (0x20 + (i)) 836#define R92C_RF_TX_BB1 0x23 837#define R92C_RF_T_METER 0x24 838#define R92C_RF_SYN_G(i) (0x25 + (i)) 839#define R92C_RF_RCK_OS 0x30 840#define R92C_RF_TXPA_G(i) (0x31 + (i)) 841 842/* Bits for R92C_RF_AC. */ 843#define R92C_RF_AC_MODE_M 0x70000 844#define R92C_RF_AC_MODE_S 16 845#define R92C_RF_AC_MODE_STANDBY 1 846 847/* Bits for R92C_RF_CHNLBW. */ 848#define R92C_RF_CHNLBW_CHNL_M 0x003ff 849#define R92C_RF_CHNLBW_CHNL_S 0 850#define R92C_RF_CHNLBW_BW20 0x00400 851#define R88E_RF_CHNLBW_BW20 0x00c00 852#define R92C_RF_CHNLBW_LCSTART 0x08000 853 854 855/* 856 * CAM entries. 857 */ 858#define R92C_CAM_ENTRY_COUNT 32 859 860#define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 861#define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 862#define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 863 864/* Bits for R92C_CAM_CTL0(i). */ 865#define R92C_CAM_KEYID_M 0x00000003 866#define R92C_CAM_KEYID_S 0 867#define R92C_CAM_ALGO_M 0x0000001c 868#define R92C_CAM_ALGO_S 2 869#define R92C_CAM_ALGO_NONE 0 870#define R92C_CAM_ALGO_WEP40 1 871#define R92C_CAM_ALGO_TKIP 2 872#define R92C_CAM_ALGO_AES 4 873#define R92C_CAM_ALGO_WEP104 5 874#define R92C_CAM_VALID 0x00008000 875#define R92C_CAM_MACLO_M 0xffff0000 876#define R92C_CAM_MACLO_S 16 877 878/* Rate adaptation modes. */ 879#define R92C_RAID_11GN 1 880#define R92C_RAID_11N 3 881#define R92C_RAID_11BG 4 882#define R92C_RAID_11G 5 /* "pure" 11g */ 883#define R92C_RAID_11B 6 884 885 886/* Macros to access unaligned little-endian memory. */ 887#define LE_READ_2(x) ((x)[0] | ((x)[1]<<8)) 888#define LE_READ_4(x) ((x)[0] | ((x)[1]<<8) | ((x)[2]<<16) | ((x)[3]<<24)) 889 890/* 891 * Macros to access subfields in registers. 892 */ 893/* Mask and Shift (getter). */ 894#define MS(val, field) \ 895 (((val) & field##_M) >> field##_S) 896 897/* Shift and Mask (setter). */ 898#define SM(field, val) \ 899 (((val) << field##_S) & field##_M) 900 901/* Rewrite. */ 902#define RW(var, field, val) \ 903 (((var) & ~field##_M) | SM(field, val)) 904 905/* 906 * Firmware image header. 907 */ 908struct r92c_fw_hdr { 909 /* QWORD0 */ 910 uint16_t signature; 911 uint8_t category; 912 uint8_t function; 913 uint16_t version; 914 uint16_t subversion; 915 /* QWORD1 */ 916 uint8_t month; 917 uint8_t date; 918 uint8_t hour; 919 uint8_t minute; 920 uint16_t ramcodesize; 921 uint16_t reserved2; 922 /* QWORD2 */ 923 uint32_t svnidx; 924 uint32_t reserved3; 925 /* QWORD3 */ 926 uint32_t reserved4; 927 uint32_t reserved5; 928} __packed; 929 930/* 931 * Host to firmware commands. 932 */ 933struct r92c_fw_cmd { 934 uint8_t id; 935#define R92C_CMD_AP_OFFLOAD 0 936#define R92C_CMD_SET_PWRMODE 1 937#define R92C_CMD_JOINBSS_RPT 2 938#define R92C_CMD_RSVD_PAGE 3 939#define R92C_CMD_RSSI 4 940#define R92C_CMD_RSSI_SETTING 5 941#define R92C_CMD_MACID_CONFIG 6 942#define R92C_CMD_MACID_PS_MODE 7 943#define R92C_CMD_P2P_PS_OFFLOAD 8 944#define R92C_CMD_SELECTIVE_SUSPEND 9 945#define R92C_CMD_FLAG_EXT 0x80 946 947 uint8_t msg[5]; 948} __packed; 949 950/* Structure for R92C_CMD_RSSI_SETTING. */ 951struct r92c_fw_cmd_rssi { 952 uint8_t macid; 953 uint8_t reserved; 954 uint8_t pwdb; 955} __packed; 956 957/* Structure for R92C_CMD_MACID_CONFIG. */ 958struct r92c_fw_cmd_macid_cfg { 959 uint8_t mask[4]; 960 uint8_t macid; 961#define URTWN_MACID_BSS 0 962#define URTWN_MACID_BC 4 /* Broadcast. */ 963#define URTWN_MACID_VALID 0x80 964} __packed; 965 966/* 967 * RTL8192CU ROM image. 968 */ 969struct r92c_rom { 970 uint16_t id; /* 0x8192 */ 971 uint8_t reserved1[5]; 972 uint8_t dbg_sel; 973 uint16_t reserved2; 974 uint16_t vid; 975 uint16_t pid; 976 uint8_t usb_opt; 977 uint8_t ep_setting; 978 uint16_t reserved3; 979 uint8_t usb_phy; 980 uint8_t reserved4[3]; 981 uint8_t macaddr[6]; 982 uint8_t string[61]; /* "Realtek" */ 983 uint8_t subcustomer_id; 984 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 985 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 986 uint8_t ht40_2s_tx_pwr_diff[3]; 987 uint8_t ht20_tx_pwr_diff[3]; 988 uint8_t ofdm_tx_pwr_diff[3]; 989 uint8_t ht40_max_pwr[3]; 990 uint8_t ht20_max_pwr[3]; 991 uint8_t xtal_calib; 992 uint8_t tssi[R92C_MAX_CHAINS]; 993 uint8_t thermal_meter; 994 uint8_t rf_opt1; 995#define R92C_ROM_RF1_REGULATORY_M 0x07 996#define R92C_ROM_RF1_REGULATORY_S 0 997#define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 998#define R92C_ROM_RF1_BOARD_TYPE_S 5 999#define R92C_BOARD_TYPE_DONGLE 0 1000#define R92C_BOARD_TYPE_HIGHPA 1 1001#define R92C_BOARD_TYPE_MINICARD 2 1002#define R92C_BOARD_TYPE_SOLO 3 1003#define R92C_BOARD_TYPE_COMBO 4 1004 1005 uint8_t rf_opt2; 1006 uint8_t rf_opt3; 1007 uint8_t rf_opt4; 1008 uint8_t channel_plan; 1009 uint8_t version; 1010 uint8_t curstomer_id; 1011} __packed; 1012 1013/* Rx MAC descriptor. */ 1014struct r92c_rx_stat { 1015 uint32_t rxdw0; 1016#define R92C_RXDW0_PKTLEN_M 0x00003fff 1017#define R92C_RXDW0_PKTLEN_S 0 1018#define R92C_RXDW0_CRCERR 0x00004000 1019#define R92C_RXDW0_ICVERR 0x00008000 1020#define R92C_RXDW0_INFOSZ_M 0x000f0000 1021#define R92C_RXDW0_INFOSZ_S 16 1022#define R92C_RXDW0_QOS 0x00800000 1023#define R92C_RXDW0_SHIFT_M 0x03000000 1024#define R92C_RXDW0_SHIFT_S 24 1025#define R92C_RXDW0_PHYST 0x04000000 1026#define R92C_RXDW0_DECRYPTED 0x08000000 1027 1028 uint32_t rxdw1; 1029 uint32_t rxdw2; 1030#define R92C_RXDW2_PKTCNT_M 0x00ff0000 1031#define R92C_RXDW2_PKTCNT_S 16 1032 1033 uint32_t rxdw3; 1034#define R92C_RXDW3_RATE_M 0x0000003f 1035#define R92C_RXDW3_RATE_S 0 1036#define R92C_RXDW3_HT 0x00000040 1037#define R92C_RXDW3_HTC 0x00000400 1038 1039 uint32_t rxdw4; 1040 uint32_t rxdw5; 1041} __packed __aligned(4); 1042 1043/* Rx PHY descriptor. */ 1044struct r92c_rx_phystat { 1045 uint32_t phydw0; 1046 uint32_t phydw1; 1047 uint32_t phydw2; 1048 uint32_t phydw3; 1049 uint32_t phydw4; 1050 uint32_t phydw5; 1051 uint32_t phydw6; 1052 uint32_t phydw7; 1053} __packed __aligned(4); 1054 1055/* Rx PHY CCK descriptor. */ 1056struct r92c_rx_cck { 1057 uint8_t adc_pwdb[4]; 1058 uint8_t sq_rpt; 1059 uint8_t agc_rpt; 1060} __packed; 1061 1062struct r88e_rx_cck { 1063 uint8_t path_agc[2]; 1064 uint8_t sig_qual; 1065 uint8_t agc_rpt; 1066 uint8_t rpt_b; 1067 uint8_t reserved1; 1068 uint8_t noise_power; 1069 uint8_t path_cfotail[2]; 1070 uint8_t pcts_mask[2]; 1071 uint8_t stream_rxevm[2]; 1072 uint8_t path_rxsnr[2]; 1073 uint8_t noise_power_db_lsb; 1074 uint8_t reserved2[3]; 1075 uint8_t stream_csi[2]; 1076 uint8_t stream_target_csi[2]; 1077 uint8_t sig_evm; 1078 uint8_t reserved3; 1079 uint8_t reserved4; 1080} __packed; 1081 1082/* Tx MAC descriptor. */ 1083struct r92c_tx_desc { 1084 uint32_t txdw0; 1085#define R92C_TXDW0_PKTLEN_M 0x0000ffff 1086#define R92C_TXDW0_PKTLEN_S 0 1087#define R92C_TXDW0_OFFSET_M 0x00ff0000 1088#define R92C_TXDW0_OFFSET_S 16 1089#define R92C_TXDW0_BMCAST 0x01000000 1090#define R92C_TXDW0_LSG 0x04000000 1091#define R92C_TXDW0_FSG 0x08000000 1092#define R92C_TXDW0_OWN 0x80000000 1093 1094 uint32_t txdw1; 1095#define R92C_TXDW1_MACID_M 0x0000001f 1096#define R92C_TXDW1_MACID_S 0 1097#define R88E_TXDW1_MACID_M 0x0000003f 1098#define R88E_TXDW1_MACID_S 0 1099#define R92C_TXDW1_AGGEN 0x00000020 1100#define R92C_TXDW1_AGGBK 0x00000040 1101#define R92C_TXDW1_QSEL_M 0x00001f00 1102#define R92C_TXDW1_QSEL_S 8 1103#define R92C_TXDW1_QSEL_BE 0x00 1104#define R92C_TXDW1_QSEL_MGNT 0x12 1105#define R92C_TXDW1_RAID_M 0x000f0000 1106#define R92C_TXDW1_RAID_S 16 1107#define R92C_TXDW1_CIPHER_M 0x00c00000 1108#define R92C_TXDW1_CIPHER_S 22 1109#define R92C_TXDW1_CIPHER_NONE 0 1110#define R92C_TXDW1_CIPHER_RC4 1 1111#define R92C_TXDW1_CIPHER_AES 3 1112#define R92C_TXDW1_PKTOFF_M 0x7c000000 1113#define R92C_TXDW1_PKTOFF_S 26 1114 1115 uint32_t txdw2; 1116#define R88E_TXDW2_AGGBK 0x00010000 1117 1118 uint16_t txdw3; 1119 uint16_t txdseq; 1120 1121 uint32_t txdw4; 1122#define R92C_TXDW4_RTSRATE_M 0x0000003f 1123#define R92C_TXDW4_RTSRATE_S 0 1124#define R92C_TXDW4_QOS 0x00000040 1125#define R92C_TXDW4_HWSEQ 0x00000080 1126#define R92C_TXDW4_DRVRATE 0x00000100 1127#define R92C_TXDW4_CTS2SELF 0x00000800 1128#define R92C_TXDW4_RTSEN 0x00001000 1129#define R92C_TXDW4_HWRTSEN 0x00002000 1130#define R92C_TXDW4_SCO_M 0x003f0000 1131#define R92C_TXDW4_SCO_S 20 1132#define R92C_TXDW4_SCO_SCA 1 1133#define R92C_TXDW4_SCO_SCB 2 1134#define R92C_TXDW4_40MHZ 0x02000000 1135 1136 uint32_t txdw5; 1137#define R92C_TXDW5_DATARATE_M 0x0000003f 1138#define R92C_TXDW5_DATARATE_S 0 1139#define R92C_TXDW5_SGI 0x00000040 1140#define R92C_TXDW5_AGGNUM_M 0xff000000 1141#define R92C_TXDW5_AGGNUM_S 24 1142 1143 uint32_t txdw6; 1144 uint16_t txdsum; 1145 uint16_t pad; 1146} __packed __aligned(4); 1147 1148/* Values for IQ calibration. */ 1149#define R92C_IQK_TRXPATHENA 0x5600 1150#define R92C_IQK_TRMUXPAR 0x00e4 1151#define R92C_IQK_RFIFACESW1 0x8200 1152#define R92C_IQK_LSSI_PARAM 0x00010000 1153#define R92C_IQK_LSSI_RESTORE 0x00032ed3 1154#define R92C_IQK_CONFIG_ANT 0x00080000 1155#define R92C_TX_IQK_SETTING 0x01007c00 1156#define R92C_RX_IQK_SETTING 0x01004800 1157#define R92C_FPGA0_IQK_SETTING 0x80800000 1158