139223Sgibbs/* $NetBSD: sdmmcreg.h,v 1.34 2018/04/19 21:50:09 christos Exp $ */ 239223Sgibbs/* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */ 339223Sgibbs 439223Sgibbs/* 544579Sgibbs * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 639223Sgibbs * 739223Sgibbs * Permission to use, copy, modify, and distribute this software for any 839223Sgibbs * purpose with or without fee is hereby granted, provided that the above 939223Sgibbs * copyright notice and this permission notice appear in all copies. 1039223Sgibbs * 1139223Sgibbs * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1239223Sgibbs * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1339223Sgibbs * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1439223Sgibbs * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1539223Sgibbs * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1639223Sgibbs * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1739223Sgibbs * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1839223Sgibbs */ 1939223Sgibbs 2039223Sgibbs#ifndef _SDMMCREG_H_ 2139223Sgibbs#define _SDMMCREG_H_ 2239223Sgibbs 2339223Sgibbs/* MMC commands */ /* response type */ 2439223Sgibbs#define MMC_GO_IDLE_STATE 0 /* R0 */ 2539223Sgibbs#define MMC_SEND_OP_COND 1 /* R3 */ 2639223Sgibbs#define MMC_ALL_SEND_CID 2 /* R2 */ 2739223Sgibbs#define MMC_SET_RELATIVE_ADDR 3 /* R1 */ 2839223Sgibbs#define MMC_SWITCH 6 /* R1b */ 2945390Sphk#define MMC_SELECT_CARD 7 /* R1 */ 3039223Sgibbs#define MMC_SEND_EXT_CSD 8 /* R1 */ 3139223Sgibbs#define MMC_SEND_CSD 9 /* R2 */ 3239223Sgibbs#define MMC_SEND_CID 10 /* R2 */ 3339223Sgibbs#define MMC_STOP_TRANSMISSION 12 /* R1b */ 3439223Sgibbs#define MMC_SEND_STATUS 13 /* R1 */ 3539223Sgibbs#define MMC_INACTIVE_STATE 15 /* R0 */ 3639223Sgibbs#define MMC_SET_BLOCKLEN 16 /* R1 */ 3739223Sgibbs#define MMC_READ_BLOCK_SINGLE 17 /* R1 */ 3839223Sgibbs#define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ 3939223Sgibbs#define MMC_SEND_TUNING_BLOCK 19 /* R1 */ 4039223Sgibbs#define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */ 4139223Sgibbs#define MMC_SET_BLOCK_COUNT 23 /* R1 */ 4239223Sgibbs#define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ 4339223Sgibbs#define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ 4439223Sgibbs#define MMC_PROGRAM_CSD 27 /* R1 */ 4539223Sgibbs#define MMC_SET_WRITE_PROT 28 /* R1b */ 4639223Sgibbs#define MMC_SET_CLR_WRITE_PROT 29 /* R1b */ 4739223Sgibbs#define MMC_SET_SEND_WRITE_PROT 30 /* R1 */ 4839223Sgibbs#define MMC_TAG_SECTOR_START 32 /* R1 */ 4939223Sgibbs#define MMC_TAG_SECTOR_END 33 /* R1 */ 5039223Sgibbs#define MMC_UNTAG_SECTOR 34 /* R1 */ 5139223Sgibbs#define MMC_TAG_ERASE_GROUP_START 35 /* R1 */ 5239223Sgibbs#define MMC_TAG_ERASE_GROUP_END 36 /* R1 */ 5339223Sgibbs#define MMC_UNTAG_ERASE_GROUP 37 /* R1 */ 5439223Sgibbs#define MMC_ERASE 38 /* R1b */ 5539223Sgibbs#define MMC_LOCK_UNLOCK 42 /* R1b */ 5639223Sgibbs#define MMC_APP_CMD 55 /* R1 */ 5739223Sgibbs#define MMC_READ_OCR 58 /* R3 */ 5839223Sgibbs 5939223Sgibbs/* SD commands */ /* response type */ 6039223Sgibbs#define SD_SEND_RELATIVE_ADDR 3 /* R6 */ 6139223Sgibbs#define SD_SEND_SWITCH_FUNC 6 /* R1 */ 6239223Sgibbs#define SD_SEND_IF_COND 8 /* R7 */ 6339223Sgibbs#define SD_VOLTAGE_SWITCH 11 /* R1 */ 6439223Sgibbs#define SD_ERASE_WR_BLK_START 32 /* R1 */ 6539223Sgibbs#define SD_ERASE_WR_BLK_END 33 /* R1 */ 6639223Sgibbs 6739223Sgibbs/* SD application commands */ /* response type */ 6839223Sgibbs#define SD_APP_SET_BUS_WIDTH 6 /* R1 */ 6939223Sgibbs#define SD_APP_SD_STATUS 13 /* R1 */ 7039223Sgibbs#define SD_APP_SET_WR_BLK_ERASE_COUNT 23 /* R1 */ 7139223Sgibbs#define SD_APP_OP_COND 41 /* R3 */ 7239223Sgibbs#define SD_APP_SEND_SCR 51 /* R1 */ 7339223Sgibbs 7439223Sgibbs/* SD erase arguments */ 7539223Sgibbs#define SD_ERASE_DISCARD 0x00000001 7639223Sgibbs#define SD_ERASE_FULE 0x00000002 7739223Sgibbs 7839223Sgibbs/* OCR bits */ 7939223Sgibbs#define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */ 8039223Sgibbs#define MMC_OCR_HCS (1<<30) /* SD only */ 8139223Sgibbs#define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */ 8239223Sgibbs#define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */ 8339223Sgibbs#define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */ 8439223Sgibbs#define MMC_OCR_S18A (1<<24) 8539223Sgibbs#define MMC_OCR_3_5V_3_6V (1<<23) 8639223Sgibbs#define MMC_OCR_3_4V_3_5V (1<<22) 8739223Sgibbs#define MMC_OCR_3_3V_3_4V (1<<21) 8839223Sgibbs#define MMC_OCR_3_2V_3_3V (1<<20) 8941048Sgibbs#define MMC_OCR_3_1V_3_2V (1<<19) 9039223Sgibbs#define MMC_OCR_3_0V_3_1V (1<<18) 9141048Sgibbs#define MMC_OCR_2_9V_3_0V (1<<17) 9241048Sgibbs#define MMC_OCR_2_8V_2_9V (1<<16) 9341048Sgibbs#define MMC_OCR_2_7V_2_8V (1<<15) 9439223Sgibbs#define MMC_OCR_2_6V_2_7V (1<<14) 9539223Sgibbs#define MMC_OCR_2_5V_2_6V (1<<13) 9644579Sgibbs#define MMC_OCR_2_4V_2_5V (1<<12) 9739223Sgibbs#define MMC_OCR_2_3V_2_4V (1<<11) 9839223Sgibbs#define MMC_OCR_2_2V_2_3V (1<<10) 9941048Sgibbs#define MMC_OCR_2_1V_2_2V (1<<9) 10039223Sgibbs#define MMC_OCR_2_0V_2_1V (1<<8) 10139223Sgibbs#define MMC_OCR_1_65V_1_95V (1<<7) 10239223Sgibbs 10340265Simp/* R1 response type bits */ 10439223Sgibbs#define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ 10539223Sgibbs#define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */ 10639223Sgibbs#define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ 10741048Sgibbs 10840265Simp/* 48-bit response decoding (32 bits w/o CRC) */ 10940160Simp#define MMC_R1(resp) ((resp)[0]) 11040160Simp#define MMC_R3(resp) ((resp)[0]) 11139223Sgibbs#define SD_R6(resp) ((resp)[0]) 11239223Sgibbs#define MMC_R7(resp) ((resp)[0]) 11339223Sgibbs#define MMC_SPI_R1(resp) ((resp)[0]) 11439223Sgibbs#define MMC_SPI_R7(resp) ((resp)[1]) 11539223Sgibbs 11639223Sgibbs/* RCA argument and response */ 11739223Sgibbs#define MMC_ARG_RCA(rca) ((rca) << 16) 11839223Sgibbs#define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) 11939223Sgibbs 12044579Sgibbs/* bus width argument */ 12145390Sphk#define SD_ARG_BUS_WIDTH_1 0 12239223Sgibbs#define SD_ARG_BUS_WIDTH_4 2 12339223Sgibbs 12439223Sgibbs/* EXT_CSD fields */ 12539223Sgibbs#define EXT_CSD_FLUSH_CACHE 32 /* W/E_P */ 12639223Sgibbs#define EXT_CSD_CACHE_CTRL 33 /* R/W/E_P */ 12744579Sgibbs#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 12844579Sgibbs#define EXT_CSD_BUS_WIDTH 183 /* W/E_P */ 12939223Sgibbs#define EXT_CSD_HS_TIMING 185 /* R/W/E_P */ 13040160Simp#define EXT_CSD_REV 192 /* R */ 13139223Sgibbs#define EXT_CSD_STRUCTURE 194 /* R */ 13239223Sgibbs#define EXT_CSD_CARD_TYPE 196 /* R */ 13339223Sgibbs#define EXT_CSD_SEC_COUNT 212 /* R */ 13439223Sgibbs#define EXT_CSD_CACHE_SIZE 249 /* R (4 bytes) */ 13539223Sgibbs 13639223Sgibbs/* EXT_CSD field definitions */ 13739223Sgibbs#define EXT_CSD_CMD_SET_NORMAL (1U << 0) 13839223Sgibbs#define EXT_CSD_CMD_SET_SECURE (1U << 1) 13939223Sgibbs#define EXT_CSD_CMD_SET_CPSECURE (1U << 2) 14039223Sgibbs 14139223Sgibbs/* EXT_CSD_FLUSH_CACHE */ 14239223Sgibbs#define EXT_CSD_FLUSH_CACHE_FLUSH (1U << 0) 14339223Sgibbs#define EXT_CSD_FLUSH_CACHE_BARRIER (1U << 1) 14439223Sgibbs 14539223Sgibbs/* EXT_CSD_CACHE_CTRL */ 14639223Sgibbs#define EXT_CSD_CACHE_CTRL_CACHE_EN (1U << 0) 14739223Sgibbs 14839223Sgibbs/* EXT_CSD_BUS_WIDTH */ 14939223Sgibbs#define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */ 15039223Sgibbs#define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */ 15139223Sgibbs#define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */ 15239223Sgibbs#define EXT_CSD_BUS_WIDTH_4_DDR 5 /* 4 bit mode (DDR) */ 15339223Sgibbs#define EXT_CSD_BUS_WIDTH_8_DDR 6 /* 8 bit mode (DDR) */ 15439223Sgibbs 15539223Sgibbs/* EXT_CSD_HS_TIMING */ 15639223Sgibbs#define EXT_CSD_HS_TIMING_LEGACY 0 15739223Sgibbs#define EXT_CSD_HS_TIMING_HIGHSPEED 1 15839223Sgibbs#define EXT_CSD_HS_TIMING_HS200 2 15939223Sgibbs#define EXT_CSD_HS_TIMING_HS400 3 16039223Sgibbs 16139223Sgibbs/* EXT_CSD_STRUCTURE */ 16239223Sgibbs#define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */ 16339223Sgibbs#define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */ 16439223Sgibbs#define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */ 16539223Sgibbs 16639223Sgibbs/* EXT_CSD_CARD_TYPE */ 16739223Sgibbs#define EXT_CSD_CARD_TYPE_F_26M (1 << 0) /* HS 26 MHz */ 16839223Sgibbs#define EXT_CSD_CARD_TYPE_F_52M (1 << 1) /* HS 52 MHz */ 16939223Sgibbs#define EXT_CSD_CARD_TYPE_F_DDR52_1_8V (1 << 2) /* HS DDR 52 MHz 1.8V or 3V */ 17039223Sgibbs#define EXT_CSD_CARD_TYPE_F_DDR52_1_2V (1 << 3) /* HS DDR 52 MHz 1.2V */ 17139223Sgibbs#define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4) /* HS200 SDR 200 MHz 1.8V */ 17239223Sgibbs#define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5) /* HS200 SDR 200 MHz 1.2V */ 17339223Sgibbs#define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6) /* HS400 DDR 200 MHz 1.8V */ 17439223Sgibbs#define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7) /* HS400 DDR 200 MHz 1.2V */ 17539223Sgibbs 17639223Sgibbs/* EXT_CSD_RST_N_FUNCTION */ 17739223Sgibbs#define EXT_CSD_RST_N_TMP_DISABLED 0x00 17839223Sgibbs#define EXT_CSD_RST_N_PERM_ENABLED 0x01 17939223Sgibbs#define EXT_CSD_RST_N_PERM_DISABLED 0x02 18039223Sgibbs#define EXT_CSD_RST_N_MASK 0x03 18139223Sgibbs 18239223Sgibbs/* MMC_SWITCH access mode */ 18339223Sgibbs#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 18439223Sgibbs#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ 18539223Sgibbs#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ 18639223Sgibbs#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 18739223Sgibbs 18839223Sgibbs/* SPI mode reports R1/R2(SEND_STATUS) status. */ 18939223Sgibbs#define R1_SPI_IDLE (1 << 0) 19039223Sgibbs#define R1_SPI_ERASE_RESET (1 << 1) 19139223Sgibbs#define R1_SPI_ILLEGAL_COMMAND (1 << 2) 19239223Sgibbs#define R1_SPI_COM_CRC (1 << 3) 19339223Sgibbs#define R1_SPI_ERASE_SEQ (1 << 4) 19439223Sgibbs#define R1_SPI_ADDRESS (1 << 5) 19539223Sgibbs#define R1_SPI_PARAMETER (1 << 6) 19639223Sgibbs/* R1 bit 7 is always zero */ 19739223Sgibbs#define R2_SPI_CARD_LOCKED (1 << 8) 19839223Sgibbs#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ 19939223Sgibbs#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP 20039223Sgibbs#define R2_SPI_ERROR (1 << 10) 20139223Sgibbs#define R2_SPI_CC_ERROR (1 << 11) 20239223Sgibbs#define R2_SPI_CARD_ECC_ERROR (1 << 12) 20339223Sgibbs#define R2_SPI_WP_VIOLATION (1 << 13) 20439223Sgibbs#define R2_SPI_ERASE_PARAM (1 << 14) 20539223Sgibbs#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ 20639223Sgibbs#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE 20739223Sgibbs 20839223Sgibbs/* MMC R2 response (CSD) */ 20939223Sgibbs#define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 21039223Sgibbs#define MMC_CSD_CSDVER_1_0 0 21139223Sgibbs#define MMC_CSD_CSDVER_1_1 1 21239223Sgibbs#define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */ 21339223Sgibbs#define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ 21439223Sgibbs#define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 21539223Sgibbs#define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ 21639223Sgibbs#define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ 21739223Sgibbs#define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ 21839223Sgibbs#define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ 21939223Sgibbs#define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */ 22039223Sgibbs#define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 22139223Sgibbs#define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4) 22239223Sgibbs#define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3) 22339223Sgibbs#define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 22439223Sgibbs#define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 22539223Sgibbs#define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) 22639223Sgibbs#define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) 22739223Sgibbs#define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 22839223Sgibbs#define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 22939223Sgibbs#define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ 23039223Sgibbs (MMC_CSD_C_SIZE_MULT((resp))+2)) 23139223Sgibbs#define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 23239223Sgibbs#define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 23339223Sgibbs#define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 23439223Sgibbs 23539223Sgibbs/* MMC v1 R2 response (CID) */ 23639223Sgibbs#define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) 23739223Sgibbs#define MMC_CID_PNM_V1_CPY(resp, pnm) \ 23839223Sgibbs do { \ 23939223Sgibbs (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 24039223Sgibbs (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 24139223Sgibbs (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 24239223Sgibbs (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 24339223Sgibbs (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 24439223Sgibbs (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 24539223Sgibbs (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ 24639223Sgibbs (pnm)[7] = '\0'; \ 24739223Sgibbs } while (/*CONSTCOND*/0) 24839223Sgibbs#define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) 24939223Sgibbs#define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) 25039223Sgibbs#define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) 25139223Sgibbs 25239223Sgibbs/* MMC v2 R2 response (CID) */ 25339223Sgibbs#define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) 25439223Sgibbs#define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) 25539223Sgibbs#define MMC_CID_PNM_V2_CPY(resp, pnm) \ 25639223Sgibbs do { \ 25739223Sgibbs (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 25839223Sgibbs (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 25939223Sgibbs (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 26039223Sgibbs (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 26139223Sgibbs (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 26239223Sgibbs (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ 26339223Sgibbs (pnm)[6] = '\0'; \ 26439223Sgibbs } while (/*CONSTCOND*/0) 26539223Sgibbs#define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) 26639223Sgibbs 26739223Sgibbs/* SD R2 response (CSD) */ 26839223Sgibbs#define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) 26939223Sgibbs#define SD_CSD_CSDVER_1_0 0 27039223Sgibbs#define SD_CSD_CSDVER_2_0 1 27139223Sgibbs#define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) 27239223Sgibbs#define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) 27339223Sgibbs#define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4) 27439223Sgibbs#define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3) 27539223Sgibbs#define SD_CSD_TAAC_1_5_MSEC 0x26 276#define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) 277#define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) 278#define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) 279#define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) 280#define SD_CSD_SPEED_25_MHZ 0x32 281#define SD_CSD_SPEED_50_MHZ 0x5a 282#define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) 283#define SD_CSD_CCC_BASIC (1 << 0) /* basic */ 284#define SD_CSD_CCC_BR (1 << 2) /* block read */ 285#define SD_CSD_CCC_BW (1 << 4) /* block write */ 286#define SD_CSD_CCC_ERACE (1 << 5) /* erase */ 287#define SD_CSD_CCC_WP (1 << 6) /* write protection */ 288#define SD_CSD_CCC_LC (1 << 7) /* lock card */ 289#define SD_CSD_CCC_AS (1 << 8) /*application specific*/ 290#define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ 291#define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ 292#define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) 293#define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) 294#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) 295#define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) 296#define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) 297#define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) 298#define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ 299 (SD_CSD_C_SIZE_MULT((resp))+2)) 300#define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) 301#define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) 302#define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) 303#define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) 304#define SD_CSD_VDD_RW_CURR_100mA 0x7 305#define SD_CSD_VDD_RW_CURR_80mA 0x6 306#define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) 307#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 308#define SD_CSD_V2_BL_LEN 0x9 /* 512 */ 309#define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) 310#define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) 311#define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ 312#define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ 313#define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) 314#define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) 315#define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) 316#define SD_CSD_RW_BL_LEN_2G 0xa 317#define SD_CSD_RW_BL_LEN_1G 0x9 318#define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) 319#define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) 320#define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) 321#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) 322#define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) 323#define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) 324 325/* SD R2 response (CID) */ 326#define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) 327#define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) 328#define SD_CID_PNM_CPY(resp, pnm) \ 329 do { \ 330 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ 331 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ 332 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ 333 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ 334 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ 335 (pnm)[5] = '\0'; \ 336 } while (/*CONSTCOND*/0) 337#define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) 338#define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) 339#define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) 340 341/* SCR (SD Configuration Register) */ 342#define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) 343#define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ 344#define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) 345#define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ 346#define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ 347#define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ 348#define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) 349#define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) 350#define SCR_SD_SECURITY_NONE 0 /* no security */ 351#define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ 352#define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ 353#define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) 354#define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ 355#define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ 356#define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) 357#define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) 358#define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9) 359#define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) 360#define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) 361#define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) 362 363/* SSR (SD Status Register) */ 364#define SSR_DAT_BUS_WIDTH(resp) __bitfield((resp), 510, 2) 365#define SSR_DAT_BUS_WIDTH_1 0 366#define SSR_DAT_BUS_WIDTH_4 2 367#define SSR_SECURED_MODE(resp) __bitfield((resp), 509, 1) 368#define SSR_SD_CARD_TYPE(resp) __bitfield((resp), 480, 16) 369#define SSR_SD_CARD_TYPE_RDWR 0 370#define SSR_SD_CARD_TYPE_ROM 1 371#define SSR_SD_CARD_TYPE_OTP 2 372#define SSR_SIZE_OF_PROTECTED_AREA(resp) __bitfield((resp), 448, 32) 373#define SSR_SPEED_CLASS(resp) __bitfield((resp), 440, 8) 374#define SSR_SPEED_CLASS_0 0 375#define SSR_SPEED_CLASS_2 1 376#define SSR_SPEED_CLASS_4 2 377#define SSR_SPEED_CLASS_6 3 378#define SSR_SPEED_CLASS_10 4 379#define SSR_PERFORMANCE_MOVE(resp) __bitfield((resp), 432, 8) 380#define SSR_AU_SIZE(resp) __bitfield((resp), 428, 4) 381#define SSR_ERASE_SIZE(resp) __bitfield((resp), 408, 16) 382#define SSR_ERASE_TIMEOUT(resp) __bitfield((resp), 402, 6) 383#define SSR_ERASE_OFFSET(resp) __bitfield((resp), 400, 2) 384#define SSR_UHS_SPEED_GRADE(resp) __bitfield((resp), 396, 4) 385#define SSR_UHS_SPEED_GRADE_10MB 1 386#define SSR_UHS_SPEED_GRADE_30MB 3 387#define SSR_UHS_AU_SIZE(resp) __bitfield((resp), 392, 4) 388#define SSR_VIDEO_SPEED_CLASS(resp) __bitfield((resp), 384, 8) 389#define SSR_VSC_AU_SIZE(resp) __bitfield((resp), 368, 10) 390#define SSR_SUS_ADDR(resp) __bitfield((resp), 346, 22) 391#define SSR_APP_PERF_CLASS(resp) __bitfield((resp), 336, 4) 392#define SSR_APP_PERF_CLASS_UNSUPPORTED 0 393#define SSR_APP_PERF_CLASS_A1 1 394#define SSR_APP_PERF_CLASS_A2 2 395#define SSR_PERFORMANCE_ENHANCE(resp) __bitfield((resp), 328, 8) 396#define SSR_DISCARD_SUPPORT(resp) __bitfield((resp), 313, 1) 397#define SSR_FULE_SUPPORT(resp) __bitfield((resp), 312, 1) 398 399/* Status of Switch Function */ 400#define SFUNC_STATUS_GROUP(status, group) \ 401 (__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16)) 402 403#define SD_ACCESS_MODE_SDR12 0 404#define SD_ACCESS_MODE_SDR25 1 405#define SD_ACCESS_MODE_SDR50 2 406#define SD_ACCESS_MODE_SDR104 3 407#define SD_ACCESS_MODE_DDR50 4 408 409/* This assumes the response fields are in host byte order in 32-bit units. */ 410#define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len)) 411static __inline uint32_t 412__bitfield(const uint32_t *src, size_t start, size_t len) 413{ 414 if (start + len > 512 || len == 0 || len > 32) 415 return 0; 416 417 src += start / 32; 418 start %= 32; 419 420 uint32_t dst = src[0] >> start; 421 422 if (__predict_false((start + len - 1) / 32 != start / 32)) { 423 dst |= src[1] << (32 - start); 424 } 425 426 return dst & (__BIT(len) - 1); 427} 428 429#endif /* _SDMMCREG_H_ */ 430