191094Sdes/* $NetBSD$ */ 292289Sdes 391094Sdes/* 491094Sdes * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 591094Sdes * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 699158Sdes * 799158Sdes * Permission is hereby granted, free of charge, to any person obtaining a 899158Sdes * copy of this software and associated documentation files (the "Software"), 991094Sdes * to deal in the Software without restriction, including without limitation 1091094Sdes * the rights to use, copy, modify, merge, publish, distribute, sub license, 1191094Sdes * and/or sell copies of the Software, and to permit persons to whom the 1291094Sdes * Software is furnished to do so, subject to the following conditions: 1391094Sdes * 1491094Sdes * The above copyright notice and this permission notice (including the 1591094Sdes * next paragraph) shall be included in all copies or substantial portions 1691094Sdes * of the Software. 1791094Sdes * 1891094Sdes * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1991094Sdes * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2091094Sdes * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 2191094Sdes * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2291094Sdes * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2391094Sdes * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2491094Sdes * DEALINGS IN THE SOFTWARE. 2591094Sdes */ 2691094Sdes 2791094Sdes#ifndef _DEV_PCI_UNICHROMEACCEL_H 2891094Sdes#define _DEV_PCI_UNICHROMEACCEL_H 2991094Sdes 3091094Sdes/* To be included in fb.h */ 3191094Sdes#ifndef FB_ACCEL_VIA_UNICHROME 3291094Sdes#define FB_ACCEL_VIA_UNICHROME 50 3391094Sdes#endif 3499158Sdes 3591094Sdes/* MMIO Base Address Definition */ 3691094Sdes#define MMIO_VGABASE 0x8000 3791094Sdes#define MMIO_CR_READ MMIO_VGABASE + 0x3D4 3891094Sdes#define MMIO_CR_WRITE MMIO_VGABASE + 0x3D5 3991094Sdes#define MMIO_SR_READ MMIO_VGABASE + 0x3C4 4091094Sdes#define MMIO_SR_WRITE MMIO_VGABASE + 0x3C5 4191094Sdes 4291094Sdes#define MMIO_OUT8(reg, val) \ 4391094Sdes bus_space_write_1(sc->sc_memt, sc->sc_memh, reg, val) 4491094Sdes#define MMIO_OUT16(reg, val) \ 4591094Sdes bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, val) 4691094Sdes#define MMIO_OUT32(reg, val) \ 4791094Sdes bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val) 4891094Sdes#define MMIO_IN8(reg) \ 4991094Sdes bus_space_read_1(sc->sc_memt, sc->sc_memh, reg) 5091094Sdes#define MMIO_IN16(reg) \ 5191094Sdes bus_space_read_2(sc->sc_memt, sc->sc_memh, reg) 5291094Sdes#define MMIO_IN32(reg) \ 5391094Sdes bus_space_read_4(sc->sc_memt, sc->sc_memh, reg) 5491094Sdes 5591094Sdes/* HW Cursor Status Define */ 5691094Sdes#define HW_Cursor_ON 0 5791094Sdes#define HW_Cursor_OFF 1 5891094Sdes 5991094Sdes/* Initial HW cursor flag */ 6091094Sdes#if 0 6191094Sdesstatic int MAX_CURS = 32; 6291094Sdesstatic int HW_Cursor_Init = 1; 6391094Sdes#endif 6491100Sdes 6591094Sdes#define CURSOR_SIZE (8 * 1024) 6691094Sdes#define VQ_SIZE (256 * 1024) 6791094Sdes 6891094Sdes#define VIA_MMIO_BLTBASE 0x200000 6991094Sdes#define VIA_MMIO_BLTSIZE 0x200000 7091094Sdes 7191094Sdes/* Defines for 2D registers */ 7291094Sdes#define VIA_REG_GECMD 0x000 7391094Sdes#define VIA_REG_GEMODE 0x004 7491094Sdes#define VIA_REG_SRCPOS 0x008 7591094Sdes#define VIA_REG_DSTPOS 0x00C 7691094Sdes#define VIA_REG_DIMENSION 0x010 /* width and height */ 7791094Sdes#define VIA_REG_PATADDR 0x014 7891094Sdes#define VIA_REG_FGCOLOR 0x018 7991094Sdes#define VIA_REG_BGCOLOR 0x01C 8091094Sdes#define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ 8191094Sdes#define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ 8291094Sdes#define VIA_REG_OFFSET 0x028 8391094Sdes#define VIA_REG_KEYCONTROL 0x02C /* color key control */ 8491094Sdes#define VIA_REG_SRCBASE 0x030 8591094Sdes#define VIA_REG_DSTBASE 0x034 8691094Sdes#define VIA_REG_PITCH 0x038 /* pitch of src and dst */ 8791094Sdes#define VIA_REG_MONOPAT0 0x03C 8891094Sdes#define VIA_REG_MONOPAT1 0x040 8991094Sdes#define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ 9091094Sdes 9191094Sdes/* VIA_REG_PITCH(0x38): Pitch Setting */ 9291094Sdes#define VIA_PITCH_ENABLE 0x80000000 9391094Sdes 9491094Sdes/* defines for VIA HW cursor registers */ 9591094Sdes#define VIA_REG_CURSOR_MODE 0x2D0 9691094Sdes#define VIA_REG_CURSOR_POS 0x2D4 9791094Sdes#define VIA_REG_CURSOR_ORG 0x2D8 9891094Sdes#define VIA_REG_CURSOR_BG 0x2DC 9991094Sdes#define VIA_REG_CURSOR_FG 0x2E0 10091094Sdes 10191094Sdes/* VIA_REG_GEMODE(0x04): GE mode */ 10291094Sdes#define VIA_GEM_8bpp 0x00000000 10391094Sdes#define VIA_GEM_16bpp 0x00000100 10491094Sdes#define VIA_GEM_32bpp 0x00000300 10591094Sdes 10691100Sdes/* defines for VIA 3D registers */ 10791094Sdes#define VIA_REG_STATUS 0x400 10891094Sdes#define VIA_REG_TRANSET 0x43C 10991094Sdes#define VIA_REG_TRANSPACE 0x440 11091094Sdes 11191094Sdes/* VIA_REG_STATUS(0x400): Engine Status */ 11291094Sdes#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ 11391094Sdes#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ 11491094Sdes#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ 11591094Sdes#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ 11691094Sdes 11791094Sdes#define MAXLOOP 0xFFFFFF 11891094Sdes 11991094Sdes#endif /* _DEV_PCI_UNICHROMEACCEL_H */ 12091094Sdes