svwsata.c revision 1.18
1/* $NetBSD: svwsata.c,v 1.18 2013/10/07 19:51:55 jakllsch Exp $ */ 2 3/* 4 * Copyright (c) 2005 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19#include <sys/cdefs.h> 20__KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.18 2013/10/07 19:51:55 jakllsch Exp $"); 21 22#include <sys/param.h> 23#include <sys/systm.h> 24 25#include <dev/ata/atareg.h> 26#include <dev/ata/satareg.h> 27#include <dev/ata/satavar.h> 28#include <dev/pci/pcivar.h> 29#include <dev/pci/pcidevs.h> 30#include <dev/pci/pciidereg.h> 31#include <dev/pci/pciidevar.h> 32#include <dev/pci/pciide_svwsata_reg.h> 33 34static int svwsata_match(device_t, cfdata_t, void *); 35static void svwsata_attach(device_t, device_t, void *); 36 37static void svwsata_chip_map(struct pciide_softc *, 38 const struct pci_attach_args *); 39static void svwsata_mapreg_dma(struct pciide_softc *, 40 const struct pci_attach_args *); 41static void svwsata_mapchan(struct pciide_channel *); 42 43CFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc), 44 svwsata_match, svwsata_attach, pciide_detach, NULL); 45 46static const struct pciide_product_desc pciide_svwsata_products[] = { 47 { PCI_PRODUCT_SERVERWORKS_K2_SATA, 48 0, 49 "ServerWorks K2 SATA Controller", 50 svwsata_chip_map 51 }, 52 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 53 0, 54 "ServerWorks Frodo4 SATA Controller", 55 svwsata_chip_map 56 }, 57 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 58 0, 59 "ServerWorks Frodo8 SATA Controller", 60 svwsata_chip_map 61 }, 62 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1, 63 0, 64 "ServerWorks HT-1000 SATA Controller", 65 svwsata_chip_map 66 }, 67 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2, 68 0, 69 "ServerWorks HT-1000 SATA Controller", 70 svwsata_chip_map 71 }, 72 { 0, 73 0, 74 NULL, 75 NULL, 76 } 77}; 78 79static int 80svwsata_match(device_t parent, cfdata_t match, void *aux) 81{ 82 struct pci_attach_args *pa = aux; 83 84 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 85 if (pciide_lookup_product(pa->pa_id, 86 pciide_svwsata_products)) 87 return (2); 88 } 89 return (0); 90} 91 92static void 93svwsata_attach(device_t parent, device_t self, void *aux) 94{ 95 struct pci_attach_args *pa = aux; 96 struct pciide_softc *sc = device_private(self); 97 98 sc->sc_wdcdev.sc_atac.atac_dev = self; 99 100 pciide_common_attach(sc, pa, 101 pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 102} 103 104static void 105svwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 106{ 107 struct pciide_channel *cp; 108 pci_intr_handle_t intrhandle; 109 pcireg_t interface; 110 const char *intrstr; 111 int channel; 112 113 /* The 4-port version has a dummy second function. */ 114 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 115 PCI_MAPREG_START + 0x14) == 0) { 116 aprint_normal("\n"); 117 return; 118 } 119 120 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 121 PCI_MAPREG_TYPE_MEM | 122 PCI_MAPREG_MEM_TYPE_32BIT, 0, 123 &sc->sc_ba5_st, &sc->sc_ba5_sh, 124 NULL, &sc->sc_ba5_ss) != 0) { 125 aprint_error(": unable to map BA5 register space\n"); 126 return; 127 } 128 129 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 130 "bus-master DMA support present"); 131 svwsata_mapreg_dma(sc, pa); 132 aprint_verbose("\n"); 133 134 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 135 136 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 137 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 138 if (sc->sc_dma_ok) { 139 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 140 sc->sc_wdcdev.irqack = pciide_irqack; 141 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 142 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 143 } 144 145 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 146 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 147 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 148 149 /* We can use SControl and SStatus to probe for drives. */ 150 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 151 sc->sc_wdcdev.wdc_maxdrives = 1; 152 153 wdc_allocate_regs(&sc->sc_wdcdev); 154 155 /* Map and establish the interrupt handler. */ 156 if(pci_intr_map(pa, &intrhandle) != 0) { 157 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 158 "couldn't map native-PCI interrupt\n"); 159 return; 160 } 161 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 162 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 163 pciide_pci_intr, sc); 164 if (sc->sc_pci_ih != NULL) { 165 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 166 "using %s for native-PCI interrupt\n", 167 intrstr ? intrstr : "unknown interrupt"); 168 } else { 169 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 170 "couldn't establish native-PCI interrupt"); 171 if (intrstr != NULL) 172 aprint_error(" at %s", intrstr); 173 aprint_error("\n"); 174 return; 175 } 176 177 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 178 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 179 180 181 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 182 channel++) { 183 cp = &sc->pciide_channels[channel]; 184 185 if (pciide_chansetup(sc, channel, interface) == 0) 186 continue; 187 svwsata_mapchan(cp); 188 } 189} 190 191static void 192svwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 193{ 194 struct pciide_channel *pc; 195 int chan, reg; 196 bus_size_t size; 197 198 sc->sc_wdcdev.dma_arg = sc; 199 sc->sc_wdcdev.dma_init = pciide_dma_init; 200 sc->sc_wdcdev.dma_start = pciide_dma_start; 201 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 202 203 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 204 PCIIDE_OPTIONS_NODMA) { 205 aprint_normal( 206 ", but unused (forced off by config file)"); 207 sc->sc_dma_ok = 0; 208 return; 209 } 210 211 /* 212 * Slice off a subregion of BA5 for each of the channel's DMA 213 * registers. 214 */ 215 216 sc->sc_dma_iot = sc->sc_ba5_st; 217 for (chan = 0; chan < 4; chan++) { 218 pc = &sc->pciide_channels[chan]; 219 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 220 size = 4; 221 if (size > (IDEDMA_SCH_OFFSET - reg)) 222 size = IDEDMA_SCH_OFFSET - reg; 223 if (bus_space_subregion(sc->sc_ba5_st, 224 sc->sc_ba5_sh, 225 (chan << 8) + SVWSATA_DMA + reg, 226 size, &pc->dma_iohs[reg]) != 0) { 227 sc->sc_dma_ok = 0; 228 aprint_normal(", but can't subregion offset " 229 "%lu size %lu", 230 (u_long) (chan << 8) + SVWSATA_DMA + reg, 231 (u_long) size); 232 return; 233 } 234 } 235 } 236 237 /* DMA registers all set up! */ 238 sc->sc_dmat = pa->pa_dmat; 239 sc->sc_dma_ok = 1; 240} 241 242static void 243svwsata_mapchan(struct pciide_channel *cp) 244{ 245 struct ata_channel *wdc_cp = &cp->ata_channel; 246 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 247 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 248 int i; 249 250 cp->compat = 0; 251 cp->ih = sc->sc_pci_ih; 252 253 wdr->cmd_iot = sc->sc_ba5_st; 254 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 255 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 256 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 257 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 258 "couldn't map %s cmd regs\n", cp->name); 259 goto bad; 260 } 261 262 wdr->ctl_iot = sc->sc_ba5_st; 263 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 264 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 265 &cp->ctl_baseioh) != 0) { 266 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 267 "couldn't map %s ctl regs\n", cp->name); 268 goto bad; 269 } 270 wdr->ctl_ioh = cp->ctl_baseioh; 271 272 for (i = 0; i < WDC_NREG; i++) { 273 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 274 i << 2, i == 0 ? 4 : 1, 275 &wdr->cmd_iohs[i]) != 0) { 276 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 277 "couldn't subregion %s channel cmd regs\n", 278 cp->name); 279 goto bad; 280 } 281 } 282 wdc_init_shadow_regs(wdc_cp); 283 wdr->data32iot = wdr->cmd_iot; 284 wdr->data32ioh = wdr->cmd_iohs[0]; 285 286 287 wdr->sata_iot = sc->sc_ba5_st; 288 wdr->sata_baseioh = sc->sc_ba5_sh; 289 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 290 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 291 &wdr->sata_status) != 0) { 292 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 293 "couldn't map channel %d sata_status regs\n", 294 wdc_cp->ch_channel); 295 goto bad; 296 } 297 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 298 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 299 &wdr->sata_error) != 0) { 300 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 301 "couldn't map channel %d sata_error regs\n", 302 wdc_cp->ch_channel); 303 goto bad; 304 } 305 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 306 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 307 &wdr->sata_control) != 0) { 308 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 309 "couldn't map channel %d sata_control regs\n", 310 wdc_cp->ch_channel); 311 goto bad; 312 } 313 314 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 315 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1, 316 bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 317 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1) 318 & ~0x00040000); 319 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 320 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 0xffffffff); 321 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 322 (wdc_cp->ch_channel << 8) + SVWSATA_SIM, 0); 323 324 wdcattach(wdc_cp); 325 return; 326 327 bad: 328 cp->ata_channel.ch_flags |= ATACH_DISABLED; 329} 330