svwsata.c revision 1.13
1206274Srdivacky/* $NetBSD: svwsata.c,v 1.13 2011/04/04 20:37:56 dyoung Exp $ */ 2206274Srdivacky 3206274Srdivacky/* 4206274Srdivacky * Copyright (c) 2005 Mark Kettenis 5206274Srdivacky * 6206274Srdivacky * Permission to use, copy, modify, and distribute this software for any 7206274Srdivacky * purpose with or without fee is hereby granted, provided that the above 8206274Srdivacky * copyright notice and this permission notice appear in all copies. 9206274Srdivacky * 10206274Srdivacky * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11206274Srdivacky * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12206274Srdivacky * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13206274Srdivacky * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14206274Srdivacky * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15206274Srdivacky * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16249423Sdim * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17249423Sdim */ 18206274Srdivacky 19206274Srdivacky#include <sys/cdefs.h> 20206274Srdivacky__KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.13 2011/04/04 20:37:56 dyoung Exp $"); 21206274Srdivacky 22249423Sdim#include <sys/param.h> 23249423Sdim#include <sys/systm.h> 24249423Sdim 25218893Sdim#include <dev/ata/atareg.h> 26206274Srdivacky#include <dev/ata/satareg.h> 27206274Srdivacky#include <dev/ata/satavar.h> 28206274Srdivacky#include <dev/pci/pcivar.h> 29206274Srdivacky#include <dev/pci/pcidevs.h> 30206274Srdivacky#include <dev/pci/pciidereg.h> 31206274Srdivacky#include <dev/pci/pciidevar.h> 32206274Srdivacky#include <dev/pci/pciide_svwsata_reg.h> 33206274Srdivacky 34206274Srdivackystatic int svwsata_match(device_t, cfdata_t, void *); 35206274Srdivackystatic void svwsata_attach(device_t, device_t, void *); 36263508Sdim 37206274Srdivackystatic void svwsata_chip_map(struct pciide_softc *, 38206274Srdivacky const struct pci_attach_args *); 39206274Srdivackystatic void svwsata_mapreg_dma(struct pciide_softc *, 40234353Sdim const struct pci_attach_args *); 41206274Srdivackystatic void svwsata_mapchan(struct pciide_channel *); 42206274Srdivacky 43206274SrdivackyCFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc), 44263508Sdim svwsata_match, svwsata_attach, NULL, NULL); 45206274Srdivacky 46206274Srdivackystatic const struct pciide_product_desc pciide_svwsata_products[] = { 47206274Srdivacky { PCI_PRODUCT_SERVERWORKS_K2_SATA, 48218893Sdim 0, 49249423Sdim "ServerWorks K2 SATA Controller", 50206274Srdivacky svwsata_chip_map 51206274Srdivacky }, 52206274Srdivacky { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 53206274Srdivacky 0, 54206274Srdivacky "ServerWorks Frodo4 SATA Controller", 55206274Srdivacky svwsata_chip_map 56249423Sdim }, 57206274Srdivacky { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 58206274Srdivacky 0, 59206274Srdivacky "ServerWorks Frodo8 SATA Controller", 60206274Srdivacky svwsata_chip_map 61249423Sdim }, 62206274Srdivacky { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1, 63206274Srdivacky 0, 64206274Srdivacky "ServerWorks HT-1000 SATA Controller", 65206274Srdivacky svwsata_chip_map 66206274Srdivacky }, 67206274Srdivacky { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2, 68206274Srdivacky 0, 69206274Srdivacky "ServerWorks HT-1000 SATA Controller", 70206274Srdivacky svwsata_chip_map 71206274Srdivacky }, 72206274Srdivacky { 0, 73206274Srdivacky 0, 74206274Srdivacky NULL, 75206274Srdivacky NULL, 76206274Srdivacky } 77206274Srdivacky}; 78206274Srdivacky 79206274Srdivackystatic int 80206274Srdivackysvwsata_match(device_t parent, cfdata_t match, void *aux) 81206274Srdivacky{ 82206274Srdivacky struct pci_attach_args *pa = aux; 83206274Srdivacky 84206274Srdivacky if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 85206274Srdivacky if (pciide_lookup_product(pa->pa_id, 86249423Sdim pciide_svwsata_products)) 87206274Srdivacky return (2); 88206274Srdivacky } 89206274Srdivacky return (0); 90206274Srdivacky} 91206274Srdivacky 92206274Srdivackystatic void 93206274Srdivackysvwsata_attach(device_t parent, device_t self, void *aux) 94206274Srdivacky{ 95206274Srdivacky struct pci_attach_args *pa = aux; 96206274Srdivacky struct pciide_softc *sc = device_private(self); 97206274Srdivacky 98206274Srdivacky sc->sc_wdcdev.sc_atac.atac_dev = self; 99206274Srdivacky 100206274Srdivacky pciide_common_attach(sc, pa, 101206274Srdivacky pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 102206274Srdivacky} 103206274Srdivacky 104249423Sdimstatic void 105249423Sdimsvwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 106206274Srdivacky{ 107206274Srdivacky struct pciide_channel *cp; 108206274Srdivacky pci_intr_handle_t intrhandle; 109206274Srdivacky pcireg_t interface; 110206274Srdivacky const char *intrstr; 111206274Srdivacky int channel; 112249423Sdim 113206274Srdivacky if (pciide_chipen(sc, pa) == 0) 114234353Sdim return; 115243830Sdim 116206274Srdivacky /* The 4-port version has a dummy second function. */ 117206274Srdivacky if (pci_conf_read(sc->sc_pc, sc->sc_tag, 118206274Srdivacky PCI_MAPREG_START + 0x14) == 0) { 119206274Srdivacky aprint_normal("\n"); 120206274Srdivacky return; 121206274Srdivacky } 122249423Sdim 123249423Sdim if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 124249423Sdim PCI_MAPREG_TYPE_MEM | 125249423Sdim PCI_MAPREG_MEM_TYPE_32BIT, 0, 126206274Srdivacky &sc->sc_ba5_st, &sc->sc_ba5_sh, 127249423Sdim NULL, &sc->sc_ba5_ss) != 0) { 128249423Sdim aprint_error(": unable to map BA5 register space\n"); 129249423Sdim return; 130249423Sdim } 131249423Sdim 132206274Srdivacky aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 133206274Srdivacky "bus-master DMA support present"); 134206274Srdivacky svwsata_mapreg_dma(sc, pa); 135206274Srdivacky aprint_verbose("\n"); 136206274Srdivacky 137206274Srdivacky sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 138206274Srdivacky 139206274Srdivacky sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 140206274Srdivacky sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 141206274Srdivacky if (sc->sc_dma_ok) { 142206274Srdivacky sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 143206274Srdivacky sc->sc_wdcdev.irqack = pciide_irqack; 144251662Sdim sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 145234353Sdim sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 146206274Srdivacky } 147206274Srdivacky 148249423Sdim sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 149206274Srdivacky sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 150206274Srdivacky sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 151249423Sdim 152206274Srdivacky /* We can use SControl and SStatus to probe for drives. */ 153206274Srdivacky sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 154206274Srdivacky 155206274Srdivacky wdc_allocate_regs(&sc->sc_wdcdev); 156249423Sdim 157206274Srdivacky /* Map and establish the interrupt handler. */ 158206274Srdivacky if(pci_intr_map(pa, &intrhandle) != 0) { 159206274Srdivacky aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 160249423Sdim "couldn't map native-PCI interrupt\n"); 161206274Srdivacky return; 162206274Srdivacky } 163249423Sdim intrstr = pci_intr_string(pa->pa_pc, intrhandle); 164206274Srdivacky sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 165206274Srdivacky pciide_pci_intr, sc); 166206274Srdivacky if (sc->sc_pci_ih != NULL) { 167206274Srdivacky aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 168206274Srdivacky "using %s for native-PCI interrupt\n", 169206274Srdivacky intrstr ? intrstr : "unknown interrupt"); 170206274Srdivacky } else { 171206274Srdivacky aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 172263508Sdim "couldn't establish native-PCI interrupt"); 173263508Sdim if (intrstr != NULL) 174263508Sdim aprint_error(" at %s", intrstr); 175263508Sdim aprint_error("\n"); 176263508Sdim return; 177263508Sdim } 178263508Sdim 179263508Sdim interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 180263508Sdim PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 181263508Sdim 182263508Sdim 183263508Sdim for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 184263508Sdim channel++) { 185263508Sdim cp = &sc->pciide_channels[channel]; 186263508Sdim 187263508Sdim if (pciide_chansetup(sc, channel, interface) == 0) 188263508Sdim continue; 189263508Sdim svwsata_mapchan(cp); 190263508Sdim } 191263508Sdim} 192263508Sdim 193263508Sdimstatic void 194221345Sdimsvwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 195221345Sdim{ 196 struct pciide_channel *pc; 197 int chan, reg; 198 bus_size_t size; 199 200 sc->sc_wdcdev.dma_arg = sc; 201 sc->sc_wdcdev.dma_init = pciide_dma_init; 202 sc->sc_wdcdev.dma_start = pciide_dma_start; 203 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 204 205 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 206 PCIIDE_OPTIONS_NODMA) { 207 aprint_normal( 208 ", but unused (forced off by config file)"); 209 sc->sc_dma_ok = 0; 210 return; 211 } 212 213 /* 214 * Slice off a subregion of BA5 for each of the channel's DMA 215 * registers. 216 */ 217 218 sc->sc_dma_iot = sc->sc_ba5_st; 219 for (chan = 0; chan < 4; chan++) { 220 pc = &sc->pciide_channels[chan]; 221 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 222 size = 4; 223 if (size > (IDEDMA_SCH_OFFSET - reg)) 224 size = IDEDMA_SCH_OFFSET - reg; 225 if (bus_space_subregion(sc->sc_ba5_st, 226 sc->sc_ba5_sh, 227 (chan << 8) + SVWSATA_DMA + reg, 228 size, &pc->dma_iohs[reg]) != 0) { 229 sc->sc_dma_ok = 0; 230 aprint_normal(", but can't subregion offset " 231 "%lu size %lu", 232 (u_long) (chan << 8) + SVWSATA_DMA + reg, 233 (u_long) size); 234 return; 235 } 236 } 237 } 238 239 /* DMA registers all set up! */ 240 sc->sc_dmat = pa->pa_dmat; 241 sc->sc_dma_ok = 1; 242} 243 244static void 245svwsata_mapchan(struct pciide_channel *cp) 246{ 247 struct ata_channel *wdc_cp = &cp->ata_channel; 248 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 249 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 250 int i; 251 252 cp->compat = 0; 253 cp->ih = sc->sc_pci_ih; 254 255 wdr->cmd_iot = sc->sc_ba5_st; 256 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 257 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 258 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 259 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 260 "couldn't map %s cmd regs\n", cp->name); 261 goto bad; 262 } 263 264 wdr->ctl_iot = sc->sc_ba5_st; 265 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 266 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 267 &cp->ctl_baseioh) != 0) { 268 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 269 "couldn't map %s ctl regs\n", cp->name); 270 goto bad; 271 } 272 wdr->ctl_ioh = cp->ctl_baseioh; 273 274 for (i = 0; i < WDC_NREG; i++) { 275 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 276 i << 2, i == 0 ? 4 : 1, 277 &wdr->cmd_iohs[i]) != 0) { 278 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 279 "couldn't subregion %s channel cmd regs\n", 280 cp->name); 281 goto bad; 282 } 283 } 284 wdc_init_shadow_regs(wdc_cp); 285 wdr->data32iot = wdr->cmd_iot; 286 wdr->data32ioh = wdr->cmd_iohs[0]; 287 288 289 wdr->sata_iot = sc->sc_ba5_st; 290 wdr->sata_baseioh = sc->sc_ba5_sh; 291 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 292 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 293 &wdr->sata_status) != 0) { 294 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 295 "couldn't map channel %d sata_status regs\n", 296 wdc_cp->ch_channel); 297 goto bad; 298 } 299 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 300 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 301 &wdr->sata_error) != 0) { 302 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 303 "couldn't map channel %d sata_error regs\n", 304 wdc_cp->ch_channel); 305 goto bad; 306 } 307 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 308 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 309 &wdr->sata_control) != 0) { 310 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 311 "couldn't map channel %d sata_control regs\n", 312 wdc_cp->ch_channel); 313 goto bad; 314 } 315 316 wdcattach(wdc_cp); 317 return; 318 319 bad: 320 cp->ata_channel.ch_flags |= ATACH_DISABLED; 321} 322