svwsata.c revision 1.1 
1/*	$NetBSD: svwsata.c,v 1.1 2006/03/06 18:35:24 bouyer Exp $	*/
2
3/*
4 * Copyright (c) 2005 Mark Kettenis
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <sys/cdefs.h>
20__KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.1 2006/03/06 18:35:24 bouyer Exp $");
21
22#include <sys/param.h>
23#include <sys/systm.h>
24
25#include <dev/ata/atareg.h>
26#include <dev/ata/satareg.h>
27#include <dev/ata/satavar.h>
28#include <dev/pci/pcivar.h>
29#include <dev/pci/pcidevs.h>
30#include <dev/pci/pciidereg.h>
31#include <dev/pci/pciidevar.h>
32#include <dev/pci/pciide_svwsata_reg.h>
33
34static int  svwsata_match(struct device *, struct cfdata *, void *);
35static void svwsata_attach(struct device *, struct device *, void *);
36
37static void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *) __unused;
38static void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *);
39static void svwsata_mapchan(struct pciide_channel *);
40static void svwsata_drv_probe(struct ata_channel *chp);
41
42CFATTACH_DECL(svwsata, sizeof(struct pciide_softc),
43    svwsata_match, svwsata_attach, NULL, NULL);
44
45static const struct pciide_product_desc pciide_svwsata_products[] =  {
46	{ PCI_PRODUCT_SERVERWORKS_K2_SATA,
47	  0,
48	  "ServerWorks K2 SATA Controller",
49	  svwsata_chip_map
50	},
51	{ 0,
52	  0,
53	  NULL,
54	  NULL,
55	}
56};
57
58static int
59svwsata_match(struct device *parent, struct cfdata *match, void *aux)
60{
61	struct pci_attach_args *pa = aux;
62
63	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) {
64		if (pciide_lookup_product(pa->pa_id,
65		    pciide_svwsata_products))
66			return (2);
67	}
68	return (0);
69}
70
71static void
72svwsata_attach(struct device *parent, struct device *self, void *aux)
73{
74	struct pci_attach_args *pa = aux;
75	struct pciide_softc *sc = (void *)self;
76
77	pciide_common_attach(sc, pa,
78	    pciide_lookup_product(pa->pa_id, pciide_svwsata_products));
79}
80
81static void
82svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
83{
84	struct pciide_channel *cp;
85	pci_intr_handle_t intrhandle;
86	pcireg_t interface;
87	const char *intrstr;
88	int channel;
89
90	if (pciide_chipen(sc, pa) == 0)
91		return;
92
93	if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
94			   PCI_MAPREG_TYPE_MEM |
95			   PCI_MAPREG_MEM_TYPE_32BIT, 0,
96			   &sc->sc_ba5_st, &sc->sc_ba5_sh,
97			   NULL, NULL) != 0) {
98		aprint_error(": unable to map BA5 register space\n");
99		return;
100	}
101
102	aprint_normal(": DMA");
103	svwsata_mapreg_dma(sc, pa);
104	aprint_normal("\n");
105
106	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
107	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
108	if (sc->sc_dma_ok) {
109		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
110		sc->sc_wdcdev.irqack = pciide_irqack;
111		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
112		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
113	}
114
115	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
116	sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
117	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
118
119	/* We can use SControl and SStatus to probe for drives. */
120	sc->sc_wdcdev.sc_atac.atac_probe = svwsata_drv_probe;
121
122	wdc_allocate_regs(&sc->sc_wdcdev);
123
124	/* Map and establish the interrupt handler. */
125	if(pci_intr_map(pa, &intrhandle) != 0) {
126		aprint_error("%s: couldn't map native-PCI interrupt\n",
127		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
128		return;
129	}
130	intrstr = pci_intr_string(pa->pa_pc, intrhandle);
131	sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
132	    pciide_pci_intr, sc);
133	if (sc->sc_pci_ih != NULL) {
134		aprint_normal("%s: using %s for native-PCI interrupt\n",
135		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
136		    intrstr ? intrstr : "unknown interrupt");
137	} else {
138		aprint_error("%s: couldn't establish native-PCI interrupt",
139		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
140		if (intrstr != NULL)
141			aprint_normal(" at %s", intrstr);
142		aprint_normal("\n");
143		return;
144	}
145
146	interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
147	    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
148
149
150	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
151	     channel++) {
152		cp = &sc->pciide_channels[channel];
153
154		if (pciide_chansetup(sc, channel, interface) == 0)
155			continue;
156		svwsata_mapchan(cp);
157	}
158}
159
160static void
161svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
162{
163	struct pciide_channel *pc;
164	int chan, reg;
165	bus_size_t size;
166
167	sc->sc_wdcdev.dma_arg = sc;
168	sc->sc_wdcdev.dma_init = pciide_dma_init;
169	sc->sc_wdcdev.dma_start = pciide_dma_start;
170	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
171
172	if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags &
173	    PCIIDE_OPTIONS_NODMA) {
174		aprint_normal(
175		    ", but unused (forced off by config file)");
176		sc->sc_dma_ok = 0;
177		return;
178	}
179
180	/*
181	 * Slice off a subregion of BA5 for each of the channel's DMA
182	 * registers.
183	 */
184
185	sc->sc_dma_iot = sc->sc_ba5_st;
186	for (chan = 0; chan < 4; chan++) {
187		pc = &sc->pciide_channels[chan];
188		for (reg = 0; reg < IDEDMA_NREGS; reg++) {
189			size = 4;
190			if (size > (IDEDMA_SCH_OFFSET - reg))
191				size = IDEDMA_SCH_OFFSET - reg;
192			if (bus_space_subregion(sc->sc_ba5_st,
193			    sc->sc_ba5_sh,
194			    (chan << 8) + SVWSATA_DMA + reg,
195			    size, &pc->dma_iohs[reg]) != 0) {
196				sc->sc_dma_ok = 0;
197				aprint_normal(", but can't subregion offset "
198				    "%lu size %lu",
199				    (u_long) (chan << 8) + SVWSATA_DMA + reg,
200				    (u_long) size);
201				return;
202			}
203		}
204	}
205
206	/* DMA registers all set up! */
207	sc->sc_dmat = pa->pa_dmat;
208	sc->sc_dma_ok = 1;
209}
210
211static void
212svwsata_mapchan(struct pciide_channel *cp)
213{
214	struct ata_channel *wdc_cp = &cp->ata_channel;
215	struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp);
216	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
217	int i;
218
219	cp->compat = 0;
220	cp->ih = sc->sc_pci_ih;
221
222	wdr->cmd_iot = sc->sc_ba5_st;
223	if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
224		(wdc_cp->ch_channel << 8) + SVWSATA_TF0,
225		SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) {
226		aprint_error("%s: couldn't map %s cmd regs\n",
227		       sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
228		goto bad;
229	}
230
231	wdr->ctl_iot = sc->sc_ba5_st;
232	if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
233		(wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4,
234		&cp->ctl_baseioh) != 0) {
235		aprint_error("%s: couldn't map %s ctl regs\n",
236		       sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
237		goto bad;
238	}
239	wdr->ctl_ioh = cp->ctl_baseioh;
240
241	for (i = 0; i < WDC_NREG; i++) {
242		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
243					i << 2, i == 0 ? 4 : 1,
244					&wdr->cmd_iohs[i]) != 0) {
245			aprint_error("%s: couldn't subregion %s channel "
246				     "cmd regs\n",
247			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
248			goto bad;
249		}
250	}
251	wdc_init_shadow_regs(wdc_cp);
252	wdr->data32iot = wdr->cmd_iot;
253	wdr->data32ioh = wdr->cmd_iohs[0];
254
255	wdcattach(wdc_cp);
256	return;
257
258 bad:
259	cp->ata_channel.ch_flags |= ATACH_DISABLED;
260}
261
262static void
263svwsata_drv_probe(struct ata_channel *chp)
264{
265	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
266	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
267	int channel = chp->ch_channel;
268	uint32_t scontrol, sstatus;
269	uint8_t scnt, sn, cl, ch;
270	int i, s;
271
272	/* XXX This should be done by other code. */
273	for (i = 0; i < 2; i++) {
274		chp->ch_drive[i].chnl_softc = chp;
275		chp->ch_drive[i].drive = i;
276	}
277
278	/*
279	 * Request communication initialization sequence, any speed.
280	 * Performing this is the equivalent of an ATA Reset.
281	 */
282	scontrol = SControl_DET_INIT | SControl_SPD_ANY;
283
284	/*
285	 * XXX We don't yet support SATA power management; disable all
286	 * power management state transitions.
287	 */
288	scontrol |= SControl_IPM_NONE;
289
290	bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
291	    (channel << 8) + SVWSATA_SCONTROL, scontrol);
292	delay(50 * 1000);
293	scontrol &= ~SControl_DET_INIT;
294	bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
295	    (channel << 8) + SVWSATA_SCONTROL, scontrol);
296	delay(50 * 1000);
297
298	sstatus = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh,
299	    (channel << 8) + SVWSATA_SSTATUS);
300#if 0
301	printf("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n",
302	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus,
303	    bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh,
304	        (channel << 8) + SVWSATA_SSTATUS));
305#endif
306	switch (sstatus & SStatus_DET_mask) {
307	case SStatus_DET_NODEV:
308		/* No device; be silent. */
309		break;
310
311	case SStatus_DET_DEV_NE:
312		aprint_error("%s: port %d: device connected, but "
313		    "communication not established\n",
314		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
315		break;
316
317	case SStatus_DET_OFFLINE:
318		aprint_error("%s: port %d: PHY offline\n",
319		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel);
320		break;
321
322	case SStatus_DET_DEV:
323		/*
324		 * XXX ATAPI detection doesn't currently work.  Don't
325		 * XXX know why.  But, it's not like the standard method
326		 * XXX can detect an ATAPI device connected via a SATA/PATA
327		 * XXX bridge, so at least this is no worse.  --thorpej
328		 */
329		bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
330		    WDSD_IBM | (0 << 4));
331		delay(10);	/* 400ns delay */
332		/* Save register contents. */
333		scnt = bus_space_read_1(wdr->cmd_iot,
334				        wdr->cmd_iohs[wd_seccnt], 0);
335		sn = bus_space_read_1(wdr->cmd_iot,
336				      wdr->cmd_iohs[wd_sector], 0);
337		cl = bus_space_read_1(wdr->cmd_iot,
338				      wdr->cmd_iohs[wd_cyl_lo], 0);
339		ch = bus_space_read_1(wdr->cmd_iot,
340				      wdr->cmd_iohs[wd_cyl_hi], 0);
341#if 0
342		printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
343		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
344		    scnt, sn, cl, ch);
345#endif
346		/*
347		 * scnt and sn are supposed to be 0x1 for ATAPI, but in some
348		 * cases we get wrong values here, so ignore it.
349		 */
350		s = splbio();
351		if (cl == 0x14 && ch == 0xeb)
352			chp->ch_drive[0].drive_flags |= DRIVE_ATAPI;
353		else
354			chp->ch_drive[0].drive_flags |= DRIVE_ATA;
355		splx(s);
356
357		aprint_normal("%s: port %d: device present, speed: %s\n",
358		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel,
359		    sata_speed(sstatus));
360		break;
361
362	default:
363		aprint_error("%s: port %d: unknown SStatus: 0x%08x\n",
364		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus);
365	}
366}
367