1/* $NetBSD: stpcide.c,v 1.26 2012/07/31 15:50:36 bouyer Exp $ */ 2 3/*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: stpcide.c,v 1.26 2012/07/31 15:50:36 bouyer Exp $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37 38#include <dev/pci/pcivar.h> 39#include <dev/pci/pcidevs.h> 40#include <dev/pci/pciidereg.h> 41#include <dev/pci/pciidevar.h> 42 43static void stpc_chip_map(struct pciide_softc *, 44 const struct pci_attach_args *); 45static void stpc_setup_channel(struct ata_channel *); 46 47static int stpcide_match(device_t, cfdata_t, void *); 48static void stpcide_attach(device_t, device_t, void *); 49 50const struct pciide_product_desc pciide_stpc_products[] = { 51 { 0x0228, 52 0, 53 "STMicroelectronics STPC IDE Controller", 54 stpc_chip_map, 55 }, 56 { 0, 0, NULL, NULL }, 57}; 58 59CFATTACH_DECL_NEW(stpcide, sizeof(struct pciide_softc), 60 stpcide_match, stpcide_attach, pciide_detach, NULL); 61 62static int 63stpcide_match(device_t parent, cfdata_t match, void *aux) 64{ 65 struct pci_attach_args *pa = aux; 66 67 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SGSTHOMSON) { 68 if (pciide_lookup_product(pa->pa_id, pciide_stpc_products)) 69 return (2); 70 } 71 return (0); 72} 73 74static void 75stpcide_attach(device_t parent, device_t self, void *aux) 76{ 77 struct pci_attach_args *pa = aux; 78 struct pciide_softc *sc = device_private(self); 79 80 sc->sc_wdcdev.sc_atac.atac_dev = self; 81 82 pciide_common_attach(sc, pa, 83 pciide_lookup_product(pa->pa_id, pciide_stpc_products)); 84 85} 86 87static void 88stpc_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 89{ 90 struct pciide_channel *cp; 91 int channel; 92 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 93 94 if (pciide_chipen(sc, pa) == 0) 95 return; 96 97 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 98 "bus-master DMA support present"); 99 pciide_mapreg_dma(sc, pa); 100 aprint_verbose("\n"); 101 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 102 if (sc->sc_dma_ok) { 103 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 104 sc->sc_wdcdev.irqack = pciide_irqack; 105 } 106 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 107 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 108 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 109 sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel; 110 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 111 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 112 sc->sc_wdcdev.wdc_maxdrives = 2; 113 114 wdc_allocate_regs(&sc->sc_wdcdev); 115 116 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 117 channel++) { 118 cp = &sc->pciide_channels[channel]; 119 if (pciide_chansetup(sc, channel, interface) == 0) 120 continue; 121 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 122 } 123} 124 125/* 126 * IDE timing register (0x40, 0x42, 0x44, and 0x46) assignment. 127 * 33MHz PCI system will have; 128 * DMA0 01-11-11 129 * DMA1 00-01-10 130 * DMA2 00-00-10 131 * PIO0 111-100 132 * PIO1 100-011 133 * PIO2 011-010 134 * PIO3 010-001 135 * PIO4 000-001 136 * MISC XYZW 137 */ 138static const u_int16_t dmatbl[] = { 0x7C00, 0x1800, 0x0800 }; 139static const u_int16_t piotbl[] = { 0x03C0, 0x0230, 0x01A0, 0x0110, 0x0010 }; 140 141static void 142stpc_setup_channel(struct ata_channel *chp) 143{ 144 struct atac_softc *atac = chp->ch_atac; 145 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 146 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 147 int channel = chp->ch_channel; 148 struct ata_drive_datas *drvp; 149 u_int32_t idedma_ctl, idetim; 150 int drive, bits[2], s; 151 152 /* setup DMA if needed */ 153 pciide_channel_dma_setup(cp); 154 155 idedma_ctl = 0; 156 bits[0] = bits[1] = 0x7F60; /* assume PIO2/DMA0 */ 157 158 /* Per drive settings */ 159 for (drive = 0; drive < 2; drive++) { 160 drvp = &chp->ch_drive[drive]; 161 /* If no drive, skip */ 162 if (drvp->drive_type == ATA_DRIVET_NONE) 163 continue; 164 /* add timing values, setup DMA if needed */ 165 if ((atac->atac_cap & ATAC_CAP_DMA) && 166 (drvp->drive_flags & ATA_DRIVE_DMA)) { 167 /* use Multiword DMA */ 168 s = splbio(); 169 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 170 splx(s); 171 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 172 bits[drive] = 0xe; /* IOCHRDY,wr/post,rd/prefetch */ 173 } 174 else { 175 /* PIO only */ 176 s = splbio(); 177 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 178 splx(s); 179 bits[drive] = 0x8; /* IOCHRDY */ 180 } 181 bits[drive] |= dmatbl[drvp->DMA_mode] | piotbl[drvp->PIO_mode]; 182 } 183#if 0 184 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 185 (channel == 0) ? 0x40 : 0x44); 186 aprint_normal("wdc%d: IDETIM %08x -> %08x\n", 187 channel, idetim, (bits[1] << 16) | bits[0]); 188#endif 189 idetim = (bits[1] << 16) | bits[0]; 190 pci_conf_write(sc->sc_pc, sc->sc_tag, 191 (channel == 0) ? 0x40 : 0x44, idetim); 192 193 if (idedma_ctl != 0) { 194 /* Add software bits in status register */ 195 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 196 idedma_ctl); 197 } 198} 199