satalink.c revision 1.8
1/* $NetBSD: satalink.c,v 1.8 2003/12/31 12:46:04 martin Exp $ */ 2 3/*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42 43#include <dev/pci/pcivar.h> 44#include <dev/pci/pcidevs.h> 45#include <dev/pci/pciidereg.h> 46#include <dev/pci/pciidevar.h> 47#include <dev/pci/pciide_sii3112_reg.h> 48 49#include <dev/ata/satareg.h> 50#include <dev/ata/atareg.h> 51 52/* 53 * Register map for BA5 register space, indexed by channel. 54 */ 55static const struct { 56 bus_addr_t ba5_IDEDMA_CMD; 57 bus_addr_t ba5_IDEDMA_CTL; 58 bus_addr_t ba5_IDEDMA_TBL; 59 bus_addr_t ba5_IDEDMA_CMD2; 60 bus_addr_t ba5_IDEDMA_CTL2; 61 bus_addr_t ba5_IDE_TF0; 62 bus_addr_t ba5_IDE_TF1; 63 bus_addr_t ba5_IDE_TF2; 64 bus_addr_t ba5_IDE_TF3; 65 bus_addr_t ba5_IDE_TF4; 66 bus_addr_t ba5_IDE_TF5; 67 bus_addr_t ba5_IDE_TF6; 68 bus_addr_t ba5_IDE_TF7; 69 bus_addr_t ba5_IDE_TF8; 70 bus_addr_t ba5_IDE_RAD; 71 bus_addr_t ba5_IDE_TF9; 72 bus_addr_t ba5_IDE_TF10; 73 bus_addr_t ba5_IDE_TF11; 74 bus_addr_t ba5_IDE_TF12; 75 bus_addr_t ba5_IDE_TF13; 76 bus_addr_t ba5_IDE_TF14; 77 bus_addr_t ba5_IDE_TF15; 78 bus_addr_t ba5_IDE_TF16; 79 bus_addr_t ba5_IDE_TF17; 80 bus_addr_t ba5_IDE_TF18; 81 bus_addr_t ba5_IDE_TF19; 82 bus_addr_t ba5_IDE_RABC; 83 bus_addr_t ba5_IDE_CMD_STS; 84 bus_addr_t ba5_IDE_CFG_STS; 85 bus_addr_t ba5_IDE_DTM; 86 bus_addr_t ba5_SControl; 87 bus_addr_t ba5_SStatus; 88 bus_addr_t ba5_SError; 89 bus_addr_t ba5_SActive; /* 3114 */ 90 bus_addr_t ba5_SMisc; 91 bus_addr_t ba5_PHY_CONFIG; 92 bus_addr_t ba5_SIEN; 93 bus_addr_t ba5_SFISCfg; 94} satalink_ba5_regmap[] = { 95 { /* Channel 0 */ 96 .ba5_IDEDMA_CMD = 0x000, 97 .ba5_IDEDMA_CTL = 0x002, 98 .ba5_IDEDMA_TBL = 0x004, 99 .ba5_IDEDMA_CMD2 = 0x010, 100 .ba5_IDEDMA_CTL2 = 0x012, 101 .ba5_IDE_TF0 = 0x080, /* wd_data */ 102 .ba5_IDE_TF1 = 0x081, /* wd_error */ 103 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 104 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 105 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 106 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 107 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 108 .ba5_IDE_TF7 = 0x087, /* wd_command */ 109 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 110 .ba5_IDE_RAD = 0x08c, 111 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 112 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 113 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 114 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 115 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 116 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 117 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 118 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 119 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 120 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 121 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 122 .ba5_IDE_RABC = 0x09c, 123 .ba5_IDE_CMD_STS = 0x0a0, 124 .ba5_IDE_CFG_STS = 0x0a1, 125 .ba5_IDE_DTM = 0x0b4, 126 .ba5_SControl = 0x100, 127 .ba5_SStatus = 0x104, 128 .ba5_SError = 0x108, 129 .ba5_SActive = 0x10c, 130 .ba5_SMisc = 0x140, 131 .ba5_PHY_CONFIG = 0x144, 132 .ba5_SIEN = 0x148, 133 .ba5_SFISCfg = 0x14c, 134 }, 135 { /* Channel 1 */ 136 .ba5_IDEDMA_CMD = 0x008, 137 .ba5_IDEDMA_CTL = 0x00a, 138 .ba5_IDEDMA_TBL = 0x00c, 139 .ba5_IDEDMA_CMD2 = 0x018, 140 .ba5_IDEDMA_CTL2 = 0x01a, 141 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 142 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 143 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 144 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 145 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 146 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 147 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 148 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 149 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 150 .ba5_IDE_RAD = 0x0cc, 151 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 152 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 153 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 154 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 155 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 156 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 157 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 158 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 159 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 160 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 161 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 162 .ba5_IDE_RABC = 0x0dc, 163 .ba5_IDE_CMD_STS = 0x0e0, 164 .ba5_IDE_CFG_STS = 0x0e1, 165 .ba5_IDE_DTM = 0x0f4, 166 .ba5_SControl = 0x180, 167 .ba5_SStatus = 0x184, 168 .ba5_SError = 0x188, 169 .ba5_SActive = 0x18c, 170 .ba5_SMisc = 0x1c0, 171 .ba5_PHY_CONFIG = 0x1c4, 172 .ba5_SIEN = 0x1c8, 173 .ba5_SFISCfg = 0x1cc, 174 }, 175 { /* Channel 2 (3114) */ 176 .ba5_IDEDMA_CMD = 0x200, 177 .ba5_IDEDMA_CTL = 0x202, 178 .ba5_IDEDMA_TBL = 0x204, 179 .ba5_IDEDMA_CMD2 = 0x210, 180 .ba5_IDEDMA_CTL2 = 0x212, 181 .ba5_IDE_TF0 = 0x280, /* wd_data */ 182 .ba5_IDE_TF1 = 0x281, /* wd_error */ 183 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 184 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 185 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 186 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 187 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 188 .ba5_IDE_TF7 = 0x287, /* wd_command */ 189 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 190 .ba5_IDE_RAD = 0x28c, 191 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 192 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 193 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 194 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 195 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 196 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 197 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 198 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 199 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 200 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 201 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 202 .ba5_IDE_RABC = 0x29c, 203 .ba5_IDE_CMD_STS = 0x2a0, 204 .ba5_IDE_CFG_STS = 0x2a1, 205 .ba5_IDE_DTM = 0x2b4, 206 .ba5_SControl = 0x300, 207 .ba5_SStatus = 0x304, 208 .ba5_SError = 0x308, 209 .ba5_SActive = 0x30c, 210 .ba5_SMisc = 0x340, 211 .ba5_PHY_CONFIG = 0x344, 212 .ba5_SIEN = 0x348, 213 .ba5_SFISCfg = 0x34c, 214 }, 215 { /* Channel 3 (3114) */ 216 .ba5_IDEDMA_CMD = 0x208, 217 .ba5_IDEDMA_CTL = 0x20a, 218 .ba5_IDEDMA_TBL = 0x20c, 219 .ba5_IDEDMA_CMD2 = 0x218, 220 .ba5_IDEDMA_CTL2 = 0x21a, 221 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 222 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 223 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 224 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 225 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 226 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 227 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 228 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 229 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 230 .ba5_IDE_RAD = 0x2cc, 231 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 232 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 233 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 234 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 235 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 236 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 237 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 238 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 239 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 240 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 241 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 242 .ba5_IDE_RABC = 0x2dc, 243 .ba5_IDE_CMD_STS = 0x2e0, 244 .ba5_IDE_CFG_STS = 0x2e1, 245 .ba5_IDE_DTM = 0x2f4, 246 .ba5_SControl = 0x380, 247 .ba5_SStatus = 0x384, 248 .ba5_SError = 0x388, 249 .ba5_SActive = 0x38c, 250 .ba5_SMisc = 0x3c0, 251 .ba5_PHY_CONFIG = 0x3c4, 252 .ba5_SIEN = 0x3c8, 253 .ba5_SFISCfg = 0x3cc, 254 }, 255}; 256 257#define ba5_SIS 0x214 /* summary interrupt status */ 258 259/* Interrupt steering bit in BA5[0x200]. */ 260#define IDEDMA_CMD_INT_STEER (1U << 1) 261 262static int satalink_match(struct device *, struct cfdata *, void *); 263static void satalink_attach(struct device *, struct device *, void *); 264 265CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 266 satalink_match, satalink_attach, NULL, NULL); 267 268static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 269static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 270static void sii3112_drv_probe(struct channel_softc*); 271static void sii3112_setup_channel(struct channel_softc*); 272 273static const struct pciide_product_desc pciide_satalink_products[] = { 274 { PCI_PRODUCT_CMDTECH_3112, 275 0, 276 "Silicon Image SATALink 3112", 277 sii3112_chip_map, 278 }, 279 { PCI_PRODUCT_CMDTECH_3114, 280 0, 281 "Silicon Image SATALink 3114", 282 sii3114_chip_map, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289}; 290 291static int 292satalink_match(struct device *parent, struct cfdata *match, void *aux) 293{ 294 struct pci_attach_args *pa = aux; 295 296 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 297 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 298 return (2); 299 } 300 return (0); 301} 302 303static void 304satalink_attach(struct device *parent, struct device *self, void *aux) 305{ 306 struct pci_attach_args *pa = aux; 307 struct pciide_softc *sc = (struct pciide_softc *)self; 308 309 pciide_common_attach(sc, pa, 310 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 311 312} 313 314static __inline uint32_t 315ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 316{ 317 uint32_t rv; 318 int s; 319 320 s = splbio(); 321 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 322 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 323 splx(s); 324 325 return (rv); 326} 327 328static __inline uint32_t 329ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 330{ 331 332 if (__predict_true(sc->sc_ba5_en != 0)) 333 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 334 335 return (ba5_read_4_ind(sc, reg)); 336} 337 338#define BA5_READ_4(sc, chan, reg) \ 339 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 340 341static __inline void 342ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 343{ 344 int s; 345 346 s = splbio(); 347 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 348 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 349 splx(s); 350} 351 352static __inline void 353ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 354{ 355 356 if (__predict_true(sc->sc_ba5_en != 0)) 357 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 358 else 359 ba5_write_4_ind(sc, reg, val); 360} 361 362#define BA5_WRITE_4(sc, chan, reg, val) \ 363 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 364 365static void 366sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 367{ 368 struct pciide_channel *cp; 369 bus_size_t cmdsize, ctlsize; 370 pcireg_t interface, scs_cmd, cfgctl; 371 int channel; 372 373 if (pciide_chipen(sc, pa) == 0) 374 return; 375 376#define SII3112_RESET_BITS \ 377 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 378 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 379 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 380 381 /* 382 * Reset everything and then unblock all of the interrupts. 383 */ 384 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 385 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 386 scs_cmd | SII3112_RESET_BITS); 387 delay(50 * 1000); 388 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 389 scs_cmd & SCS_CMD_BA5_EN); 390 delay(50 * 1000); 391 392 if (scs_cmd & SCS_CMD_BA5_EN) { 393 aprint_verbose("%s: SATALink BA5 register space enabled\n", 394 sc->sc_wdcdev.sc_dev.dv_xname); 395 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 396 PCI_MAPREG_TYPE_MEM| 397 PCI_MAPREG_MEM_TYPE_32BIT, 0, 398 &sc->sc_ba5_st, &sc->sc_ba5_sh, 399 NULL, NULL) != 0) 400 aprint_error("%s: unable to map SATALink BA5 " 401 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 402 else 403 sc->sc_ba5_en = 1; 404 } else { 405 aprint_verbose("%s: SATALink BA5 register space disabled\n", 406 sc->sc_wdcdev.sc_dev.dv_xname); 407 408 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 409 SII3112_PCI_CFGCTL); 410 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 411 cfgctl | CFGCTL_BA5INDEN); 412 } 413 414 aprint_normal("%s: bus-master DMA support present", 415 sc->sc_wdcdev.sc_dev.dv_xname); 416 pciide_mapreg_dma(sc, pa); 417 aprint_normal("\n"); 418 419 /* 420 * Rev. <= 0x01 of the 3112 have a bug that can cause data 421 * corruption if DMA transfers cross an 8K boundary. This is 422 * apparently hard to tickle, but we'll go ahead and play it 423 * safe. 424 */ 425 if (PCI_REVISION(pa->pa_class) <= 0x01) { 426 sc->sc_dma_maxsegsz = 8192; 427 sc->sc_dma_boundary = 8192; 428 } 429 430 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 431 WDC_CAPABILITY_MODE; 432 sc->sc_wdcdev.PIO_cap = 4; 433 if (sc->sc_dma_ok) { 434 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 435 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 436 sc->sc_wdcdev.irqack = pciide_irqack; 437 sc->sc_wdcdev.DMA_cap = 2; 438 sc->sc_wdcdev.UDMA_cap = 6; 439 } 440 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 441 442 /* We can use SControl and SStatus to probe for drives. */ 443 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 444 445 sc->sc_wdcdev.channels = sc->wdc_chanarray; 446 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 447 448 /* 449 * The 3112 either identifies itself as a RAID storage device 450 * or a Misc storage device. Fake up the interface bits for 451 * what our driver expects. 452 */ 453 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 454 interface = PCI_INTERFACE(pa->pa_class); 455 } else { 456 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 457 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 458 } 459 460 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 461 cp = &sc->pciide_channels[channel]; 462 if (pciide_chansetup(sc, channel, interface) == 0) 463 continue; 464 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 465 pciide_pci_intr); 466 } 467} 468 469static void 470sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 471{ 472 struct pciide_channel *pc; 473 int chan, reg; 474 bus_size_t size; 475 476 sc->sc_wdcdev.dma_arg = sc; 477 sc->sc_wdcdev.dma_init = pciide_dma_init; 478 sc->sc_wdcdev.dma_start = pciide_dma_start; 479 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 480 481 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 482 PCIIDE_OPTIONS_NODMA) { 483 aprint_normal( 484 ", but unused (forced off by config file)"); 485 sc->sc_dma_ok = 0; 486 return; 487 } 488 489 /* 490 * Slice off a subregion of BA5 for each of the channel's DMA 491 * registers. 492 */ 493 494 sc->sc_dma_iot = sc->sc_ba5_st; 495 for (chan = 0; chan < 4; chan++) { 496 pc = &sc->pciide_channels[chan]; 497 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 498 size = 4; 499 if (size > (IDEDMA_SCH_OFFSET - reg)) 500 size = IDEDMA_SCH_OFFSET - reg; 501 if (bus_space_subregion(sc->sc_ba5_st, 502 sc->sc_ba5_sh, 503 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 504 size, &pc->dma_iohs[reg]) != 0) { 505 sc->sc_dma_ok = 0; 506 aprint_normal(", but can't subregion offset " 507 "%lu size %lu", 508 (u_long) satalink_ba5_regmap[ 509 chan].ba5_IDEDMA_CMD + reg, 510 (u_long) size); 511 return; 512 } 513 } 514 } 515 516 /* DMA registers all set up! */ 517 sc->sc_dmat = pa->pa_dmat; 518 sc->sc_dma_ok = 1; 519} 520 521static int 522sii3114_chansetup(struct pciide_softc *sc, int channel) 523{ 524 static const char *channel_names[] = { 525 "port 0", 526 "port 1", 527 "port 2", 528 "port 3", 529 }; 530 struct pciide_channel *cp = &sc->pciide_channels[channel]; 531 532 sc->wdc_chanarray[channel] = &cp->wdc_channel; 533 534 /* 535 * We must always keep the Interrupt Steering bit set in channel 2's 536 * IDEDMA_CMD register. 537 */ 538 if (channel == 2) 539 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 540 541 cp->name = channel_names[channel]; 542 cp->wdc_channel.channel = channel; 543 cp->wdc_channel.wdc = &sc->sc_wdcdev; 544 cp->wdc_channel.ch_queue = 545 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 546 if (cp->wdc_channel.ch_queue == NULL) { 547 aprint_error("%s %s channel: " 548 "can't allocate memory for command queue", 549 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 550 return (0); 551 } 552 return (1); 553} 554 555static void 556sii3114_mapchan(struct pciide_channel *cp) 557{ 558 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 559 struct channel_softc *wdc_cp = &cp->wdc_channel; 560 int i; 561 562 cp->compat = 0; 563 cp->ih = sc->sc_pci_ih; 564 565 wdc_cp->cmd_iot = sc->sc_ba5_st; 566 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 567 satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF0, 568 9, &wdc_cp->cmd_baseioh) != 0) { 569 aprint_error("%s: couldn't subregion %s cmd base\n", 570 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 571 goto bad; 572 } 573 574 wdc_cp->ctl_iot = sc->sc_ba5_st; 575 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 576 satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF8, 577 1, &cp->ctl_baseioh) != 0) { 578 aprint_error("%s: couldn't subregion %s ctl base\n", 579 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 580 goto bad; 581 } 582 wdc_cp->ctl_ioh = cp->ctl_baseioh; 583 584 for (i = 0; i < WDC_NREG; i++) { 585 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 586 i, i == 0 ? 4 : 1, 587 &wdc_cp->cmd_iohs[i]) != 0) { 588 aprint_error("%s: couldn't subregion %s channel " 589 "cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 goto bad; 592 } 593 } 594 wdc_cp->data32iot = wdc_cp->cmd_iot; 595 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 596 wdcattach(wdc_cp); 597 return; 598 599 bad: 600 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 601} 602 603static void 604sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 605{ 606 struct pciide_channel *cp; 607 pcireg_t scs_cmd; 608 pci_intr_handle_t intrhandle; 609 const char *intrstr; 610 int channel; 611 612 if (pciide_chipen(sc, pa) == 0) 613 return; 614 615#define SII3114_RESET_BITS \ 616 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 617 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 618 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 619 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 620 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 621 622 /* 623 * Reset everything and then unblock all of the interrupts. 624 */ 625 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 626 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 627 scs_cmd | SII3114_RESET_BITS); 628 delay(50 * 1000); 629 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 630 scs_cmd & SCS_CMD_M66EN); 631 delay(50 * 1000); 632 633 /* 634 * On the 3114, the BA5 register space is always enabled. In 635 * order to use the 3114 in any sane way, we must use this BA5 636 * register space, and so we consider it an error if we cannot 637 * map it. 638 * 639 * As a consequence of using BA5, our register mapping is different 640 * from a normal PCI IDE controller's, and so we are unable to use 641 * most of the common PCI IDE register mapping functions. 642 */ 643 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 644 PCI_MAPREG_TYPE_MEM| 645 PCI_MAPREG_MEM_TYPE_32BIT, 0, 646 &sc->sc_ba5_st, &sc->sc_ba5_sh, 647 NULL, NULL) != 0) { 648 aprint_error("%s: unable to map SATALink BA5 " 649 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 650 return; 651 } 652 sc->sc_ba5_en = 1; 653 654 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_dev.dv_xname, 655 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 656 657 /* 658 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 659 * channel 2. This is required at all times for proper operation 660 * when using the BA5 register space (otherwise interrupts from 661 * all 4 channels won't work). 662 */ 663 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 664 665 aprint_normal("%s: bus-master DMA support present", 666 sc->sc_wdcdev.sc_dev.dv_xname); 667 sii3114_mapreg_dma(sc, pa); 668 aprint_normal("\n"); 669 670 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 671 WDC_CAPABILITY_MODE; 672 sc->sc_wdcdev.PIO_cap = 4; 673 if (sc->sc_dma_ok) { 674 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 675 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 676 sc->sc_wdcdev.irqack = pciide_irqack; 677 sc->sc_wdcdev.DMA_cap = 2; 678 sc->sc_wdcdev.UDMA_cap = 6; 679 } 680 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 681 682 /* We can use SControl and SStatus to probe for drives. */ 683 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 684 685 sc->sc_wdcdev.channels = sc->wdc_chanarray; 686 sc->sc_wdcdev.nchannels = 4; 687 688 /* Map and establish the interrupt handler. */ 689 if (pci_intr_map(pa, &intrhandle) != 0) { 690 aprint_error("%s: couldn't map native-PCI interrupt\n", 691 sc->sc_wdcdev.sc_dev.dv_xname); 692 return; 693 } 694 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 695 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 696 /* XXX */ 697 pciide_pci_intr, sc); 698 if (sc->sc_pci_ih != NULL) { 699 aprint_normal("%s: using %s for native-PCI interrupt\n", 700 sc->sc_wdcdev.sc_dev.dv_xname, 701 intrstr ? intrstr : "unknown interrupt"); 702 } else { 703 aprint_error("%s: couldn't establish native-PCI interrupt", 704 sc->sc_wdcdev.sc_dev.dv_xname); 705 if (intrstr != NULL) 706 aprint_normal(" at %s", intrstr); 707 aprint_normal("\n"); 708 return; 709 } 710 711 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 712 cp = &sc->pciide_channels[channel]; 713 if (sii3114_chansetup(sc, channel) == 0) 714 continue; 715 sii3114_mapchan(cp); 716 } 717} 718 719static const char *sata_speed[] = { 720 "no negotiated speed", 721 "1.5Gb/s", 722 "<unknown 2>", 723 "<unknown 3>", 724 "<unknown 4>", 725 "<unknown 5>", 726 "<unknown 6>", 727 "<unknown 7>", 728 "<unknown 8>", 729 "<unknown 9>", 730 "<unknown 10>", 731 "<unknown 11>", 732 "<unknown 12>", 733 "<unknown 13>", 734 "<unknown 14>", 735 "<unknown 15>", 736}; 737 738static void 739sii3112_drv_probe(struct channel_softc *chp) 740{ 741 struct pciide_channel *cp = (struct pciide_channel *)chp; 742 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 743 uint32_t scontrol, sstatus; 744 uint8_t scnt, sn, cl, ch; 745 746 /* 747 * The 3112 is a 2-port part, and only has one drive per channel 748 * (each port emulates a master drive). 749 * 750 * The 3114 is similar, but has 4 channels. 751 */ 752 753 /* 754 * Request communication initialization sequence, any speed. 755 * Performing this is the equivalent of an ATA Reset. 756 */ 757 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 758 759 /* 760 * XXX We don't yet support SATA power management; disable all 761 * power management state transitions. 762 */ 763 scontrol |= SControl_IPM_NONE; 764 765 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 766 delay(50 * 1000); 767 scontrol &= ~SControl_DET_INIT; 768 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 769 delay(50 * 1000); 770 771 sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); 772#if 0 773 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 774 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 775 BA5_READ_4(sc, chp->channel, ba5_SControl)); 776#endif 777 switch (sstatus & SStatus_DET_mask) { 778 case SStatus_DET_NODEV: 779 /* No device; be silent. */ 780 break; 781 782 case SStatus_DET_DEV_NE: 783 aprint_error("%s: port %d: device connected, but " 784 "communication not established\n", 785 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 786 break; 787 788 case SStatus_DET_OFFLINE: 789 aprint_error("%s: port %d: PHY offline\n", 790 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 791 break; 792 793 case SStatus_DET_DEV: 794 /* 795 * XXX ATAPI detection doesn't currently work. Don't 796 * XXX know why. But, it's not like the standard method 797 * XXX can detect an ATAPI device connected via a SATA/PATA 798 * XXX bridge, so at least this is no worse. --thorpej 799 */ 800 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 801 WDSD_IBM | (0 << 4)); 802 delay(10); /* 400ns delay */ 803 /* Save register contents. */ 804 scnt = bus_space_read_1(chp->cmd_iot, 805 chp->cmd_iohs[wd_seccnt], 0); 806 sn = bus_space_read_1(chp->cmd_iot, 807 chp->cmd_iohs[wd_sector], 0); 808 cl = bus_space_read_1(chp->cmd_iot, 809 chp->cmd_iohs[wd_cyl_lo], 0); 810 ch = bus_space_read_1(chp->cmd_iot, 811 chp->cmd_iohs[wd_cyl_hi], 0); 812#if 0 813 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 814 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 815 scnt, sn, cl, ch); 816#endif 817 /* 818 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 819 * cases we get wrong values here, so ignore it. 820 */ 821 if (cl == 0x14 && ch == 0xeb) 822 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 823 else 824 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 825 826 aprint_normal("%s: port %d: device present, speed: %s\n", 827 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 828 sata_speed[(sstatus & SStatus_SPD_mask) >> 829 SStatus_SPD_shift]); 830 break; 831 832 default: 833 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 834 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 835 } 836} 837 838static void 839sii3112_setup_channel(struct channel_softc *chp) 840{ 841 struct ata_drive_datas *drvp; 842 int drive; 843 u_int32_t idedma_ctl, dtm; 844 struct pciide_channel *cp = (struct pciide_channel*)chp; 845 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 846 847 /* setup DMA if needed */ 848 pciide_channel_dma_setup(cp); 849 850 idedma_ctl = 0; 851 dtm = 0; 852 853 for (drive = 0; drive < 2; drive++) { 854 drvp = &chp->ch_drive[drive]; 855 /* If no drive, skip */ 856 if ((drvp->drive_flags & DRIVE) == 0) 857 continue; 858 if (drvp->drive_flags & DRIVE_UDMA) { 859 /* use Ultra/DMA */ 860 drvp->drive_flags &= ~DRIVE_DMA; 861 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 862 dtm |= DTM_IDEx_DMA; 863 } else if (drvp->drive_flags & DRIVE_DMA) { 864 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 865 dtm |= DTM_IDEx_DMA; 866 } else { 867 dtm |= DTM_IDEx_PIO; 868 } 869 } 870 871 /* 872 * Nothing to do to setup modes; it is meaningless in S-ATA 873 * (but many S-ATA drives still want to get the SET_FEATURE 874 * command). 875 */ 876 if (idedma_ctl != 0) { 877 /* Add software bits in status register */ 878 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 879 idedma_ctl); 880 } 881 BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm); 882} 883