nside.c revision 1.5
1/* $NetBSD: nside.c,v 1.5 2012/07/24 14:04:31 jakllsch Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.5 2012/07/24 14:04:31 jakllsch Exp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32 33#include <dev/pci/pcivar.h> 34#include <dev/pci/pcidevs.h> 35#include <dev/pci/pciidereg.h> 36#include <dev/pci/pciidevar.h> 37#include <dev/pci/pciide_natsemi_reg.h> 38 39static void natsemi_chip_map(struct pciide_softc *, 40 const struct pci_attach_args *); 41static void natsemi_setup_channel(struct ata_channel *); 42static int natsemi_pci_intr(void *); 43static void natsemi_irqack(struct ata_channel *); 44 45static int nside_match(device_t, cfdata_t, void *); 46static void nside_attach(device_t, device_t, void *); 47 48struct nside_softc { 49 struct pciide_softc pciide_sc; 50 struct pci_attach_args pcib_pa; 51}; 52 53CFATTACH_DECL_NEW(nside, sizeof(struct nside_softc), 54 nside_match, nside_attach, NULL, NULL); 55 56static const struct pciide_product_desc pciide_natsemi_products[] = { 57 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 58 0, 59 "National Semiconductor PC87415 IDE Controller", 60 natsemi_chip_map, 61 }, 62 { 0, 63 0, 64 NULL, 65 NULL 66 } 67}; 68 69static int 70nside_match(device_t parent, cfdata_t match, void *aux) 71{ 72 struct pci_attach_args *pa = aux; 73 74 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 75 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 76 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 77 if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products)) 78 return 2; 79 } 80 return 0; 81} 82 83static void 84nside_attach(device_t parent, device_t self, void *aux) 85{ 86 struct pci_attach_args *pa = aux; 87 struct pciide_softc *sc = device_private(self); 88 89 sc->sc_wdcdev.sc_atac.atac_dev = self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_natsemi_products)); 93} 94 95static void 96natsemi_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 97{ 98 struct pciide_channel *cp; 99 int channel; 100 pcireg_t interface, ctl; 101 102 if (pciide_chipen(sc, pa) == 0) 103 return; 104 105 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 106 "bus-master DMA support present"); 107 pciide_mapreg_dma(sc, pa); 108 aprint_verbose("\n"); 109 110 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 111 112 if (sc->sc_dma_ok) { 113 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 114 sc->sc_wdcdev.irqack = natsemi_irqack; 115 } 116 117 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 118 119 /* 120 * Mask off interrupts from both channels, appropriate channel(s) 121 * will be unmasked later. 122 */ 123 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 124 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 125 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 126 127 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 128 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 129 sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel; 130 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 131 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 132 sc->sc_wdcdev.wdc_maxdrives = 2; 133 134 interface = PCI_INTERFACE(pa->pa_class); 135 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 136 137 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 138 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 139 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 140 ctl &= ~NATSEMI_CTRL1_INTAMASK; 141 else 142 ctl |= NATSEMI_CTRL1_INTAMASK; 143 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 144 145 wdc_allocate_regs(&sc->sc_wdcdev); 146 147 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) { 148 cp = &sc->pciide_channels[channel]; 149 if (pciide_chansetup(sc, channel, interface) == 0) 150 continue; 151 152 pciide_mapchan(pa, cp, interface, natsemi_pci_intr); 153 154 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 155 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 156 ~(NATSEMI_CHMASK(channel))); 157 } 158} 159 160void 161natsemi_setup_channel(struct ata_channel *chp) 162{ 163 struct ata_drive_datas *drvp; 164 int drive, ndrives = 0; 165 uint32_t idedma_ctl = 0; 166 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 167 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 168 uint8_t tim; 169 170 /* setup DMA if needed */ 171 pciide_channel_dma_setup(cp); 172 173 for (drive = 0; drive < 2; drive++) { 174 drvp = &chp->ch_drive[drive]; 175 /* If no drive, skip */ 176 if (drvp->drive_type == DRIVET_NONE) 177 continue; 178 179 ndrives++; 180 /* add timing values, setup DMA if needed */ 181 if ((drvp->drive_flags & DRIVE_DMA) == 0) { 182 tim = natsemi_pio_pulse[drvp->PIO_mode] | 183 (natsemi_pio_recover[drvp->PIO_mode] << 4); 184 } else { 185 /* 186 * use Multiword DMA 187 * Timings will be used for both PIO and DMA, 188 * so adjust DMA mode if needed 189 */ 190 if (drvp->PIO_mode >= 3 && 191 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 192 drvp->DMA_mode = drvp->PIO_mode - 2; 193 } 194 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 195 tim = natsemi_dma_pulse[drvp->DMA_mode] | 196 (natsemi_dma_recover[drvp->DMA_mode] << 4); 197 198 } 199 200 pciide_pci_write(sc->sc_pc, sc->sc_tag, 201 NATSEMI_RTREG(chp->ch_channel, drive), tim); 202 pciide_pci_write(sc->sc_pc, sc->sc_tag, 203 NATSEMI_WTREG(chp->ch_channel, drive), tim); 204 } 205 206 if (idedma_ctl != 0) { 207 /* Add software bits in status register */ 208 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 209 idedma_ctl); 210 211 } 212 /* Go ahead and ack interrupts generated during probe. */ 213 natsemi_irqack(chp); 214} 215 216void 217natsemi_irqack(struct ata_channel *chp) 218{ 219 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 220 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 221 uint8_t clr; 222 223 /* Errata: The "clear" bits are in the wrong register *sigh* */ 224 clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0); 225 clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) & 226 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 227 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr); 228} 229 230int 231natsemi_pci_intr(void *arg) 232{ 233 struct pciide_softc *sc = arg; 234 struct pciide_channel *cp; 235 struct ata_channel *wdc_cp; 236 int i, rv, crv; 237 uint8_t msk; 238 239 rv = 0; 240 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 241 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 242 cp = &sc->pciide_channels[i]; 243 wdc_cp = &cp->ata_channel; 244 245 /* If a compat channel skip. */ 246 if (cp->compat) 247 continue; 248 249 /* If this channel is masked, skip it. */ 250 if (msk & NATSEMI_CHMASK(i)) 251 continue; 252 253 crv = wdcintr(wdc_cp); 254 if (crv == 0) 255 ; /* leave alone */ 256 else if (crv == 1) 257 rv = 1; /* claim the intr */ 258 else if (rv == 0) /* crv should be -1 in this case */ 259 rv = crv; /* if we've done no better, take it */ 260 } 261 return (rv); 262} 263