nside.c revision 1.10
1/* $NetBSD: nside.c,v 1.10 2017/01/04 15:49:28 christos Exp $ */ 2 3/* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__KERNEL_RCSID(0, "$NetBSD: nside.c,v 1.10 2017/01/04 15:49:28 christos Exp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32 33#include <dev/pci/pcivar.h> 34#include <dev/pci/pcidevs.h> 35#include <dev/pci/pciidereg.h> 36#include <dev/pci/pciidevar.h> 37#include <dev/pci/pciide_natsemi_reg.h> 38 39static void natsemi_chip_map(struct pciide_softc *, 40 const struct pci_attach_args *); 41static void natsemi_setup_channel(struct ata_channel *); 42static int natsemi_pci_intr(void *); 43static void natsemi_irqack(struct ata_channel *); 44 45static int nside_match(device_t, cfdata_t, void *); 46static void nside_attach(device_t, device_t, void *); 47 48CFATTACH_DECL_NEW(nside, sizeof(struct pciide_softc), 49 nside_match, nside_attach, pciide_detach, NULL); 50 51static const struct pciide_product_desc pciide_natsemi_products[] = { 52 { PCI_PRODUCT_NS_PC87415, /* National Semi PC87415 IDE */ 53 0, 54 "National Semiconductor PC87415 IDE Controller", 55 natsemi_chip_map, 56 }, 57 { 0, 58 0, 59 NULL, 60 NULL 61 } 62}; 63 64static int 65nside_match(device_t parent, cfdata_t match, void *aux) 66{ 67 struct pci_attach_args *pa = aux; 68 69 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 70 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 71 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 72 if (pciide_lookup_product(pa->pa_id, pciide_natsemi_products)) 73 return 2; 74 } 75 return 0; 76} 77 78static void 79nside_attach(device_t parent, device_t self, void *aux) 80{ 81 struct pci_attach_args *pa = aux; 82 struct pciide_softc *sc = device_private(self); 83 84 sc->sc_wdcdev.sc_atac.atac_dev = self; 85 86 pciide_common_attach(sc, pa, 87 pciide_lookup_product(pa->pa_id, pciide_natsemi_products)); 88} 89 90static void 91natsemi_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 92{ 93 struct pciide_channel *cp; 94 int channel; 95 pcireg_t interface, ctl; 96 97 if (pciide_chipen(sc, pa) == 0) 98 return; 99 100 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 101 "bus-master DMA support present"); 102 pciide_mapreg_dma(sc, pa); 103 aprint_verbose("\n"); 104 105 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 106 107 if (sc->sc_dma_ok) { 108 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 109 sc->sc_wdcdev.irqack = natsemi_irqack; 110 } 111 112 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CCBT, 0xb7); 113 114 /* 115 * Mask off interrupts from both channels, appropriate channel(s) 116 * will be unmasked later. 117 */ 118 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 119 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) | 120 NATSEMI_CHMASK(0) | NATSEMI_CHMASK(1)); 121 122 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 123 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 124 sc->sc_wdcdev.sc_atac.atac_set_modes = natsemi_setup_channel; 125 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 126 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 127 sc->sc_wdcdev.wdc_maxdrives = 2; 128 129 interface = PCI_INTERFACE(pa->pa_class); 130 interface &= ~PCIIDE_CHANSTATUS_EN; /* Reserved on PC87415 */ 131 132 /* If we're in PCIIDE mode, unmask INTA, otherwise mask it. */ 133 ctl = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1); 134 if (interface & (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))) 135 ctl &= ~NATSEMI_CTRL1_INTAMASK; 136 else 137 ctl |= NATSEMI_CTRL1_INTAMASK; 138 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL1, ctl); 139 140 wdc_allocate_regs(&sc->sc_wdcdev); 141 142 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) { 143 cp = &sc->pciide_channels[channel]; 144 if (pciide_chansetup(sc, channel, interface) == 0) 145 continue; 146 147 pciide_mapchan(pa, cp, interface, natsemi_pci_intr); 148 149 pciide_pci_write(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2, 150 pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2) & 151 ~(NATSEMI_CHMASK(channel))); 152 } 153} 154 155void 156natsemi_setup_channel(struct ata_channel *chp) 157{ 158 struct ata_drive_datas *drvp; 159 int drive; 160 uint32_t idedma_ctl = 0; 161 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 162 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 163 uint8_t tim; 164 165 /* setup DMA if needed */ 166 pciide_channel_dma_setup(cp); 167 168 for (drive = 0; drive < 2; drive++) { 169 drvp = &chp->ch_drive[drive]; 170 /* If no drive, skip */ 171 if (drvp->drive_type == ATA_DRIVET_NONE) 172 continue; 173 174 /* add timing values, setup DMA if needed */ 175 if ((drvp->drive_flags & ATA_DRIVE_DMA) == 0) { 176 tim = natsemi_pio_pulse[drvp->PIO_mode] | 177 (natsemi_pio_recover[drvp->PIO_mode] << 4); 178 } else { 179 /* 180 * use Multiword DMA 181 * Timings will be used for both PIO and DMA, 182 * so adjust DMA mode if needed 183 */ 184 if (drvp->PIO_mode >= 3 && 185 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 186 drvp->DMA_mode = drvp->PIO_mode - 2; 187 } 188 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 189 tim = natsemi_dma_pulse[drvp->DMA_mode] | 190 (natsemi_dma_recover[drvp->DMA_mode] << 4); 191 192 } 193 194 pciide_pci_write(sc->sc_pc, sc->sc_tag, 195 NATSEMI_RTREG(chp->ch_channel, drive), tim); 196 pciide_pci_write(sc->sc_pc, sc->sc_tag, 197 NATSEMI_WTREG(chp->ch_channel, drive), tim); 198 } 199 200 if (idedma_ctl != 0) { 201 /* Add software bits in status register */ 202 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 203 idedma_ctl); 204 205 } 206 /* Go ahead and ack interrupts generated during probe. */ 207 natsemi_irqack(chp); 208} 209 210void 211natsemi_irqack(struct ata_channel *chp) 212{ 213 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 214 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 215 uint8_t clr; 216 217 /* Errata: The "clear" bits are in the wrong register *sigh* */ 218 clr = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0); 219 clr |= bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0) & 220 (IDEDMA_CTL_ERR | IDEDMA_CTL_INTR); 221 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, clr); 222} 223 224int 225natsemi_pci_intr(void *arg) 226{ 227 struct pciide_softc *sc = arg; 228 struct pciide_channel *cp; 229 struct ata_channel *wdc_cp; 230 int i, rv, crv; 231 uint8_t msk; 232 233 rv = 0; 234 msk = pciide_pci_read(sc->sc_pc, sc->sc_tag, NATSEMI_CTRL2); 235 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 236 cp = &sc->pciide_channels[i]; 237 wdc_cp = &cp->ata_channel; 238 239 /* If a compat channel skip. */ 240 if (cp->compat) 241 continue; 242 243 /* If this channel is masked, skip it. */ 244 if (msk & NATSEMI_CHMASK(i)) 245 continue; 246 247 crv = wdcintr(wdc_cp); 248 if (crv == 0) 249 ; /* leave alone */ 250 else if (crv == 1) 251 rv = 1; /* claim the intr */ 252 else if (rv == 0) /* crv should be -1 in this case */ 253 rv = crv; /* if we've done no better, take it */ 254 } 255 return (rv); 256} 257