jmide.c revision 1.6 
1/*	$NetBSD: jmide.c,v 1.6 2008/06/05 18:22:02 bouyer Exp $	*/
2
3/*
4 * Copyright (c) 2007 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.6 2008/06/05 18:22:02 bouyer Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38
39#include <dev/pci/pcivar.h>
40#include <dev/pci/pcidevs.h>
41#include <dev/pci/pciidereg.h>
42#include <dev/pci/pciidevar.h>
43
44#include <dev/pci/jmide_reg.h>
45
46#include <dev/ic/ahcisatavar.h>
47
48#include "jmide.h"
49
50static const struct jmide_product *jmide_lookup(pcireg_t);
51
52static int  jmide_match(device_t, cfdata_t, void *);
53static void jmide_attach(device_t, device_t, void *);
54static int  jmide_intr(void *);
55
56static void jmpata_chip_map(struct pciide_softc*, struct pci_attach_args*);
57static void jmpata_setup_channel(struct ata_channel*);
58
59static int  jmahci_print(void *, const char *);
60
61struct jmide_product {
62	u_int32_t jm_product;
63	int jm_npata;
64	int jm_nsata;
65};
66
67static const struct jmide_product jm_products[] =  {
68	{ PCI_PRODUCT_JMICRON_JMB360,
69	  0,
70	  1
71	},
72	{ PCI_PRODUCT_JMICRON_JMB361,
73	  1,
74	  1
75	},
76	{ PCI_PRODUCT_JMICRON_JMB363,
77	  1,
78	  2
79	},
80	{ PCI_PRODUCT_JMICRON_JMB365,
81	  2,
82	  1
83	},
84	{ PCI_PRODUCT_JMICRON_JMB366,
85	  2,
86	  2
87	},
88	{ PCI_PRODUCT_JMICRON_JMB368,
89	  1,
90	  0
91	},
92	{ 0,
93	  0,
94	  0
95	}
96};
97
98typedef enum {
99	TYPE_INVALID = 0,
100	TYPE_PATA,
101	TYPE_SATA,
102	TYPE_NONE
103} jmchan_t;
104
105struct jmide_softc {
106	struct pciide_softc sc_pciide;
107	device_t sc_ahci;
108	int sc_npata;
109	int sc_nsata;
110	jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS];
111	int sc_chan_swap;
112};
113
114struct jmahci_attach_args {
115	struct pci_attach_args *jma_pa;
116	bus_space_tag_t jma_ahcit;
117	bus_space_handle_t jma_ahcih;
118};
119
120#define JM_NAME(sc) (device_xname(sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev))
121
122CFATTACH_DECL_NEW(jmide, sizeof(struct jmide_softc),
123    jmide_match, jmide_attach, NULL, NULL);
124
125static const struct jmide_product *
126jmide_lookup(pcireg_t id) {
127	const struct jmide_product *jp;
128
129	for (jp = jm_products; jp->jm_product != 0; jp++) {
130		if (jp->jm_product == PCI_PRODUCT(id))
131			return jp;
132	}
133	return NULL;
134}
135
136static int
137jmide_match(device_t parent, cfdata_t match, void *aux)
138{
139	struct pci_attach_args *pa = aux;
140
141	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) {
142		if (jmide_lookup(pa->pa_id))
143			return (4); /* highter than ahcisata */
144	}
145	return (0);
146}
147
148static void
149jmide_attach(device_t parent, device_t self, void *aux)
150{
151	struct pci_attach_args *pa = aux;
152	struct jmide_softc *sc = device_private(self);
153	const struct jmide_product *jp;
154        char devinfo[256];
155	const char *intrstr;
156        pci_intr_handle_t intrhandle;
157	u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag,
158	    PCI_JM_CONTROL0);
159	u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
160	    PCI_JM_CONTROL1);
161	struct pciide_product_desc *pp;
162	int ahci_used = 0;
163
164	sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev = self;
165
166	jp = jmide_lookup(pa->pa_id);
167	if (jp == NULL) {
168		printf("jmide_attach: WTF?\n");
169		return;
170	}
171	sc->sc_npata = jp->jm_npata;
172	sc->sc_nsata = jp->jm_nsata;
173
174	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
175        aprint_naive(": JMICRON PATA/SATA disk controller\n");
176        aprint_normal(": %s\n", devinfo);
177
178	aprint_normal("%s: ", JM_NAME(sc));
179	if (sc->sc_npata)
180		aprint_normal("%d PATA port%s", sc->sc_npata,
181		    (sc->sc_npata > 1) ? "s" : "");
182	if (sc->sc_nsata)
183		aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "",
184		    sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : "");
185	aprint_normal("\n");
186
187	if (pci_intr_map(pa, &intrhandle) != 0) {
188                aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc));
189                return;
190        }
191        intrstr = pci_intr_string(pa->pa_pc, intrhandle);
192        sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle,
193	    IPL_BIO, jmide_intr, sc);
194        if (sc->sc_pciide.sc_pci_ih == NULL) {
195                aprint_error("%s: couldn't establish interrupt", JM_NAME(sc));
196                return;
197        }
198        aprint_normal("%s: interrupting at %s\n", JM_NAME(sc),
199            intrstr ? intrstr : "unknown interrupt");
200
201	if (pcictrl0 & JM_CONTROL0_AHCI_EN) {
202		bus_size_t size;
203		struct jmahci_attach_args jma;
204		u_int32_t saved_pcictrl0;
205		/*
206		 * ahci controller enabled; disable sata on pciide and
207		 * enable on ahci
208		 */
209		saved_pcictrl0 = pcictrl0;
210		pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI;
211		pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE);
212		pci_conf_write(pa->pa_pc, pa->pa_tag,
213		    PCI_JM_CONTROL0, pcictrl0);
214		/* attach ahci controller if on the right function */
215		if ((pa->pa_function == 0 &&
216		      (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) ||
217	    	    (pa->pa_function == 1 &&
218		      (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) {
219			jma.jma_pa = pa;
220			/* map registers */
221			if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
222			    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
223			    &jma.jma_ahcit, &jma.jma_ahcih, NULL, &size) != 0) {
224				aprint_error("%s: can't map ahci registers\n",
225				    JM_NAME(sc));
226			} else {
227				sc->sc_ahci = config_found_ia(
228				    sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev,
229				    "jmide_hl", &jma, jmahci_print);
230			}
231			/*
232			 * if we couldn't attach an ahci, try to fall back
233			 * to pciide. Note that this will not work if IDE
234			 * is on function 0 and AHCI on function 1.
235			 */
236			if (sc->sc_ahci == NULL) {
237				pcictrl0 = saved_pcictrl0 &
238				    ~(JM_CONTROL0_SATA0_AHCI |
239				      JM_CONTROL0_SATA1_AHCI |
240				      JM_CONTROL0_AHCI_EN);
241				pcictrl0 |= JM_CONTROL0_SATA1_IDE |
242					JM_CONTROL0_SATA0_IDE;
243				pci_conf_write(pa->pa_pc, pa->pa_tag,
244				    PCI_JM_CONTROL0, pcictrl0);
245			} else
246				ahci_used = 1;
247		}
248	}
249	sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0);
250	/* compute the type of internal primary channel */
251	if (pcictrl1 & JM_CONTROL1_PATA1_PRI) {
252		if (sc->sc_npata > 1)
253			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA;
254		else
255			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
256	} else if (ahci_used == 0 && sc->sc_nsata > 0)
257		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA;
258	else
259		sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
260	/* compute the type of internal secondary channel */
261	if (sc->sc_nsata > 1 && ahci_used == 0 &&
262	    (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0) {
263		sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA;
264	} else {
265		/* only a drive if first PATA enabled */
266		if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN)
267		    && (pcictrl0 &
268		    (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC)))
269			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA;
270		else
271			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
272	}
273
274	if (sc->sc_chan_type[0] == TYPE_NONE &&
275	    sc->sc_chan_type[1] == TYPE_NONE)
276		return;
277	if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1))
278		return;
279	if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0)
280		return;
281	pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT);
282	if (pp == NULL) {
283		aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc));
284		return;
285	}
286	aprint_normal("%s: PCI IDE interface used", JM_NAME(sc));
287	pp->ide_product = 0;
288	pp->ide_flags = 0;
289	pp->ide_name = NULL;
290	pp->chip_map = jmpata_chip_map;
291	pciide_common_attach(&sc->sc_pciide, pa, pp);
292
293}
294
295static int
296jmide_intr(void *arg)
297{
298	struct jmide_softc *sc = arg;
299	int ret = 0;
300
301#ifdef NJMAHCI
302	if (sc->sc_ahci)
303		ret |= ahci_intr(device_private(sc->sc_ahci));
304#endif
305	if (sc->sc_npata)
306		ret |= pciide_pci_intr(&sc->sc_pciide);
307	return ret;
308}
309
310static void
311jmpata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
312{
313	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
314	int channel;
315	pcireg_t interface;
316	bus_size_t cmdsize, ctlsize;
317	struct pciide_channel *cp;
318
319	if (pciide_chipen(sc, pa) == 0)
320		return;
321	aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
322	pciide_mapreg_dma(sc, pa);
323	aprint_verbose("\n");
324	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
325	if (sc->sc_dma_ok) {
326		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
327		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
328	}
329	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
330	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
331	sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
332	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
333	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
334	wdc_allocate_regs(&sc->sc_wdcdev);
335	/*
336         * can't rely on the PCI_CLASS_REG content if the chip was in raid
337         * mode. We have to fake interface
338         */
339	interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
340	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
341	    channel++) {
342		cp = &sc->pciide_channels[channel];
343		if (pciide_chansetup(sc, channel, interface) == 0)
344			continue;
345		aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
346		    PCIIDE_CHANNEL_NAME(channel));
347		switch(jmidesc->sc_chan_type[channel]) {
348		case TYPE_PATA:
349			aprint_normal("PATA");
350			break;
351		case TYPE_SATA:
352			aprint_normal("SATA");
353			break;
354		case TYPE_NONE:
355			aprint_normal("unused");
356			break;
357		default:
358			aprint_normal("impossible");
359			panic("jmide: wrong/uninitialised channel type");
360		}
361		aprint_normal("\n");
362		if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
363			cp->ata_channel.ch_flags |= ATACH_DISABLED;
364			continue;
365		}
366		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
367			pciide_pci_intr);
368	}
369}
370
371static void
372jmpata_setup_channel(struct ata_channel *chp)
373{
374	struct ata_drive_datas *drvp;
375	int drive, s;
376	u_int32_t idedma_ctl;
377	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
378	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
379	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
380	int ide80p;
381
382	/* setup DMA if needed */
383	pciide_channel_dma_setup(cp);
384
385	idedma_ctl = 0;
386
387	/* cable type detect */
388	ide80p = 1;
389	if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) {
390		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
391		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) &
392		    JM_CONTROL1_PATA1_40P))
393			ide80p = 0;
394	} else {
395		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
396		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) &
397		    JM_CONTROL0_PATA0_40P))
398			ide80p = 0;
399	}
400
401	for (drive = 0; drive < 2; drive++) {
402		drvp = &chp->ch_drive[drive];
403		/* If no drive, skip */
404		if ((drvp->drive_flags & DRIVE) == 0)
405			continue;
406		if (drvp->drive_flags & DRIVE_UDMA) {
407			/* use Ultra/DMA */
408			s = splbio();
409			drvp->drive_flags &= ~DRIVE_DMA;
410			if (drvp->UDMA_mode > 2 && ide80p == 0)
411				drvp->UDMA_mode = 2;
412			splx(s);
413			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
414		} else if (drvp->drive_flags & DRIVE_DMA) {
415			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
416		}
417	}
418	/* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
419	if (idedma_ctl != 0) {
420		/* Add software bits in status register */
421		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
422		    0, idedma_ctl);
423	}
424}
425
426static int
427jmahci_print(void *aux, const char *pnp)
428{
429        if (pnp)
430                aprint_normal("ahcisata at %s", pnp);
431
432        return (UNCONF);
433}
434
435
436#ifdef NJMAHCI
437static int  jmahci_match(device_t, cfdata_t, void *);
438static void jmahci_attach(device_t, device_t, void *);
439
440CFATTACH_DECL_NEW(jmahci, sizeof(struct ahci_softc),
441	jmahci_match, jmahci_attach, NULL, NULL);
442
443static int
444jmahci_match(device_t parent, cfdata_t match, void *aux)
445{
446	return 1;
447}
448
449static void
450jmahci_attach(device_t parent, device_t self, void *aux)
451{
452	struct jmahci_attach_args *jma = aux;
453	struct pci_attach_args *pa = jma->jma_pa;
454	struct ahci_softc *sc = device_private(self);
455
456	aprint_naive(": AHCI disk controller\n");
457	aprint_normal("\n");
458
459	sc->sc_atac.atac_dev = self;
460	sc->sc_ahcit = jma->jma_ahcit;
461	sc->sc_ahcih = jma->jma_ahcih;
462	sc->sc_dmat = jma->jma_pa->pa_dmat;
463
464	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
465		sc->sc_atac_capflags = ATAC_CAP_RAID;
466
467	ahci_attach(sc);
468}
469#endif
470