jmide.c revision 1.1 
1/*	$NetBSD: jmide.c,v 1.1 2007/05/15 17:53:45 bouyer Exp $	*/
2
3/*
4 * Copyright (c) 2007 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: jmide.c,v 1.1 2007/05/15 17:53:45 bouyer Exp $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38
39#include <dev/pci/pcivar.h>
40#include <dev/pci/pcidevs.h>
41#include <dev/pci/pciidereg.h>
42#include <dev/pci/pciidevar.h>
43
44#include <dev/pci/jmide_reg.h>
45
46#include <dev/ic/ahcisatavar.h>
47
48#include "jmide.h"
49
50static const struct jmide_product *jmide_lookup(pcireg_t);
51
52static int  jmide_match(struct device *, struct cfdata *, void *);
53static void jmide_attach(struct device *, struct device *, void *);
54static int  jmide_intr(void *);
55
56static void jmpata_chip_map(struct pciide_softc*, struct pci_attach_args*);
57static void jmpata_setup_channel(struct ata_channel*);
58
59static int  jmahci_print(void *, const char *);
60
61struct jmide_product {
62	u_int32_t jm_product;
63	int jm_npata;
64	int jm_nsata;
65};
66
67static const struct jmide_product jm_products[] =  {
68	{ PCI_PRODUCT_JMICRON_JMB360,
69	  0,
70	  1
71	},
72	{ PCI_PRODUCT_JMICRON_JMB361,
73	  1,
74	  1
75	},
76	{ PCI_PRODUCT_JMICRON_JMB363,
77	  1,
78	  2
79	},
80	{ PCI_PRODUCT_JMICRON_JMB365,
81	  2,
82	  1
83	},
84	{ PCI_PRODUCT_JMICRON_JMB366,
85	  2,
86	  2
87	},
88	{ PCI_PRODUCT_JMICRON_JMB368,
89	  1,
90	  0
91	},
92	{ 0,
93	  0,
94	  0
95	}
96};
97
98typedef enum {
99	TYPE_INVALID = 0,
100	TYPE_PATA,
101	TYPE_SATA,
102	TYPE_NONE
103} jmchan_t;
104
105struct jmide_softc {
106	struct pciide_softc sc_pciide;
107	void *sc_ahci;
108	int sc_npata;
109	int sc_nsata;
110	jmchan_t sc_chan_type[PCIIDE_NUM_CHANNELS];
111	int sc_chan_swap;
112};
113
114#define JM_NAME(sc) (sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev.dv_xname)
115
116CFATTACH_DECL(jmide, sizeof(struct jmide_softc),
117    jmide_match, jmide_attach, NULL, NULL);
118
119static const struct jmide_product *
120jmide_lookup(pcireg_t id) {
121	const struct jmide_product *jp;
122
123	for (jp = jm_products; jp->jm_product != 0; jp++) {
124		if (jp->jm_product == PCI_PRODUCT(id))
125			return jp;
126	}
127	return NULL;
128}
129
130static int
131jmide_match(struct device *parent, struct cfdata *match,
132    void *aux)
133{
134	struct pci_attach_args *pa = aux;
135
136	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_JMICRON) {
137		if (jmide_lookup(pa->pa_id))
138			return (4); /* highter than ahcisata */
139	}
140	return (0);
141}
142
143static void
144jmide_attach(struct device *parent, struct device *self, void *aux)
145{
146	struct pci_attach_args *pa = aux;
147	struct jmide_softc *sc = (struct jmide_softc *)self;
148	const struct jmide_product *jp;
149        char devinfo[256];
150	const char *intrstr;
151        pci_intr_handle_t intrhandle;
152	u_int32_t pcictrl0 = pci_conf_read(pa->pa_pc, pa->pa_tag,
153	    PCI_JM_CONTROL0);
154	u_int32_t pcictrl1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
155	    PCI_JM_CONTROL1);
156	struct pciide_product_desc *pp;
157
158	jp = jmide_lookup(pa->pa_id);
159	if (jp == NULL) {
160		printf("jmide_attach: WTF?\n");
161		return;
162	}
163	sc->sc_npata = jp->jm_npata;
164	sc->sc_nsata = jp->jm_nsata;
165
166	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
167        aprint_naive(": JMICRON PATA/SATA disk controller\n");
168        aprint_normal(": %s\n", devinfo);
169
170	aprint_normal("%s: ", JM_NAME(sc));
171	if (sc->sc_npata)
172		aprint_normal("%d PATA port%s", sc->sc_npata,
173		    (sc->sc_npata > 1) ? "s" : "");
174	if (sc->sc_nsata)
175		aprint_normal("%s%d SATA port%s", sc->sc_npata ? ", " : "",
176		    sc->sc_nsata, (sc->sc_nsata > 1) ? "s" : "");
177	aprint_normal("\n");
178
179	if (pci_intr_map(pa, &intrhandle) != 0) {
180                aprint_error("%s: couldn't map interrupt\n", JM_NAME(sc));
181                return;
182        }
183        intrstr = pci_intr_string(pa->pa_pc, intrhandle);
184        sc->sc_pciide.sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle,
185	    IPL_BIO, jmide_intr, sc);
186        if (sc->sc_pciide.sc_pci_ih == NULL) {
187                aprint_error("%s: couldn't establish interrupt", JM_NAME(sc));
188                return;
189        }
190        aprint_normal("%s: interrupting at %s\n", JM_NAME(sc),
191            intrstr ? intrstr : "unknown interrupt");
192
193	if (pcictrl0 & JM_CONTROL0_AHCI_EN) {
194		/*
195		 * ahci controller enabled; disable sata on pciide and
196		 * enable on ahci
197		 */
198		pcictrl0 |= JM_CONTROL0_SATA0_AHCI | JM_CONTROL0_SATA1_AHCI;
199		pcictrl0 &= ~(JM_CONTROL0_SATA0_IDE | JM_CONTROL0_SATA1_IDE);
200		pci_conf_write(pa->pa_pc, pa->pa_tag,
201		    PCI_JM_CONTROL0, pcictrl0);
202		/* attach ahci controller if on the right function */
203		if ((pa->pa_function == 0 &&
204		      (pcictrl0 & JM_CONTROL0_AHCI_F1) == 0) ||
205	    	    (pa->pa_function == 1 &&
206		      (pcictrl0 & JM_CONTROL0_AHCI_F1) != 0)) {
207			sc->sc_ahci = config_found_ia(
208			    &sc->sc_pciide.sc_wdcdev.sc_atac.atac_dev,
209			    "jmide_hl", pa, jmahci_print);
210		}
211	}
212	sc->sc_chan_swap = ((pcictrl0 & JM_CONTROL0_PCIIDE_CS) != 0);
213	/* compute the type of internal primary channel */
214	if ((pcictrl0 & JM_CONTROL0_AHCI_EN) || sc->sc_nsata == 0) {
215		/* only a drive if second PATA enabled */
216		if (sc->sc_npata > 1 && (pcictrl1 & JM_CONTROL1_PATA1_PRI)
217		    && (pcictrl1 & JM_CONTROL1_PATA1_EN))
218			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_PATA;
219		else
220			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_NONE;
221	} else {
222		/* always SATA here */
223			sc->sc_chan_type[sc->sc_chan_swap ? 1 : 0] = TYPE_SATA;
224	}
225	/* compute the type of internal secondary channel */
226	if (((pcictrl0 & JM_CONTROL0_AHCI_EN) &&
227	    (pcictrl0 & JM_CONTROL0_PCIIDE0_MS)) || sc->sc_nsata == 0) {
228		/* only a drive if first PATA enabled */
229		if (sc->sc_npata > 0 && (pcictrl0 & JM_CONTROL0_PATA0_EN)
230		    && (pcictrl0 &
231		    (sc->sc_chan_swap ? JM_CONTROL0_PATA0_PRI: JM_CONTROL0_PATA0_SEC)))
232			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_PATA;
233		else
234			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
235	} else {
236		if (sc->sc_nsata && (pcictrl0 & JM_CONTROL0_AHCI_EN) &&
237		    (pcictrl0 & JM_CONTROL0_PCIIDE0_MS) == 0)
238			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_SATA;
239		else
240			sc->sc_chan_type[sc->sc_chan_swap ? 0 : 1] = TYPE_NONE;
241	}
242	if (sc->sc_chan_type[0] == TYPE_NONE &&
243	    sc->sc_chan_type[1] == TYPE_NONE)
244		return;
245	if (pa->pa_function == 0 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1))
246		return;
247	if (pa->pa_function == 1 && (pcictrl0 & JM_CONTROL0_PCIIDE_F1) == 0)
248		return;
249	pp = malloc(sizeof(struct pciide_product_desc), M_DEVBUF, M_NOWAIT);
250	if (pp == NULL) {
251		aprint_error("%s: can't malloc sc_pp\n", JM_NAME(sc));
252		return;
253	}
254	aprint_normal("%s: PCI IDE interface used", JM_NAME(sc));
255	pp->ide_product = 0;
256	pp->ide_flags = 0;
257	pp->ide_name = NULL;
258	pp->chip_map = jmpata_chip_map;
259	pciide_common_attach(&sc->sc_pciide, pa, pp);
260
261}
262
263static int
264jmide_intr(void *arg)
265{
266	struct jmide_softc *sc = arg;
267	int ret = 0;
268
269#ifdef NJMAHCI
270	if (sc->sc_ahci)
271		ret |= ahci_intr(sc->sc_ahci);
272#endif
273	if (sc->sc_npata)
274		ret |= pciide_pci_intr(&sc->sc_pciide);
275	return ret;
276}
277
278static void
279jmpata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
280{
281	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
282	int channel;
283	pcireg_t interface;
284	bus_size_t cmdsize, ctlsize;
285	struct pciide_channel *cp;
286
287	if (pciide_chipen(sc, pa) == 0)
288		return;
289	aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
290	pciide_mapreg_dma(sc, pa);
291	aprint_verbose("\n");
292	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
293	if (sc->sc_dma_ok) {
294		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
295		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
296	}
297	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
298	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
299	sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
300	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
301	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
302	wdc_allocate_regs(&sc->sc_wdcdev);
303	/*
304         * can't rely on the PCI_CLASS_REG content if the chip was in raid
305         * mode. We have to fake interface
306         */
307	interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
308	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
309	    channel++) {
310		cp = &sc->pciide_channels[channel];
311		if (pciide_chansetup(sc, channel, interface) == 0)
312			continue;
313		aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
314		    PCIIDE_CHANNEL_NAME(channel));
315		switch(jmidesc->sc_chan_type[channel]) {
316		case TYPE_PATA:
317			aprint_normal("PATA");
318			break;
319		case TYPE_SATA:
320			aprint_normal("SATA");
321			break;
322		case TYPE_NONE:
323			aprint_normal("unused");
324			break;
325		default:
326			aprint_normal("impossible");
327			panic("jmide: wrong/uninitialised channel type");
328		}
329		aprint_normal("\n");
330		if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
331			cp->ata_channel.ch_flags |= ATACH_DISABLED;
332			continue;
333		}
334		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
335			pciide_pci_intr);
336	}
337}
338
339static void
340jmpata_setup_channel(struct ata_channel *chp)
341{
342	struct ata_drive_datas *drvp;
343	int drive, s;
344	u_int32_t idedma_ctl;
345	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
346	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
347	struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
348	int ide80p;
349
350	/* setup DMA if needed */
351	pciide_channel_dma_setup(cp);
352
353	idedma_ctl = 0;
354
355	/* cable type detect */
356	ide80p = 1;
357	if (chp->ch_channel == (jmidesc->sc_chan_swap ? 1 : 0)) {
358		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
359		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL1) &
360		    JM_CONTROL1_PATA1_40P))
361			ide80p = 0;
362	} else {
363		if (jmidesc->sc_chan_type[chp->ch_channel] == TYPE_PATA &&
364		    (pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_JM_CONTROL0) &
365		    JM_CONTROL0_PATA0_40P))
366			ide80p = 0;
367	}
368
369	for (drive = 0; drive < 2; drive++) {
370		drvp = &chp->ch_drive[drive];
371		/* If no drive, skip */
372		if ((drvp->drive_flags & DRIVE) == 0)
373			continue;
374		if (drvp->drive_flags & DRIVE_UDMA) {
375			/* use Ultra/DMA */
376			s = splbio();
377			drvp->drive_flags &= ~DRIVE_DMA;
378			if (drvp->UDMA_mode > 2 && ide80p == 0)
379				drvp->UDMA_mode = 2;
380			splx(s);
381			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
382		} else if (drvp->drive_flags & DRIVE_DMA) {
383			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
384		}
385	}
386	/* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */
387	if (idedma_ctl != 0) {
388		/* Add software bits in status register */
389		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL],
390		    0, idedma_ctl);
391	}
392}
393
394static int
395jmahci_print(void *aux, const char *pnp)
396{
397        if (pnp)
398                aprint_normal("ahcisata at %s", pnp);
399
400        return (UNCONF);
401}
402
403
404#ifdef NJMAHCI
405static int  jmahci_match(struct device *, struct cfdata *, void *);
406static void jmahci_attach(struct device *, struct device *, void *);
407
408CFATTACH_DECL(jmahci, sizeof(struct ahci_softc),
409	jmahci_match, jmahci_attach, NULL, NULL);
410
411static int
412jmahci_match(struct device *parent, struct cfdata *match, void *aux)
413{
414	return 1;
415}
416
417static void
418jmahci_attach(struct device *parent, struct device *self, void *aux)
419{
420	struct pci_attach_args *pa = aux;
421	struct ahci_softc *sc = (struct ahci_softc *)self;
422	bus_size_t size;
423
424	if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
425	    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
426	    &sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) {
427		aprint_error("%s: can't map ahci registers\n", AHCINAME(sc));
428		return;
429	}
430	aprint_naive(": AHCI disk controller\n");
431	aprint_normal("\n");
432
433	sc->sc_dmat = pa->pa_dmat;
434	ahci_attach(sc);
435}
436#endif
437