ixgbe_osdep.c revision 1.7 
1/* $NetBSD: ixgbe_osdep.c,v 1.7 2021/04/30 06:55:32 msaitoh Exp $ */
2
3/******************************************************************************
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5  Copyright (c) 2001-2017, Intel Corporation
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34******************************************************************************/
35/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.c 327031 2017-12-20 18:15:06Z erj $*/
36
37#include <sys/cdefs.h>
38__KERNEL_RCSID(0, "$NetBSD: ixgbe_osdep.c,v 1.7 2021/04/30 06:55:32 msaitoh Exp $");
39
40#include "ixgbe_osdep.h"
41#include "ixgbe.h"
42
43inline device_t
44ixgbe_dev_from_hw(struct ixgbe_hw *hw)
45{
46	return ((struct adapter *)hw->back)->dev;
47}
48
49u16
50ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
51{
52	pci_chipset_tag_t  pc = hw->back->osdep.pc;
53	pcitag_t           tag = hw->back->osdep.tag;
54
55	switch (reg % 4) {
56	case 0:
57		return pci_conf_read(pc, tag, reg) & __BITS(15, 0);
58	case 2:
59		return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),
60		    __BITS(31, 16));
61	default:
62		panic("%s: invalid register (%" PRIx32, __func__, reg);
63		break;
64	}
65}
66
67void
68ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
69{
70	pci_chipset_tag_t  pc = hw->back->osdep.pc;
71	pcitag_t           tag = hw->back->osdep.tag;
72	pcireg_t old;
73
74	switch (reg % 4) {
75	case 0:
76		old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);
77		pci_conf_write(pc, tag, reg, value | old);
78		break;
79	case 2:
80		old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);
81		pci_conf_write(pc, tag, reg - 2,
82		    __SHIFTIN(value, __BITS(31, 16)) | old);
83		break;
84	default:
85		panic("%s: invalid register (%" PRIx32, __func__, reg);
86		break;
87	}
88
89	return;
90}
91
92inline u32
93ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
94{
95	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
96	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle, reg);
97}
98
99inline void
100ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
101{
102	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
103	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
104	    reg, val);
105}
106
107inline u32
108ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
109{
110	return bus_space_read_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
111	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
112	    reg + (offset << 2));
113}
114
115inline void
116ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
117{
118	bus_space_write_4(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
119	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
120	    reg + (offset << 2), val);
121}
122
123inline void
124ixgbe_write_barrier(struct ixgbe_hw *hw)
125{
126	bus_space_barrier(((struct adapter *)hw->back)->osdep.mem_bus_space_tag,
127	    ((struct adapter *)hw->back)->osdep.mem_bus_space_handle,
128	    0, ((struct adapter *)hw->back)->osdep.mem_size,
129	    BUS_SPACE_BARRIER_WRITE);
130}
131