1139749Simp/* $NetBSD: ixgbe_82598.c,v 1.19 2022/06/06 02:16:37 msaitoh Exp $ */ 279047Scg 379148Scg/****************************************************************************** 479047Scg SPDX-License-Identifier: BSD-3-Clause 579047Scg 679047Scg Copyright (c) 2001-2020, Intel Corporation 779047Scg All rights reserved. 879047Scg 979047Scg Redistribution and use in source and binary forms, with or without 1079047Scg modification, are permitted provided that the following conditions are met: 1179047Scg 1279047Scg 1. Redistributions of source code must retain the above copyright notice, 1379047Scg this list of conditions and the following disclaimer. 1479047Scg 1579047Scg 2. Redistributions in binary form must reproduce the above copyright 1679047Scg notice, this list of conditions and the following disclaimer in the 1779047Scg documentation and/or other materials provided with the distribution. 1879047Scg 1979047Scg 3. Neither the name of the Intel Corporation nor the names of its 2079047Scg contributors may be used to endorse or promote products derived from 2179047Scg this software without specific prior written permission. 2279047Scg 2379047Scg THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2479047Scg AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2579047Scg IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2679047Scg ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2779047Scg LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2879047Scg CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2979047Scg SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3079148Scg INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3179047Scg CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32119287Simp ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33119287Simp POSSIBILITY OF SUCH DAMAGE. 3479047Scg 3582180Scg******************************************************************************/ 3682180Scg/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 331224 2018-03-19 20:55:05Z erj $*/ 3779047Scg 3879047Scg#include <sys/cdefs.h> 39164614Sariff__KERNEL_RCSID(0, "$NetBSD: ixgbe_82598.c,v 1.19 2022/06/06 02:16:37 msaitoh Exp $"); 40164614Sariff 41164614Sariff#include "ixgbe_type.h" 42164614Sariff#include "ixgbe_82598.h" 43164614Sariff#include "ixgbe_api.h" 44164614Sariff#include "ixgbe_common.h" 45164614Sariff#include "ixgbe_phy.h" 46164614Sariff 47169278Sariff#define IXGBE_82598_MAX_TX_QUEUES 32 4879047Scg#define IXGBE_82598_MAX_RX_QUEUES 64 49152420Sariff#define IXGBE_82598_RAR_ENTRIES 16 50152420Sariff#define IXGBE_82598_MC_TBL_SIZE 128 51152420Sariff#define IXGBE_82598_VFT_TBL_SIZE 128 52152420Sariff#define IXGBE_82598_RX_PB_SIZE 512 5390880Salfred 54152420Sariffstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 55152420Sariff ixgbe_link_speed *speed, 56152420Sariff bool *autoneg); 57152420Sariffstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); 58152420Sariffstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 59152420Sariff bool autoneg_wait_to_complete); 60152420Sariffstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 61152420Sariff ixgbe_link_speed *speed, bool *link_up, 62152420Sariff bool link_up_wait_to_complete); 63152420Sariffstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 64152420Sariff ixgbe_link_speed speed, 65152420Sariff bool autoneg_wait_to_complete); 66152420Sariffstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 67152420Sariff ixgbe_link_speed speed, 68152420Sariff bool autoneg_wait_to_complete); 69152420Sariffstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw); 70152420Sariffstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq); 71157436Sariffstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); 72165304Sariffstatic void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 73152420Sariff u32 headroom, int strategy); 74152420Sariffstatic s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 75152420Sariff u8 *sff8472_data); 76152420Sariff/** 77152420Sariff * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout 78152420Sariff * @hw: pointer to the HW structure 79152420Sariff * 80164614Sariff * The defaults for 82598 should be in the range of 50us to 50ms, 81164614Sariff * however the hardware default for these parts is 500us to 1ms which is less 82164614Sariff * than the 10ms recommended by the pci-e spec. To address this we need to 83164614Sariff * increase the value to either 10ms to 250ms for capability version 1 config, 84164614Sariff * or 16ms to 55ms for version 2. 85169278Sariff **/ 86164614Sariffvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw) 87164614Sariff{ 88169278Sariff u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR); 89169278Sariff u16 pcie_devctl2; 90169278Sariff 91169278Sariff /* only take action if timeout value is defaulted to 0 */ 92169278Sariff if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK) 93169278Sariff goto out; 94169278Sariff 95152420Sariff /* 96152420Sariff * if capabilities version is type 1 we can write the 97152420Sariff * timeout of 10ms to 250ms through the GCR register 98152420Sariff */ 99152420Sariff if (!(gcr & IXGBE_GCR_CAP_VER2)) { 100152420Sariff gcr |= IXGBE_GCR_CMPL_TMOUT_10ms; 101152420Sariff goto out; 102152420Sariff } 103152420Sariff 104152420Sariff /* 105152420Sariff * for version 2 capabilities we need to write the config space 106152420Sariff * directly in order to set the completion timeout value for 107152420Sariff * 16ms to 55ms 108152420Sariff */ 109152420Sariff pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 110152420Sariff pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms; 111152420Sariff IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2); 112152420Sariffout: 113152420Sariff /* disable completion timeout resend */ 114152420Sariff gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND; 115152420Sariff IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); 116152420Sariff} 117152420Sariff 118152420Sariff/** 119152420Sariff * ixgbe_init_ops_82598 - Inits func ptrs and MAC type 120152420Sariff * @hw: pointer to hardware structure 121152420Sariff * 122152420Sariff * Initialize the function pointers and assign the MAC type for 82598. 123152420Sariff * Does not touch the hardware. 124152420Sariff **/ 125152420Sariffs32 ixgbe_init_ops_82598(struct ixgbe_hw *hw) 126152420Sariff{ 127152420Sariff struct ixgbe_mac_info *mac = &hw->mac; 128152420Sariff struct ixgbe_phy_info *phy = &hw->phy; 129152420Sariff s32 ret_val; 130152420Sariff 131152420Sariff DEBUGFUNC("ixgbe_init_ops_82598"); 132152420Sariff 133152420Sariff ret_val = ixgbe_init_phy_ops_generic(hw); 134152420Sariff ret_val = ixgbe_init_ops_generic(hw); 135152420Sariff 136157436Sariff /* PHY */ 137157436Sariff phy->ops.init = ixgbe_init_phy_ops_82598; 138165304Sariff 139165304Sariff /* MAC */ 140152420Sariff mac->ops.start_hw = ixgbe_start_hw_82598; 141152420Sariff mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598; 142152420Sariff mac->ops.reset_hw = ixgbe_reset_hw_82598; 143152420Sariff mac->ops.get_media_type = ixgbe_get_media_type_82598; 144152420Sariff mac->ops.get_supported_physical_layer = 145152420Sariff ixgbe_get_supported_physical_layer_82598; 14679047Scg mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598; 14779047Scg mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598; 148164614Sariff mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598; 149164614Sariff mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598; 15079047Scg 15179047Scg /* RAR, Multicast, VLAN */ 15279047Scg mac->ops.set_vmdq = ixgbe_set_vmdq_82598; 15379047Scg mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598; 15479047Scg mac->ops.set_vfta = ixgbe_set_vfta_82598; 15579047Scg mac->ops.set_vlvf = NULL; 156164614Sariff mac->ops.clear_vfta = ixgbe_clear_vfta_82598; 157164614Sariff 158164614Sariff /* Flow Control */ 159164614Sariff mac->ops.fc_enable = ixgbe_fc_enable_82598; 160164614Sariff 16179148Scg mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; 16279047Scg mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; 16379047Scg mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; 16479047Scg mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE; 16579148Scg mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 16679148Scg mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 167111183Scognet mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 16879047Scg 16979047Scg /* SFP+ Module */ 17079047Scg phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; 17179047Scg phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598; 17279148Scg 17383617Scg /* Link */ 174164614Sariff mac->ops.check_link = ixgbe_check_mac_link_82598; 175169278Sariff mac->ops.setup_link = ixgbe_setup_mac_link_82598; 17679047Scg mac->ops.flap_tx_laser = NULL; 17779148Scg mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598; 178118729Sorion mac->ops.setup_rxpba = ixgbe_set_rxpba_82598; 17979047Scg 18079047Scg /* Manageability interface */ 181169278Sariff mac->ops.set_fw_drv_ver = NULL; 18279148Scg 18379148Scg mac->ops.get_rtrup2tc = NULL; 18479047Scg 18579047Scg return ret_val; 18679148Scg} 187169278Sariff 18879148Scg/** 189169278Sariff * ixgbe_init_phy_ops_82598 - PHY/SFP specific init 190111183Scognet * @hw: pointer to hardware structure 19198940Sscottl * 192152420Sariff * Initialize any function pointers that were not able to be 193152420Sariff * set during init_shared_code because the PHY/SFP type was 194152644Syongari * not known. Perform the SFP init if necessary. 195152420Sariff * 19679047Scg **/ 19779047Scgs32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 19879047Scg{ 19979047Scg struct ixgbe_mac_info *mac = &hw->mac; 200164614Sariff struct ixgbe_phy_info *phy = &hw->phy; 20179047Scg s32 ret_val = IXGBE_SUCCESS; 20279047Scg u16 list_offset, data_offset; 20379047Scg 20479148Scg DEBUGFUNC("ixgbe_init_phy_ops_82598"); 20579148Scg 20679047Scg /* Identify the PHY */ 20779047Scg phy->ops.identify(hw); 20879047Scg 209164614Sariff /* Overwrite the link function pointers if copper PHY */ 21079047Scg if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 21179047Scg mac->ops.setup_link = ixgbe_setup_copper_link_82598; 21279047Scg mac->ops.get_link_capabilities = 21379047Scg ixgbe_get_copper_link_capabilities_generic; 214164614Sariff } 21579047Scg 216164614Sariff switch (hw->phy.type) { 21779047Scg case ixgbe_phy_tn: 218164614Sariff phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 21979047Scg phy->ops.check_link = ixgbe_check_phy_link_tnx; 220164614Sariff phy->ops.get_firmware_version = 22179047Scg ixgbe_get_phy_firmware_version_tnx; 22279047Scg break; 22379047Scg case ixgbe_phy_nl: 224152420Sariff phy->ops.reset = ixgbe_reset_phy_nl; 225164614Sariff 22679047Scg /* Call SFP+ identify routine to get the SFP+ module type */ 22779047Scg ret_val = phy->ops.identify_sfp(hw); 22879047Scg if (ret_val != IXGBE_SUCCESS) 22979148Scg goto out; 23079047Scg else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) { 23179047Scg ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 23279148Scg goto out; 23379047Scg } 23479047Scg 23579148Scg /* Check to see if SFP+ module is supported */ 23679047Scg ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, 23779047Scg &list_offset, 23879047Scg &data_offset); 23979047Scg if (ret_val != IXGBE_SUCCESS) { 24079047Scg ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; 24179047Scg goto out; 24279047Scg } 24379047Scg break; 244164614Sariff default: 245164614Sariff break; 24679047Scg } 24779148Scg 24879148Scgout: 24979148Scg return ret_val; 25079047Scg} 251164614Sariff 252152644Syongari/** 25379047Scg * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx 254169278Sariff * @hw: pointer to hardware structure 255152644Syongari * 25679047Scg * Starts the hardware using the generic start_hw function. 257164614Sariff * Disables relaxed ordering Then set pcie completion timeout 25879047Scg * 25979047Scg **/ 26079047Scgs32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 26179047Scg{ 26279047Scg u32 regval; 26379047Scg u32 i; 26479148Scg s32 ret_val = IXGBE_SUCCESS; 26579047Scg 26679047Scg DEBUGFUNC("ixgbe_start_hw_82598"); 26779148Scg 268164614Sariff ret_val = ixgbe_start_hw_generic(hw); 26979047Scg if (ret_val) 27079047Scg return ret_val; 27179047Scg 272164614Sariff /* Disable relaxed ordering */ 27379047Scg for (i = 0; ((i < hw->mac.max_tx_queues) && 27479047Scg (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 27579148Scg regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 27679047Scg regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 27779047Scg IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 27879148Scg } 27979148Scg 280164614Sariff for (i = 0; ((i < hw->mac.max_rx_queues) && 28179047Scg (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 28279047Scg regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 28379047Scg regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 28479047Scg IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 28579047Scg IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 28679047Scg } 28779047Scg 28879047Scg /* set the completion timeout for interface */ 28979047Scg ixgbe_set_pcie_completion_timeout(hw); 29079047Scg 29179148Scg return ret_val; 29279047Scg} 29379047Scg 29479148Scg/** 29579047Scg * ixgbe_get_link_capabilities_82598 - Determines link capabilities 296152420Sariff * @hw: pointer to hardware structure 297164614Sariff * @speed: pointer to link speed 29882478Scg * @autoneg: boolean auto-negotiation value 29979047Scg * 300111183Scognet * Determines the link capabilities by reading the AUTOC register. 301164614Sariff **/ 302164614Sariffstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, 303164614Sariff ixgbe_link_speed *speed, 304164614Sariff bool *autoneg) 305164614Sariff{ 306164614Sariff s32 status = IXGBE_SUCCESS; 307164614Sariff u32 autoc = 0; 308152420Sariff 30979047Scg DEBUGFUNC("ixgbe_get_link_capabilities_82598"); 31079148Scg 31182478Scg /* 31290880Salfred * Determine link capabilities based on the stored value of AUTOC, 31390880Salfred * which represents EEPROM defaults. If AUTOC value has not been 31479047Scg * stored, use the current register value. 31579047Scg */ 31679047Scg if (hw->mac.orig_link_settings_stored) 31779148Scg autoc = hw->mac.orig_autoc; 31879148Scg else 31979047Scg autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 32079148Scg 32179047Scg switch (autoc & IXGBE_AUTOC_LMS_MASK) { 32279148Scg case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 32379148Scg *speed = IXGBE_LINK_SPEED_1GB_FULL; 32479148Scg *autoneg = FALSE; 32579148Scg break; 32679148Scg 32779148Scg case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 32879148Scg *speed = IXGBE_LINK_SPEED_10GB_FULL; 329164614Sariff *autoneg = FALSE; 33079047Scg break; 33179148Scg 332150979Snetchild case IXGBE_AUTOC_LMS_1G_AN: 333150979Snetchild *speed = IXGBE_LINK_SPEED_1GB_FULL; 33479148Scg *autoneg = TRUE; 335150979Snetchild break; 336150979Snetchild 337150979Snetchild case IXGBE_AUTOC_LMS_KX4_AN: 33879148Scg case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 33979148Scg *speed = IXGBE_LINK_SPEED_UNKNOWN; 34079148Scg if (autoc & IXGBE_AUTOC_KX4_SUPP) 34179148Scg *speed |= IXGBE_LINK_SPEED_10GB_FULL; 342164614Sariff if (autoc & IXGBE_AUTOC_KX_SUPP) 343169278Sariff *speed |= IXGBE_LINK_SPEED_1GB_FULL; 34479148Scg *autoneg = TRUE; 34579047Scg break; 346169278Sariff 347169278Sariff default: 348169278Sariff status = IXGBE_ERR_LINK_SETUP; 349169278Sariff break; 350169278Sariff } 351169278Sariff 352169278Sariff return status; 353169278Sariff} 354169278Sariff 355169278Sariff/** 35679148Scg * ixgbe_get_media_type_82598 - Determines media type 357164614Sariff * @hw: pointer to hardware structure 35879047Scg * 35979047Scg * Returns the media type (fiber, copper, backplane) 36079148Scg **/ 36179148Scgstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) 36279047Scg{ 36379047Scg enum ixgbe_media_type media_type; 36479148Scg 36579047Scg DEBUGFUNC("ixgbe_get_media_type_82598"); 36679047Scg 36779047Scg /* Detect if there is a copper PHY attached. */ 36883617Scg switch (hw->phy.type) { 36979047Scg case ixgbe_phy_cu_unknown: 370152420Sariff case ixgbe_phy_tn: 37179148Scg media_type = ixgbe_media_type_copper; 37279148Scg goto out; 37379148Scg default: 37479047Scg break; 37579047Scg } 37679047Scg 37779047Scg /* Media type for I82598 is based on device ID */ 37879148Scg switch (hw->device_id) { 379169278Sariff case IXGBE_DEV_ID_82598: 380169278Sariff case IXGBE_DEV_ID_82598_BX: 381164614Sariff /* Default device ID is mezzanine card KX/KX4 */ 38283617Scg media_type = ixgbe_media_type_backplane; 38379047Scg break; 38479148Scg case IXGBE_DEV_ID_82598AF_DUAL_PORT: 38579148Scg case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 38679148Scg case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 38779148Scg case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 388164614Sariff case IXGBE_DEV_ID_82598EB_XF_LR: 38988206Sorion case IXGBE_DEV_ID_82598EB_SFP_LOM: 39079148Scg media_type = ixgbe_media_type_fiber; 39179047Scg break; 39282478Scg case IXGBE_DEV_ID_82598EB_CX4: 39379148Scg case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 39482478Scg media_type = ixgbe_media_type_cx4; 395164614Sariff break; 39688206Sorion case IXGBE_DEV_ID_82598AT: 39779148Scg case IXGBE_DEV_ID_82598AT2: 39879047Scg media_type = ixgbe_media_type_copper; 39982478Scg break; 40079148Scg default: 40182478Scg media_type = ixgbe_media_type_unknown; 402164614Sariff break; 40388206Sorion } 40479148Scgout: 40579047Scg return media_type; 40679148Scg} 407164614Sariff 40879047Scg/** 40979047Scg * ixgbe_fc_enable_82598 - Enable flow control 410169278Sariff * @hw: pointer to hardware structure 411164614Sariff * 412164614Sariff * Enable flow control according to the current settings. 413152420Sariff **/ 414169278Sariffs32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw) 415169278Sariff{ 416169278Sariff s32 ret_val = IXGBE_SUCCESS; 417164614Sariff u32 fctrl_reg; 41879047Scg u32 rmcs_reg; 419152420Sariff u32 reg; 420164614Sariff u32 fcrtl, fcrth; 421152420Sariff u32 link_speed = 0; 42279047Scg int i; 423164614Sariff bool link_up; 42479047Scg 42579047Scg DEBUGFUNC("ixgbe_fc_enable_82598"); 42679047Scg 427164614Sariff /* Validate the water mark configuration */ 42879047Scg if (!hw->fc.pause_time) { 429164614Sariff ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 430164614Sariff goto out; 431164614Sariff } 432164614Sariff 433169278Sariff /* Low water mark of zero causes XOFF floods */ 434164614Sariff for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 435164614Sariff if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 436164614Sariff hw->fc.high_water[i]) { 437164614Sariff if (!hw->fc.low_water[i] || 438164614Sariff hw->fc.low_water[i] >= hw->fc.high_water[i]) { 439164614Sariff DEBUGOUT("Invalid water mark configuration\n"); 44079047Scg ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 44179047Scg goto out; 44279047Scg } 443164614Sariff } 44479047Scg } 44579047Scg 44679047Scg /* 44779047Scg * On 82598 having Rx FC on causes resets while doing 1G 448164614Sariff * so if it's on turn it off once we know link_speed. For 449169278Sariff * more details see 82598 Specification update. 450164614Sariff */ 451164614Sariff hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 452164614Sariff if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { 453164614Sariff switch (hw->fc.requested_mode) { 454164614Sariff case ixgbe_fc_full: 45588033Sorion hw->fc.requested_mode = ixgbe_fc_tx_pause; 456152420Sariff break; 457152420Sariff case ixgbe_fc_rx_pause: 458152420Sariff hw->fc.requested_mode = ixgbe_fc_none; 45988033Sorion break; 46088033Sorion default: 461152420Sariff /* no change */ 462152420Sariff break; 463152420Sariff } 46494647Sjhay } 465164614Sariff 46694647Sjhay /* Negotiate the fc mode to use */ 46794647Sjhay ixgbe_fc_autoneg(hw); 468164614Sariff 469152420Sariff /* Disable any previous flow control settings */ 47088033Sorion fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); 47188361Sorion fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); 47288033Sorion 473164614Sariff rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 47479047Scg rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); 47579047Scg 47679047Scg /* 477164614Sariff * The possible values of fc.current_mode are: 47879047Scg * 0: Flow control is completely disabled 47979047Scg * 1: Rx flow control is enabled (we can receive pause frames, 48079148Scg * but not send pause frames). 48179047Scg * 2: Tx flow control is enabled (we can send pause frames but 482164614Sariff * we do not support receiving pause frames). 483169278Sariff * 3: Both Rx and Tx flow control (symmetric) are enabled. 484164614Sariff * other: Invalid. 485164614Sariff */ 486164614Sariff switch (hw->fc.current_mode) { 487164614Sariff case ixgbe_fc_none: 488164614Sariff /* 489169278Sariff * Flow control is disabled by software override or autoneg. 490169278Sariff * The code below will actually disable it in the HW. 491169278Sariff */ 492169278Sariff break; 493169278Sariff case ixgbe_fc_rx_pause: 494169278Sariff /* 49579148Scg * Rx Flow control is enabled and Tx Flow control is 49679148Scg * disabled by software override. Since there really 497152420Sariff * isn't a way to advertise that we are capable of RX 49882478Scg * Pause ONLY, we will advertise that we support both 499152420Sariff * symmetric and asymmetric Rx PAUSE. Later, we will 50079047Scg * disable the adapter's ability to send PAUSE frames. 501164614Sariff */ 50279047Scg fctrl_reg |= IXGBE_FCTRL_RFCE; 50379047Scg break; 50479047Scg case ixgbe_fc_tx_pause: 50579148Scg /* 50679047Scg * Tx Flow control is enabled, and Rx Flow control is 50779047Scg * disabled by software override. 50879047Scg */ 50979047Scg rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 510164614Sariff break; 511169278Sariff case ixgbe_fc_full: 512164614Sariff /* Flow control (both Rx and Tx) is enabled by SW override. */ 513164614Sariff fctrl_reg |= IXGBE_FCTRL_RFCE; 514164614Sariff rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; 515164614Sariff break; 516164614Sariff default: 51779047Scg DEBUGOUT("Flow control param set incorrectly\n"); 51879047Scg ret_val = IXGBE_ERR_CONFIG; 51979047Scg goto out; 520152420Sariff break; 521164614Sariff } 52289516Sorion 523152420Sariff /* Set 802.3x based flow control settings. */ 52479047Scg fctrl_reg |= IXGBE_FCTRL_DPF; 525170521Sariff IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); 52679047Scg IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); 527152420Sariff 52879148Scg /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 529152420Sariff for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 53079047Scg if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 53179047Scg hw->fc.high_water[i]) { 532170521Sariff fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 533170521Sariff fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 53479047Scg IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); 535164614Sariff IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); 53679047Scg } else { 53779047Scg IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); 53879047Scg IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); 53979148Scg } 54079047Scg 54179047Scg } 54279047Scg 543164614Sariff /* Configure pause time (2 TCs per register) */ 54479047Scg reg = (u32)hw->fc.pause_time * 0x00010001; 545164614Sariff for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 546169278Sariff IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 547164614Sariff 548164614Sariff /* Configure flow control refresh threshold value */ 549164614Sariff IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 550164614Sariff 551164614Sariffout: 552152420Sariff return ret_val; 55382478Scg} 554152420Sariff 55579148Scg/** 55682478Scg * ixgbe_start_mac_link_82598 - Configures MAC link settings 55779148Scg * @hw: pointer to hardware structure 558164614Sariff * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 55979047Scg * 56079047Scg * Configures link settings based on values in the ixgbe_hw struct. 56179047Scg * Restarts the link. Performs autonegotiation if needed. 56279148Scg **/ 56379047Scgstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, 56479148Scg bool autoneg_wait_to_complete) 56579148Scg{ 566164614Sariff u32 autoc_reg; 567164614Sariff u32 links_reg; 568164614Sariff u32 i; 569169278Sariff s32 status = IXGBE_SUCCESS; 570164614Sariff 571164614Sariff DEBUGFUNC("ixgbe_start_mac_link_82598"); 572164614Sariff 573164614Sariff /* Restart link */ 574164614Sariff autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 575164614Sariff autoc_reg |= IXGBE_AUTOC_AN_RESTART; 57679047Scg IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 57779047Scg 57879148Scg /* Only poll for autoneg to complete if specified to do so */ 57979148Scg if (autoneg_wait_to_complete) { 58079148Scg if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 58179148Scg IXGBE_AUTOC_LMS_KX4_AN || 58279148Scg (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 58379148Scg IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 58479148Scg links_reg = 0; /* Just in case Autoneg time = 0 */ 58579148Scg for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 58679047Scg links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 58779047Scg if (links_reg & IXGBE_LINKS_KX_AN_COMP) 58879148Scg break; 58979047Scg msec_delay(100); 59079047Scg } 59179047Scg if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 59279148Scg status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 59379047Scg DEBUGOUT("Autonegotiation did not complete.\n"); 59479047Scg } 59579047Scg } 59679047Scg } 59779047Scg 598164614Sariff /* Add delay to filter out noises during initial link setup */ 59979148Scg msec_delay(50); 60079047Scg 601152420Sariff return status; 602164614Sariff} 603164614Sariff 604169278Sariff/** 605164614Sariff * ixgbe_validate_link_ready - Function looks for phy link 606164614Sariff * @hw: pointer to hardware structure 607164614Sariff * 608164614Sariff * Function indicates success when phy link is available. If phy is not ready 609164614Sariff * within 5 seconds of MAC indicating link, the function returns error. 61088215Sorion **/ 61188206Sorionstatic s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw) 61288206Sorion{ 61388206Sorion u32 timeout; 61488206Sorion u16 an_reg; 61588206Sorion 61688206Sorion if (hw->device_id != IXGBE_DEV_ID_82598AT2) 61779148Scg return IXGBE_SUCCESS; 61879148Scg 619117272Scg for (timeout = 0; 62088206Sorion timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { 62188206Sorion hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 622117272Scg IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); 623164614Sariff 62490880Salfred if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && 62579148Scg (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) 62688206Sorion break; 62779148Scg 628152420Sariff msec_delay(100); 629152420Sariff } 63088206Sorion 631152420Sariff if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) { 632152420Sariff DEBUGOUT("Link was indicated but link is down\n"); 63388206Sorion return IXGBE_ERR_LINK_SETUP; 63488206Sorion } 63588206Sorion 63688206Sorion return IXGBE_SUCCESS; 63788206Sorion} 63888206Sorion 63988206Sorion/** 64088206Sorion * ixgbe_check_mac_link_82598 - Get link/speed status 64188206Sorion * @hw: pointer to hardware structure 64288206Sorion * @speed: pointer to link speed 64388206Sorion * @link_up: TRUE is link is up, FALSE otherwise 64488206Sorion * @link_up_wait_to_complete: bool used to wait for link up or not 64588206Sorion * 64688206Sorion * Reads the links register to determine if link is up and the current speed 64779047Scg **/ 64888206Sorionstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, 649117272Scg ixgbe_link_speed *speed, bool *link_up, 650164614Sariff bool link_up_wait_to_complete) 65190880Salfred{ 65279047Scg u32 links_reg; 653152420Sariff u32 i; 65488206Sorion u16 link_reg, adapt_comp_reg; 655117272Scg 65688206Sorion DEBUGFUNC("ixgbe_check_mac_link_82598"); 65788206Sorion 65879047Scg /* 65979047Scg * SERDES PHY requires us to read link status from undocumented 66088033Sorion * register 0xC79F. Bit 0 set indicates link is up/ready; clear 661117272Scg * indicates link down. OxC00C is read to check that the XAUI lanes 662117272Scg * are active. Bit 0 clear indicates active; set indicates inactive. 663113056Sorion */ 66488033Sorion if (hw->phy.type == ixgbe_phy_nl) { 66588033Sorion hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 66688033Sorion hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 66788033Sorion hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 66888033Sorion &adapt_comp_reg); 669159732Snetchild if (link_up_wait_to_complete) { 670159732Snetchild for (i = 0; i < hw->mac.max_link_up_time; i++) { 671159732Snetchild if ((link_reg & 1) && 672164614Sariff ((adapt_comp_reg & 1) == 0)) { 673164614Sariff *link_up = TRUE; 674117272Scg break; 675117272Scg } else { 67688033Sorion *link_up = FALSE; 67788033Sorion } 678164614Sariff msec_delay(100); 67988033Sorion hw->phy.ops.read_reg(hw, 0xC79F, 68088033Sorion IXGBE_TWINAX_DEV, 681164614Sariff &link_reg); 682164614Sariff hw->phy.ops.read_reg(hw, 0xC00C, 683164614Sariff IXGBE_TWINAX_DEV, 684164614Sariff &adapt_comp_reg); 685164614Sariff } 686164614Sariff } else { 687164614Sariff if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) 688164614Sariff *link_up = TRUE; 689164614Sariff else 690164614Sariff *link_up = FALSE; 691169278Sariff } 692169278Sariff 693169278Sariff if (*link_up == FALSE) 694169278Sariff goto out; 695164614Sariff } 696164614Sariff 697164614Sariff links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 69879047Scg if (link_up_wait_to_complete) { 699117272Scg for (i = 0; i < hw->mac.max_link_up_time; i++) { 700113056Sorion if (links_reg & IXGBE_LINKS_UP) { 701113056Sorion *link_up = TRUE; 70288108Sorion break; 703164614Sariff } else { 704164614Sariff *link_up = FALSE; 70588108Sorion } 70698940Sscottl msec_delay(100); 70798940Sscottl links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 70889516Sorion } 709164614Sariff } else { 710164614Sariff if (links_reg & IXGBE_LINKS_UP) 71189516Sorion *link_up = TRUE; 71298940Sscottl else 713164614Sariff *link_up = FALSE; 71498940Sscottl } 71598940Sscottl 716169278Sariff if (links_reg & IXGBE_LINKS_SPEED) 71798940Sscottl *speed = IXGBE_LINK_SPEED_10GB_FULL; 718169278Sariff else 719169278Sariff *speed = IXGBE_LINK_SPEED_1GB_FULL; 72098940Sscottl 72189516Sorion if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) && 72289516Sorion (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS)) 72388108Sorion *link_up = FALSE; 72488108Sorion 72589516Sorionout: 72689516Sorion return IXGBE_SUCCESS; 72789516Sorion} 72888108Sorion 72988108Sorion/** 730164614Sariff * ixgbe_setup_mac_link_82598 - Set MAC link speed 731164614Sariff * @hw: pointer to hardware structure 732169278Sariff * @speed: new link speed 733164614Sariff * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 734164614Sariff * 735164614Sariff * Set the link speed in the AUTOC register and restarts link. 736169278Sariff **/ 73788108Sorionstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, 73889516Sorion ixgbe_link_speed speed, 73989516Sorion bool autoneg_wait_to_complete) 74089516Sorion{ 74189516Sorion bool autoneg = FALSE; 74289516Sorion s32 status = IXGBE_SUCCESS; 74389516Sorion ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 74489516Sorion u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 74589516Sorion u32 autoc = curr_autoc; 74689516Sorion u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 74789516Sorion 74889516Sorion DEBUGFUNC("ixgbe_setup_mac_link_82598"); 74988108Sorion 75089516Sorion /* Check to see if speed passed in is supported. */ 75189516Sorion ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); 75289516Sorion speed &= link_capabilities; 753164614Sariff 75488108Sorion if (speed == IXGBE_LINK_SPEED_UNKNOWN) 75589516Sorion status = IXGBE_ERR_LINK_SETUP; 75689516Sorion 75789516Sorion /* Set KX4/KX support according to speed requested */ 75888108Sorion else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || 75989516Sorion link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { 760164614Sariff autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; 76189516Sorion if (speed & IXGBE_LINK_SPEED_10GB_FULL) 76289516Sorion autoc |= IXGBE_AUTOC_KX4_SUPP; 76389516Sorion if (speed & IXGBE_LINK_SPEED_1GB_FULL) 76489516Sorion autoc |= IXGBE_AUTOC_KX_SUPP; 765164614Sariff if (autoc != curr_autoc) 76689516Sorion IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 76789516Sorion } 76889516Sorion 76989516Sorion if (status == IXGBE_SUCCESS) { 77089516Sorion /* 77189516Sorion * Setup and restart the link based on the new values in 77289516Sorion * ixgbe_hw This will write the AUTOC register based on the new 773164614Sariff * stored values 77489516Sorion */ 77589516Sorion status = ixgbe_start_mac_link_82598(hw, 77689516Sorion autoneg_wait_to_complete); 77789516Sorion } 77889516Sorion 77989516Sorion return status; 780169278Sariff} 781164614Sariff 782164614Sariff 78398940Sscottl/** 78489516Sorion * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field 78589516Sorion * @hw: pointer to hardware structure 786171363Sariff * @speed: new link speed 787171363Sariff * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 788171363Sariff * 789171363Sariff * Sets the link speed in the AUTOC register in the MAC and restarts link. 790171363Sariff **/ 79189516Sorionstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 79289516Sorion ixgbe_link_speed speed, 79388108Sorion bool autoneg_wait_to_complete) 79488108Sorion{ 79588108Sorion s32 status; 79688108Sorion 79788209Sorion DEBUGFUNC("ixgbe_setup_copper_link_82598"); 79889516Sorion 79989516Sorion /* Setup the PHY according to input speed */ 80089516Sorion status = hw->phy.ops.setup_link_speed(hw, speed, 80189516Sorion autoneg_wait_to_complete); 80289516Sorion /* Set up MAC */ 80389516Sorion ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); 804169278Sariff 805164614Sariff return status; 80688209Sorion} 807164614Sariff 808164614Sariff/** 80998940Sscottl * ixgbe_reset_hw_82598 - Performs hardware reset 81088108Sorion * @hw: pointer to hardware structure 81188108Sorion * 81288108Sorion * Resets the hardware by resetting the transmit and receive units, masks and 81379148Scg * clears all interrupts, performing a PHY reset, and performing a link (MAC) 81479047Scg * reset. 81579148Scg **/ 81679148Scgstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw) 81779148Scg{ 818111183Scognet s32 status = IXGBE_SUCCESS; 819111183Scognet s32 phy_status = IXGBE_SUCCESS; 82079148Scg u32 ctrl; 82179148Scg u32 gheccr; 82279047Scg u32 i; 82379047Scg u32 autoc; 82479047Scg u8 analog_val; 82579047Scg 826164614Sariff DEBUGFUNC("ixgbe_reset_hw_82598"); 82779047Scg 82879148Scg /* Call adapter stop to disable tx/rx and clear interrupts */ 82979047Scg status = hw->mac.ops.stop_adapter(hw); 83079148Scg if (status != IXGBE_SUCCESS) 83179148Scg goto reset_hw_out; 832102106Sorion 833117296Scg /* 834152420Sariff * Power up the Atlas Tx lanes if they are currently powered down. 835152420Sariff * Atlas Tx lanes are powered down for MAC loopback tests, but 836152420Sariff * they are not automatically restored on reset. 837152420Sariff */ 838169278Sariff hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val); 839152644Syongari if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { 840102106Sorion /* Enable Tx Atlas so packets can be transmitted again */ 841102106Sorion hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 84279047Scg &analog_val); 843157028Sariff analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; 84479148Scg hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, 845157028Sariff analog_val); 846157028Sariff 847157028Sariff hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 84879047Scg &analog_val); 84983617Scg analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; 850164614Sariff hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, 85183617Scg analog_val); 852164614Sariff 85379148Scg hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 854164614Sariff &analog_val); 85579047Scg analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; 85679047Scg hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, 85779047Scg analog_val); 85879047Scg 85979047Scg hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 860152420Sariff &analog_val); 861152420Sariff analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; 86279047Scg hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, 863152420Sariff analog_val); 864152420Sariff } 865152420Sariff 866152420Sariff /* Reset PHY */ 867152420Sariff if (hw->phy.reset_disable == FALSE) { 868152420Sariff /* PHY ops must be identified and initialized prior to reset */ 869152420Sariff 870152420Sariff /* Init PHY and function pointers, perform SFP setup */ 871152420Sariff phy_status = hw->phy.ops.init(hw); 872152420Sariff if ((phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED) || 873152420Sariff (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)) 87479148Scg goto mac_reset_top; 875152420Sariff 87679047Scg hw->phy.ops.reset(hw); 87779047Scg } 87879047Scg 87979047Scgmac_reset_top: 88079047Scg /* 881154168Sariff * Issue global reset to the MAC. This needs to be a SW reset. 882164614Sariff * If link reset is used, it might reset the MAC when mng is using it 883152420Sariff */ 88479047Scg ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST; 885164614Sariff IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 88679047Scg IXGBE_WRITE_FLUSH(hw); 887170873Sariff 888167608Sariff /* Poll for reset bit to self-clear indicating reset is complete */ 88979047Scg for (i = 0; i < 10; i++) { 89079047Scg usec_delay(1); 891152420Sariff ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 892152420Sariff if (!(ctrl & IXGBE_CTRL_RST)) 893154168Sariff break; 89490880Salfred } 89590880Salfred if (ctrl & IXGBE_CTRL_RST) { 89690880Salfred status = IXGBE_ERR_RESET_FAILED; 89790880Salfred DEBUGOUT("Reset polling failed to complete.\n"); 898152420Sariff } 89990880Salfred 90090880Salfred msec_delay(50); 90190880Salfred 90290880Salfred /* 90390880Salfred * Double resets are required for recovery from certain error 90490880Salfred * conditions. Between resets, it is necessary to stall to allow time 90590880Salfred * for any pending HW events to complete. 906102106Sorion */ 907169278Sariff if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 908169278Sariff hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 909169278Sariff goto mac_reset_top; 910169278Sariff } 911169278Sariff 912169278Sariff gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR); 913169278Sariff gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6)); 914169278Sariff IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr); 915169278Sariff 916152644Syongari /* 917152644Syongari * Store the original AUTOC value if it has not been 918152644Syongari * stored off yet. Otherwise restore the stored original 919152644Syongari * AUTOC value since the reset operation sets back to defaults. 920152644Syongari */ 921152644Syongari autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 922127651Smatk if (hw->mac.orig_link_settings_stored == FALSE) { 923127651Smatk hw->mac.orig_autoc = autoc; 924127651Smatk hw->mac.orig_link_settings_stored = TRUE; 925127651Smatk } else if (autoc != hw->mac.orig_autoc) { 926127651Smatk IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc); 927127651Smatk } 928152644Syongari 929152644Syongari /* Store the permanent mac address */ 930152644Syongari hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 931118729Sorion 932118729Sorion /* 933118729Sorion * Store MAC address from RAR0, clear receive address registers, and 934152644Syongari * clear the multicast table 935118729Sorion */ 936118729Sorion hw->mac.ops.init_rx_addrs(hw); 937118729Sorion 938118729Sorionreset_hw_out: 939118729Sorion if (phy_status != IXGBE_SUCCESS) 94079148Scg status = phy_status; 941127135Snjl 942127135Snjl return status; 943127135Snjl} 944127135Snjl 945118729Sorion/** 94679047Scg * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address 94779047Scg * @hw: pointer to hardware struct 94879047Scg * @rar: receive address register index to associate with a VMDq index 94979047Scg * @vmdq: VMDq set index 95079148Scg **/ 95179047Scgs32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 95279047Scg{ 95379047Scg u32 rar_high; 95479047Scg u32 rar_entries = hw->mac.num_rar_entries; 95579047Scg 956164614Sariff DEBUGFUNC("ixgbe_set_vmdq_82598"); 957164614Sariff 958164614Sariff /* Make sure we are using a valid rar index range */ 959169278Sariff if (rar >= rar_entries) { 960169278Sariff DEBUGOUT1("RAR index %d is out of range.\n", rar); 961164614Sariff return IXGBE_ERR_INVALID_ARGUMENT; 962164614Sariff } 963164614Sariff 964164614Sariff rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 965164614Sariff rar_high &= ~IXGBE_RAH_VIND_MASK; 966164614Sariff rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); 967164614Sariff IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 968164614Sariff return IXGBE_SUCCESS; 969164614Sariff} 970164614Sariff 971164614Sariff/** 972164614Sariff * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address 973169278Sariff * @hw: pointer to hardware struct 974169278Sariff * @rar: receive address register index to associate with a VMDq index 975169278Sariff * @vmdq: VMDq clear index (not used in 82598, but elsewhere) 976169278Sariff **/ 97779047Scgstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 97879047Scg{ 979169278Sariff u32 rar_high; 980169278Sariff u32 rar_entries = hw->mac.num_rar_entries; 981169278Sariff 982169278Sariff UNREFERENCED_1PARAMETER(vmdq); 983174552Sariff 984174552Sariff /* Make sure we are using a valid rar index range */ 985174552Sariff if (rar >= rar_entries) { 986174552Sariff DEBUGOUT1("RAR index %d is out of range.\n", rar); 98789516Sorion return IXGBE_ERR_INVALID_ARGUMENT; 988127135Snjl } 989169278Sariff 990169278Sariff rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 991169278Sariff if (rar_high & IXGBE_RAH_VIND_MASK) { 99289516Sorion rar_high &= ~IXGBE_RAH_VIND_MASK; 99389516Sorion IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high); 99489516Sorion } 99589516Sorion 99679148Scg return IXGBE_SUCCESS; 99779047Scg} 99879047Scg 99979047Scg/** 100079047Scg * ixgbe_set_vfta_82598 - Set VLAN filter table 100179047Scg * @hw: pointer to hardware structure 100279047Scg * @vlan: VLAN id to write to VLAN filter 100379047Scg * @vind: VMDq output index that maps queue to VLAN id in VFTA 1004154132Sariff * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1005154132Sariff * @vlvf_bypass: boolean flag - unused 1006154168Sariff * 1007154168Sariff * Turn on/off specified VLAN in the VLAN filter table. 1008154132Sariff **/ 1009154168Sariffs32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, 1010154378Sariff bool vlan_on, bool vlvf_bypass) 1011154168Sariff{ 1012191911Smav u32 regindex; 1013156376Sariff u32 bitindex; 1014154378Sariff u32 bits; 1015158210Sariff u32 vftabyte; 1016156308Sariff 1017158210Sariff UNREFERENCED_1PARAMETER(vlvf_bypass); 1018161300Syongari 1019164783Sariff DEBUGFUNC("ixgbe_set_vfta_82598"); 1020164614Sariff 1021164614Sariff if (vlan > 4095) 1022154132Sariff return IXGBE_ERR_PARAM; 1023154168Sariff 1024154168Sariff /* Determine 32-bit word position in array */ 1025154168Sariff regindex = (vlan >> 5) & 0x7F; /* upper seven bits */ 1026154168Sariff 1027154132Sariff /* Determine the location of the (VMD) queue index */ 102879047Scg vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ 102979148Scg bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ 103079047Scg 103186795Sorion /* Set the nibble for VMD queue index */ 103286708Sorion bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex)); 103386708Sorion bits &= (~(0x0F << bitindex)); 1034174552Sariff bits |= (vind << bitindex); 1035174552Sariff IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits); 103694647Sjhay 103779047Scg /* Determine the location of the bit for this VLAN id */ 1038169278Sariff bitindex = vlan & 0x1F; /* lower five bits */ 1039169278Sariff 1040169278Sariff bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 1041169278Sariff if (vlan_on) 1042169278Sariff /* Turn on this VLAN id */ 1043169278Sariff bits |= (1 << bitindex); 1044169278Sariff else 1045169278Sariff /* Turn off this VLAN id */ 1046169278Sariff bits &= ~(1 << bitindex); 1047169278Sariff IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits); 1048169278Sariff 1049169278Sariff return IXGBE_SUCCESS; 1050169278Sariff} 1051169278Sariff 1052169278Sariff/** 1053169278Sariff * ixgbe_clear_vfta_82598 - Clear VLAN filter table 1054169278Sariff * @hw: pointer to hardware structure 1055169278Sariff * 1056169278Sariff * Clears the VLAN filter table, and the VMDq index associated with the filter 1057169278Sariff **/ 1058169278Sariffstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) 1059169278Sariff{ 1060169278Sariff u32 offset; 1061169278Sariff u32 vlanbyte; 1062169278Sariff 1063169278Sariff DEBUGFUNC("ixgbe_clear_vfta_82598"); 1064169278Sariff 1065169278Sariff for (offset = 0; offset < hw->mac.vft_size; offset++) 1066164614Sariff IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 106779148Scg 106879047Scg for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) 106983617Scg for (offset = 0; offset < hw->mac.vft_size; offset++) 107083617Scg IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), 107183617Scg 0); 107283617Scg 107379148Scg return IXGBE_SUCCESS; 1074169278Sariff} 1075169278Sariff 1076169278Sariff/** 1077169278Sariff * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register 1078164614Sariff * @hw: pointer to hardware structure 107979148Scg * @reg: analog register to read 1080164614Sariff * @val: read value 1081164614Sariff * 1082169278Sariff * Performs read operation to Atlas analog register specified. 1083169278Sariff **/ 1084169278Sariffs32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) 1085164614Sariff{ 1086164614Sariff u32 atlas_ctl; 108798940Sscottl 108898940Sscottl DEBUGFUNC("ixgbe_read_analog_reg8_82598"); 1089164614Sariff 109079047Scg IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, 109179047Scg IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); 109279047Scg IXGBE_WRITE_FLUSH(hw); 109379047Scg usec_delay(10); 109489516Sorion atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); 109589516Sorion *val = (u8)atlas_ctl; 109689516Sorion 109789516Sorion return IXGBE_SUCCESS; 109879047Scg} 1099118729Sorion 110079047Scg/** 110179047Scg * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register 1102118729Sorion * @hw: pointer to hardware structure 110379047Scg * @reg: atlas register to write 1104155568Sariff * @val: value to write 1105155568Sariff * 1106167773Sariff * Performs write operation to Atlas analog register specified. 1107167773Sariff **/ 1108169278Sariffs32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) 1109169278Sariff{ 1110155568Sariff u32 atlas_ctl; 1111155568Sariff 1112152420Sariff DEBUGFUNC("ixgbe_write_analog_reg8_82598"); 1113152420Sariff 111479047Scg atlas_ctl = (reg << 8) | val; 1115164614Sariff IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); 111679047Scg IXGBE_WRITE_FLUSH(hw); 111779047Scg usec_delay(10); 111879047Scg 111979047Scg return IXGBE_SUCCESS; 112079047Scg} 112179047Scg 112279047Scg/** 112379047Scg * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface. 112479047Scg * @hw: pointer to hardware structure 112579047Scg * @dev_addr: address to read from 1126164614Sariff * @byte_offset: byte offset to read from dev_addr 112779047Scg * @eeprom_data: value read 112879047Scg * 112979148Scg * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 113079148Scg **/ 1131118729Sorionstatic s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr, 1132118729Sorion u8 byte_offset, u8 *eeprom_data) 1133155568Sariff{ 1134167773Sariff s32 status = IXGBE_SUCCESS; 1135169278Sariff u16 sfp_addr = 0; 113679047Scg u16 sfp_data = 0; 1137152420Sariff u16 sfp_stat = 0; 113879047Scg u16 gssr; 1139164614Sariff u32 i; 114079047Scg 114179047Scg DEBUGFUNC("ixgbe_read_i2c_phy_82598"); 1142120101Snjl 1143120101Snjl if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1144120101Snjl gssr = IXGBE_GSSR_PHY1_SM; 1145120101Snjl else 1146120101Snjl gssr = IXGBE_GSSR_PHY0_SM; 1147120101Snjl 1148120101Snjl if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS) 1149120101Snjl return IXGBE_ERR_SWFW_SYNC; 1150120101Snjl 1151120101Snjl if (hw->phy.type == ixgbe_phy_nl) { 1152120101Snjl /* 1153120101Snjl * NetLogic phy SDA/SCL registers are at addresses 0xC30A to 1154120101Snjl * 0xC30D. These registers are used to talk to the SFP+ 1155120101Snjl * module's EEPROM through the SDA/SCL (I2C) interface. 1156120101Snjl */ 1157120101Snjl sfp_addr = (dev_addr << 8) + byte_offset; 1158120101Snjl sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 1159120101Snjl hw->phy.ops.write_reg_mdi(hw, 1160120101Snjl IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 1161120101Snjl IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1162120101Snjl sfp_addr); 1163120101Snjl 116479047Scg /* Poll status */ 116588361Sorion for (i = 0; i < 100; i++) { 116688361Sorion hw->phy.ops.read_reg_mdi(hw, 116788361Sorion IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 116888361Sorion IXGBE_MDIO_PMA_PMD_DEV_TYPE, 116988361Sorion &sfp_stat); 1170117296Scg sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1171152420Sariff if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 117288361Sorion break; 117388361Sorion msec_delay(10); 117488361Sorion } 1175152420Sariff 117688361Sorion if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) { 1177152420Sariff DEBUGOUT("EEPROM read did not pass.\n"); 117888361Sorion status = IXGBE_ERR_SFP_NOT_PRESENT; 117988361Sorion goto out; 1180152420Sariff } 1181164614Sariff 118288361Sorion /* Read data */ 118388361Sorion hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 118488361Sorion IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 118579047Scg 118679047Scg *eeprom_data = (u8)(sfp_data >> 8); 118779047Scg } else { 118888361Sorion status = IXGBE_ERR_PHY; 118979047Scg } 119079047Scg 119179047Scgout: 1192120101Snjl hw->mac.ops.release_swfw_sync(hw, gssr); 1193120101Snjl return status; 1194120101Snjl} 1195120101Snjl 1196120101Snjl/** 1197120101Snjl * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface. 1198152420Sariff * @hw: pointer to hardware structure 119979047Scg * @byte_offset: EEPROM byte offset to read 120079047Scg * @eeprom_data: value read 120179047Scg * 1202152420Sariff * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. 1203164614Sariff **/ 120479047Scgs32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset, 120579047Scg u8 *eeprom_data) 1206120101Snjl{ 1207155568Sariff return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR, 1208120101Snjl byte_offset, eeprom_data); 120979047Scg} 121079047Scg 1211164614Sariff/** 121279047Scg * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface. 121388361Sorion * @hw: pointer to hardware structure 121488361Sorion * @byte_offset: byte offset at address 0xA2 121588361Sorion * @sff8472_data: value read 121688361Sorion * 121788361Sorion * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C 121888361Sorion **/ 121988361Sorionstatic s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset, 122088361Sorion u8 *sff8472_data) 122188361Sorion{ 1222164614Sariff return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2, 122379047Scg byte_offset, sff8472_data); 122479047Scg} 122579047Scg 122679047Scg/** 122779047Scg * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 122879047Scg * @hw: pointer to hardware structure 122979047Scg * 123088361Sorion * Determines physical layer capabilities of the current configuration. 123179047Scg **/ 123279047Scgu64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 123379047Scg{ 123479047Scg u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 123579047Scg u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 123679047Scg u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 123779047Scg u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 123882180Scg u16 ext_ability = 0; 123979047Scg 124079047Scg DEBUGFUNC("ixgbe_get_supported_physical_layer_82598"); 124179047Scg 1242132236Stanimura hw->phy.ops.identify(hw); 124379047Scg 1244 /* Copper PHY must be checked before AUTOC LMS to determine correct 1245 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1246 switch (hw->phy.type) { 1247 case ixgbe_phy_tn: 1248 case ixgbe_phy_cu_unknown: 1249 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1250 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1251 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1252 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1253 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1254 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1255 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1256 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1257 goto out; 1258 default: 1259 break; 1260 } 1261 1262 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1263 case IXGBE_AUTOC_LMS_1G_AN: 1264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1265 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX) 1266 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1267 else 1268 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1269 break; 1270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1271 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4) 1272 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1273 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4) 1274 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1275 else /* XAUI */ 1276 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1277 break; 1278 case IXGBE_AUTOC_LMS_KX4_AN: 1279 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN: 1280 if (autoc & IXGBE_AUTOC_KX_SUPP) 1281 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1282 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1283 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1284 break; 1285 default: 1286 break; 1287 } 1288 1289 if (hw->phy.type == ixgbe_phy_nl) { 1290 hw->phy.ops.identify_sfp(hw); 1291 1292 switch (hw->phy.sfp_type) { 1293 case ixgbe_sfp_type_da_cu: 1294 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1295 break; 1296 case ixgbe_sfp_type_sr: 1297 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1298 break; 1299 case ixgbe_sfp_type_lr: 1300 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1301 break; 1302 default: 1303 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1304 break; 1305 } 1306 } 1307 1308 switch (hw->device_id) { 1309 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 1310 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1311 break; 1312 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1313 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1314 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 1315 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1316 break; 1317 case IXGBE_DEV_ID_82598EB_XF_LR: 1318 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324out: 1325 return physical_layer; 1326} 1327 1328/** 1329 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple 1330 * port devices. 1331 * @hw: pointer to the HW structure 1332 * 1333 * Calls common function and corrects issue with some single port devices 1334 * that enable LAN1 but not LAN0. 1335 **/ 1336void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw) 1337{ 1338 struct ixgbe_bus_info *bus = &hw->bus; 1339 u16 pci_gen = 0; 1340 u16 pci_ctrl2 = 0; 1341 1342 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598"); 1343 1344 ixgbe_set_lan_id_multi_port_pcie(hw); 1345 1346 /* check if LAN0 is disabled */ 1347 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen); 1348 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) { 1349 1350 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2); 1351 1352 /* if LAN0 is completely disabled force function to 0 */ 1353 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) && 1354 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) && 1355 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) { 1356 1357 bus->func = 0; 1358 } 1359 } 1360} 1361 1362/** 1363 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering 1364 * @hw: pointer to hardware structure 1365 * 1366 **/ 1367void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw) 1368{ 1369 u32 regval; 1370 u32 i; 1371 1372 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598"); 1373 1374 /* Enable relaxed ordering */ 1375 for (i = 0; ((i < hw->mac.max_tx_queues) && 1376 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1377 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); 1378 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 1379 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); 1380 } 1381 1382 for (i = 0; ((i < hw->mac.max_rx_queues) && 1383 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { 1384 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 1385 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 1386 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 1387 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 1388 } 1389 1390} 1391 1392/** 1393 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer 1394 * @hw: pointer to hardware structure 1395 * @num_pb: number of packet buffers to allocate 1396 * @headroom: reserve n KB of headroom 1397 * @strategy: packet buffer allocation strategy 1398 **/ 1399static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb, 1400 u32 headroom, int strategy) 1401{ 1402 u32 rxpktsize = IXGBE_RXPBSIZE_64KB; 1403 u8 i = 0; 1404 UNREFERENCED_1PARAMETER(headroom); 1405 1406 if (!num_pb) 1407 return; 1408 1409 /* Setup Rx packet buffer sizes */ 1410 switch (strategy) { 1411 case PBA_STRATEGY_WEIGHTED: 1412 /* Setup the first four at 80KB */ 1413 rxpktsize = IXGBE_RXPBSIZE_80KB; 1414 for (; i < 4; i++) 1415 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1416 /* Setup the last four at 48KB...don't re-init i */ 1417 rxpktsize = IXGBE_RXPBSIZE_48KB; 1418 /* Fall Through */ 1419 case PBA_STRATEGY_EQUAL: 1420 default: 1421 /* Divide the remaining Rx packet buffer evenly among the TCs */ 1422 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1423 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 1424 break; 1425 } 1426 1427 /* Setup Tx packet buffer sizes */ 1428 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) 1429 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB); 1430} 1431 1432/** 1433 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit 1434 * @hw: pointer to hardware structure 1435 * @regval: register value to write to RXCTRL 1436 * 1437 * Enables the Rx DMA unit 1438 **/ 1439s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval) 1440{ 1441 DEBUGFUNC("ixgbe_enable_rx_dma_82598"); 1442 1443 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 1444 1445 return IXGBE_SUCCESS; 1446} 1447