if_vrreg.h revision 1.5
1/* $NetBSD: if_vrreg.h,v 1.5 1999/02/02 00:05:02 thorpej Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_vrreg.h,v 1.2 1999/01/10 18:51:49 wpaul Exp $ 35 */ 36 37/* 38 * Rhine register definitions. 39 */ 40 41#define VR_PAR0 0x00 /* node address 0 to 4 */ 42#define VR_PAR1 0x04 /* node address 2 to 6 */ 43#define VR_RXCFG 0x06 /* receiver config register */ 44#define VR_TXCFG 0x07 /* transmit config register */ 45#define VR_COMMAND 0x08 /* command register */ 46#define VR_ISR 0x0C /* interrupt/status register */ 47#define VR_IMR 0x0E /* interrupt mask register */ 48#define VR_MAR0 0x10 /* multicast hash 0 */ 49#define VR_MAR1 0x14 /* multicast hash 1 */ 50#define VR_RXADDR 0x18 /* rx descriptor list start addr */ 51#define VR_TXADDR 0x1C /* tx descriptor list start addr */ 52#define VR_CURRXDESC0 0x20 53#define VR_CURRXDESC1 0x24 54#define VR_CURRXDESC2 0x28 55#define VR_CURRXDESC3 0x2C 56#define VR_NEXTRXDESC0 0x30 57#define VR_NEXTRXDESC1 0x34 58#define VR_NEXTRXDESC2 0x38 59#define VR_NEXTRXDESC3 0x3C 60#define VR_CURTXDESC0 0x40 61#define VR_CURTXDESC1 0x44 62#define VR_CURTXDESC2 0x48 63#define VR_CURTXDESC3 0x4C 64#define VR_NEXTTXDESC0 0x50 65#define VR_NEXTTXDESC1 0x54 66#define VR_NEXTTXDESC2 0x58 67#define VR_NEXTTXDESC3 0x5C 68#define VR_CURRXDMA 0x60 /* current RX DMA address */ 69#define VR_CURTXDMA 0x64 /* current TX DMA address */ 70#define VR_TALLYCNT 0x68 /* tally counter test register */ 71#define VR_PHYADDR 0x6C 72#define VR_MIISTAT 0x6D 73#define VR_BCR0 0x6E 74#define VR_BCR1 0x6F 75#define VR_MIICMD 0x70 76#define VR_MIIADDR 0x71 77#define VR_MIIDATA 0x72 78#define VR_EECSR 0x74 79#define VR_TEST 0x75 80#define VR_GPIO 0x76 81#define VR_CONFIG 0x78 82#define VR_MPA_CNT 0x7C 83#define VR_CRC_CNT 0x7E 84 85/* 86 * RX config bits. 87 */ 88#define VR_RXCFG_RX_ERRPKTS 0x01 89#define VR_RXCFG_RX_RUNT 0x02 90#define VR_RXCFG_RX_MULTI 0x04 91#define VR_RXCFG_RX_BROAD 0x08 92#define VR_RXCFG_RX_PROMISC 0x10 93#define VR_RXCFG_RX_THRESH 0xE0 94 95#define VR_RXTHRESH_32BYTES 0x00 96#define VR_RXTHRESH_64BYTES 0x20 97#define VR_RXTHRESH_128BYTES 0x40 98#define VR_RXTHRESH_256BYTES 0x60 99#define VR_RXTHRESH_512BYTES 0x80 100#define VR_RXTHRESH_768BYTES 0xA0 101#define VR_RXTHRESH_1024BYTES 0xC0 102#define VR_RXTHRESH_STORENFWD 0xE0 103 104/* 105 * TX config bits. 106 */ 107#define VR_TXCFG_RSVD0 0x01 108#define VR_TXCFG_LOOPBKMODE 0x06 109#define VR_TXCFG_BACKOFF 0x08 110#define VR_TXCFG_RSVD1 0x10 111#define VR_TXCFG_TX_THRESH 0xE0 112 113#define VR_TXTHRESH_32BYTES 0x00 114#define VR_TXTHRESH_64BYTES 0x20 115#define VR_TXTHRESH_128BYTES 0x40 116#define VR_TXTHRESH_256BYTES 0x60 117#define VR_TXTHRESH_512BYTES 0x80 118#define VR_TXTHRESH_768BYTES 0xA0 119#define VR_TXTHRESH_1024BYTES 0xC0 120#define VR_TXTHRESH_STORENFWD 0xE0 121 122/* 123 * Command register bits. 124 */ 125#define VR_CMD_INIT 0x0001 126#define VR_CMD_START 0x0002 127#define VR_CMD_STOP 0x0004 128#define VR_CMD_RX_ON 0x0008 129#define VR_CMD_TX_ON 0x0010 130#define VR_CMD_TX_GO 0x0020 131#define VR_CMD_RX_GO 0x0040 132#define VR_CMD_RSVD 0x0080 133#define VR_CMD_RX_EARLY 0x0100 134#define VR_CMD_TX_EARLY 0x0200 135#define VR_CMD_FULLDUPLEX 0x0400 136#define VR_CMD_TX_NOPOLL 0x0800 137 138#define VR_CMD_RESET 0x8000 139 140/* 141 * Interrupt status bits. 142 */ 143#define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 144#define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 145#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 146#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 147#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 148#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 149#define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 150#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 151#define VR_ISR_RX_EARLY 0x0100 /* rx early */ 152#define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 153#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 154#define VR_ISR_RX_DROPPED 0x0800 155#define VR_ISR_RX_NOBUF2 0x1000 156#define VR_ISR_TX_ABRT2 0x2000 157#define VR_ISR_LINKSTAT2 0x4000 158#define VR_ISR_MAGICPACKET 0x8000 159 160/* 161 * Interrupt mask bits. 162 */ 163#define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 164#define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 165#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 166#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 167#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 168#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 169#define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 170#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 171#define VR_IMR_RX_EARLY 0x0100 /* rx early */ 172#define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 173#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 174#define VR_IMR_RX_DROPPED 0x0800 175#define VR_IMR_RX_NOBUF2 0x1000 176#define VR_IMR_TX_ABRT2 0x2000 177#define VR_IMR_LINKSTAT2 0x4000 178#define VR_IMR_MAGICPACKET 0x8000 179 180#define VR_INTRS \ 181 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 182 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 183 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 184 185/* 186 * MII status register. 187 */ 188 189#define VR_MIISTAT_SPEED 0x01 190#define VR_MIISTAT_LINKFAULT 0x02 191#define VR_MIISTAT_MGTREADERR 0x04 192#define VR_MIISTAT_MIIERR 0x08 193#define VR_MIISTAT_PHYOPT 0x10 194#define VR_MIISTAT_MDC_SPEED 0x20 195#define VR_MIISTAT_RSVD 0x40 196#define VR_MIISTAT_GPIO1POLL 0x80 197 198/* 199 * MII command register bits. 200 */ 201#define VR_MIICMD_CLK 0x01 202#define VR_MIICMD_DATAOUT 0x02 203#define VR_MIICMD_DATAIN 0x04 204#define VR_MIICMD_DIR 0x08 205#define VR_MIICMD_DIRECTPGM 0x10 206#define VR_MIICMD_WRITE_ENB 0x20 207#define VR_MIICMD_READ_ENB 0x40 208#define VR_MIICMD_AUTOPOLL 0x80 209 210/* 211 * EEPROM control bits. 212 */ 213#define VR_EECSR_DATAIN 0x01 /* data out */ 214#define VR_EECSR_DATAOUT 0x02 /* data in */ 215#define VR_EECSR_CLK 0x04 /* clock */ 216#define VR_EECSR_CS 0x08 /* chip select */ 217#define VR_EECSR_DPM 0x10 218#define VR_EECSR_LOAD 0x20 219#define VR_EECSR_EMBP 0x40 220#define VR_EECSR_EEPR 0x80 221 222#define VR_EECMD_WRITE 0x140 223#define VR_EECMD_READ 0x180 224#define VR_EECMD_ERASE 0x1c0 225 226/* 227 * Test register bits. 228 */ 229#define VR_TEST_TEST0 0x01 230#define VR_TEST_TEST1 0x02 231#define VR_TEST_TEST2 0x04 232#define VR_TEST_TSTUD 0x08 233#define VR_TEST_TSTOV 0x10 234#define VR_TEST_BKOFF 0x20 235#define VR_TEST_FCOL 0x40 236#define VR_TEST_HBDES 0x80 237 238/* 239 * Config register bits. 240 */ 241#define VR_CFG_GPIO2OUTENB 0x00000001 242#define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 243#define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 244#define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 245#define VR_CFG_MIIOPT 0x00000010 246#define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 247#define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 248#define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 249#define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 250#define VR_CFG_MRREADWAIT 0x00000200 251#define VR_CFG_MRWRITEWAIT 0x00000400 252#define VR_CFG_RX_ARB 0x00000800 253#define VR_CFG_TX_ARB 0x00001000 254#define VR_CFG_READMULTI 0x00002000 255#define VR_CFG_TX_PACE 0x00004000 256#define VR_CFG_TX_QDIS 0x00008000 257#define VR_CFG_ROMSEL0 0x00010000 258#define VR_CFG_ROMSEL1 0x00020000 259#define VR_CFG_ROMSEL2 0x00040000 260#define VR_CFG_ROMTIMESEL 0x00080000 261#define VR_CFG_RSVD0 0x00100000 262#define VR_CFG_ROMDLY 0x00200000 263#define VR_CFG_ROMOPT 0x00400000 264#define VR_CFG_RSVD1 0x00800000 265#define VR_CFG_BACKOFFOPT 0x01000000 266#define VR_CFG_BACKOFFMOD 0x02000000 267#define VR_CFG_CAPEFFECT 0x04000000 268#define VR_CFG_BACKOFFRAND 0x08000000 269#define VR_CFG_MAGICKPACKET 0x10000000 270#define VR_CFG_PCIREADLINE 0x20000000 271#define VR_CFG_DIAG 0x40000000 272#define VR_CFG_GPIOEN 0x80000000 273 274/* 275 * Rhine TX/RX list structure. 276 */ 277 278struct vr_desc { 279 u_int32_t vr_status; 280 u_int32_t vr_ctl; 281 u_int32_t vr_ptr1; 282 u_int32_t vr_ptr2; 283}; 284 285#define vr_data vr_ptr1 286#define vr_next vr_ptr2 287 288 289#define VR_RXSTAT_RXERR 0x00000001 290#define VR_RXSTAT_CRCERR 0x00000002 291#define VR_RXSTAT_FRAMEALIGNERR 0x00000004 292#define VR_RXSTAT_FIFOOFLOW 0x00000008 293#define VR_RXSTAT_GIANT 0x00000010 294#define VR_RXSTAT_RUNT 0x00000020 295#define VR_RXSTAT_BUSERR 0x00000040 296#define VR_RXSTAT_BUFFERR 0x00000080 297#define VR_RXSTAT_LASTFRAG 0x00000100 298#define VR_RXSTAT_FIRSTFRAG 0x00000200 299#define VR_RXSTAT_RLINK 0x00000400 300#define VR_RXSTAT_RX_PHYS 0x00000800 301#define VR_RXSTAT_RX_BROAD 0x00001000 302#define VR_RXSTAT_RX_MULTI 0x00002000 303#define VR_RXSTAT_RX_OK 0x00004000 304#define VR_RXSTAT_RXLEN 0x07FF0000 305#define VR_RXSTAT_RXLEN_EXT 0x78000000 306#define VR_RXSTAT_OWN 0x80000000 307 308#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 309#define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 310 311#define VR_RXCTL_BUFLEN 0x000007FF 312#define VR_RXCTL_BUFLEN_EXT 0x00007800 313#define VR_RXCTL_CHAIN 0x00008000 314#define VR_RXCTL_RX_INTR 0x00800000 315 316#define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 317 318#define VR_TXSTAT_DEFER 0x00000001 319#define VR_TXSTAT_UNDERRUN 0x00000002 320#define VR_TXSTAT_COLLCNT 0x00000078 321#define VR_TXSTAT_SQE 0x00000080 322#define VR_TXSTAT_ABRT 0x00000100 323#define VR_TXSTAT_LATECOLL 0x00000200 324#define VR_TXSTAT_CARRLOST 0x00000400 325#define VR_TXSTAT_BUSERR 0x00002000 326#define VR_TXSTAT_JABTIMEO 0x00004000 327#define VR_TXSTAT_ERRSUM 0x00008000 328#define VR_TXSTAT_OWN 0x80000000 329 330#define VR_TXCTL_BUFLEN 0x000007FF 331#define VR_TXCTL_BUFLEN_EXT 0x00007800 332#define VR_TXCTL_TLINK 0x00008000 333#define VR_TXCTL_FIRSTFRAG 0x00200000 334#define VR_TXCTL_LASTFRAG 0x00400000 335#define VR_TXCTL_FINT 0x00800000 336 337 338#define VR_MAXFRAGS 16 339#define VR_RX_LIST_CNT 64 340#define VR_TX_LIST_CNT 64 341#define VR_MIN_FRAMELEN 60 342#define VR_FRAMELEN 1536 343#define VR_RXLEN 1520 344 345#define VR_TXOWN(x) x->vr_ptr->vr_status 346 347struct vr_list_data { 348 struct vr_desc vr_rx_list[VR_RX_LIST_CNT]; 349 struct vr_desc vr_tx_list[VR_TX_LIST_CNT]; 350}; 351 352struct vr_chain { 353 struct vr_desc *vr_ptr; 354 struct mbuf *vr_mbuf; 355 struct vr_chain *vr_nextdesc; 356}; 357 358struct vr_chain_onefrag { 359 struct vr_desc *vr_ptr; 360 struct mbuf *vr_mbuf; 361 struct vr_chain_onefrag *vr_nextdesc; 362}; 363 364struct vr_chain_data { 365 struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT]; 366 struct vr_chain vr_tx_chain[VR_TX_LIST_CNT]; 367 368 struct vr_chain_onefrag *vr_rx_head; 369 370 struct vr_chain *vr_tx_head; 371 struct vr_chain *vr_tx_tail; 372 struct vr_chain *vr_tx_free; 373}; 374 375struct vr_type { 376 pci_vendor_id_t vr_vid; 377 pci_product_id_t vr_did; 378 char *vr_name; 379}; 380 381struct vr_mii_frame { 382 u_int8_t mii_stdelim; 383 u_int8_t mii_opcode; 384 u_int8_t mii_phyaddr; 385 u_int8_t mii_regaddr; 386 u_int8_t mii_turnaround; 387 u_int16_t mii_data; 388}; 389 390/* 391 * MII constants 392 */ 393#define VR_MII_STARTDELIM 0x01 394#define VR_MII_READOP 0x02 395#define VR_MII_WRITEOP 0x01 396#define VR_MII_TURNAROUND 0x02 397 398#define VR_FLAG_FORCEDELAY 1 399#define VR_FLAG_SCHEDDELAY 2 400#define VR_FLAG_DELAYTIMEO 3 401 402struct vr_softc { 403 struct device vr_dev; 404 void *vr_ih; 405 void *vr_ats; 406 bus_space_tag_t vr_bustag; 407 bus_space_handle_t vr_bushandle; 408 pci_chipset_tag_t vr_pc; 409 struct ethercom vr_ec; 410 u_int8_t vr_enaddr[ETHER_ADDR_LEN]; 411 struct ifmedia ifmedia; /* media info */ 412 bus_space_handle_t vr_bhandle; /* bus space handle */ 413 bus_space_tag_t vr_btag; /* bus space tag */ 414 struct vr_type *vr_info; /* Rhine adapter info */ 415 struct vr_type *vr_pinfo; /* phy info */ 416 u_int8_t vr_unit; /* interface number */ 417 u_int8_t vr_type; 418 u_int8_t vr_phy_addr; /* PHY address */ 419 u_int8_t vr_tx_pend; /* TX pending */ 420 u_int8_t vr_want_auto; 421 u_int8_t vr_autoneg; 422 caddr_t vr_ldata_ptr; 423 struct vr_list_data *vr_ldata; 424 struct vr_chain_data vr_cdata; 425}; 426 427/* 428 * register space access macros 429 */ 430#define CSR_WRITE_4(sc, reg, val) \ 431 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val) 432#define CSR_WRITE_2(sc, reg, val) \ 433 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val) 434#define CSR_WRITE_1(sc, reg, val) \ 435 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val) 436 437#define CSR_READ_4(sc, reg) \ 438 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg) 439#define CSR_READ_2(sc, reg) \ 440 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg) 441#define CSR_READ_1(sc, reg) \ 442 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg) 443 444#define VR_TIMEOUT 1000 445 446/* 447 * General constants that are fun to know. 448 * 449 * VIA vendor ID 450 */ 451#define VIA_VENDORID 0x1106 452 453/* 454 * VIA Rhine device IDs. 455 */ 456#define VIA_DEVICEID_RHINE 0x3043 457#define VIA_DEVICEID_RHINE_II 0x6100 458 459 460/* 461 * Texas Instruments PHY identifiers 462 */ 463#define TI_PHY_VENDORID 0x4000 464#define TI_PHY_10BT 0x501F 465#define TI_PHY_100VGPMI 0x502F 466 467/* 468 * These ID values are for the NS DP83840A 10/100 PHY 469 */ 470#define NS_PHY_VENDORID 0x2000 471#define NS_PHY_83840A 0x5C0F 472 473/* 474 * Level 1 10/100 PHY 475 */ 476#define LEVEL1_PHY_VENDORID 0x7810 477#define LEVEL1_PHY_LXT970 0x000F 478 479/* 480 * Intel 82555 10/100 PHY 481 */ 482#define INTEL_PHY_VENDORID 0x0A28 483#define INTEL_PHY_82555 0x015F 484 485/* 486 * SEEQ 80220 10/100 PHY 487 */ 488#define SEEQ_PHY_VENDORID 0x0016 489#define SEEQ_PHY_80220 0xF83F 490 491 492/* 493 * PCI low memory base and low I/O base register, and 494 * other PCI registers. 495 */ 496 497#define VR_PCI_VENDOR_ID 0x00 498#define VR_PCI_DEVICE_ID 0x02 499#define VR_PCI_COMMAND 0x04 500#define VR_PCI_STATUS 0x06 501#define VR_PCI_CLASSCODE 0x09 502#define VR_PCI_LATENCY_TIMER 0x0D 503#define VR_PCI_HEADER_TYPE 0x0E 504#define VR_PCI_LOIO 0x10 505#define VR_PCI_LOMEM 0x14 506#define VR_PCI_BIOSROM 0x30 507#define VR_PCI_INTLINE 0x3C 508#define VR_PCI_INTPIN 0x3D 509#define VR_PCI_MINGNT 0x3E 510#define VR_PCI_MINLAT 0x0F 511#define VR_PCI_RESETOPT 0x48 512#define VR_PCI_EEPROM_DATA 0x4C 513 514/* power management registers */ 515#define VR_PCI_CAPID 0xDC /* 8 bits */ 516#define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 517#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 518#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 519 520#define VR_PSTATE_MASK 0x0003 521#define VR_PSTATE_D0 0x0000 522#define VR_PSTATE_D1 0x0002 523#define VR_PSTATE_D2 0x0002 524#define VR_PSTATE_D3 0x0003 525#define VR_PME_EN 0x0010 526#define VR_PME_STATUS 0x8000 527 528#define PHY_UNKNOWN 6 529 530#define VR_PHYADDR_MIN 0x00 531#define VR_PHYADDR_MAX 0x1F 532 533#define PHY_BMCR 0x00 534#define PHY_BMSR 0x01 535#define PHY_VENID 0x02 536#define PHY_DEVID 0x03 537#define PHY_ANAR 0x04 538#define PHY_LPAR 0x05 539#define PHY_ANEXP 0x06 540 541#define PHY_ANAR_NEXTPAGE 0x8000 542#define PHY_ANAR_RSVD0 0x4000 543#define PHY_ANAR_TLRFLT 0x2000 544#define PHY_ANAR_RSVD1 0x1000 545#define PHY_ANAR_RSVD2 0x0800 546#define PHY_ANAR_RSVD3 0x0400 547#define PHY_ANAR_100BT4 0x0200 548#define PHY_ANAR_100BTXFULL 0x0100 549#define PHY_ANAR_100BTXHALF 0x0080 550#define PHY_ANAR_10BTFULL 0x0040 551#define PHY_ANAR_10BTHALF 0x0020 552#define PHY_ANAR_PROTO4 0x0010 553#define PHY_ANAR_PROTO3 0x0008 554#define PHY_ANAR_PROTO2 0x0004 555#define PHY_ANAR_PROTO1 0x0002 556#define PHY_ANAR_PROTO0 0x0001 557 558/* 559 * These are the register definitions for the PHY (physical layer 560 * interface chip). 561 */ 562/* 563 * PHY BMCR Basic Mode Control Register 564 */ 565#define PHY_BMCR_RESET 0x8000 566#define PHY_BMCR_LOOPBK 0x4000 567#define PHY_BMCR_SPEEDSEL 0x2000 568#define PHY_BMCR_AUTONEGENBL 0x1000 569#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 570#define PHY_BMCR_ISOLATE 0x0400 571#define PHY_BMCR_AUTONEGRSTR 0x0200 572#define PHY_BMCR_DUPLEX 0x0100 573#define PHY_BMCR_COLLTEST 0x0080 574#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 575#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 576#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 577#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 578#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 579#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 580#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 581/* 582 * RESET: 1 == software reset, 0 == normal operation 583 * Resets status and control registers to default values. 584 * Relatches all hardware config values. 585 * 586 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 587 * 588 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 589 * Link speed is selected byt his bit or if auto-negotiation if bit 590 * 12 (AUTONEGENBL) is set (in which case the value of this register 591 * is ignored). 592 * 593 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 594 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 595 * determine speed and mode. Should be cleared and then set if PHY configured 596 * for no autoneg on startup. 597 * 598 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 599 * 600 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 601 * 602 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 603 * 604 * COLLTEST: 1 == collision test enabled, 0 == normal operation 605 */ 606 607/* 608 * PHY, BMSR Basic Mode Status Register 609 */ 610#define PHY_BMSR_100BT4 0x8000 611#define PHY_BMSR_100BTXFULL 0x4000 612#define PHY_BMSR_100BTXHALF 0x2000 613#define PHY_BMSR_10BTFULL 0x1000 614#define PHY_BMSR_10BTHALF 0x0800 615#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 616#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 617#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 618#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 619#define PHY_BMSR_MFPRESUP 0x0040 620#define PHY_BMSR_AUTONEGCOMP 0x0020 621#define PHY_BMSR_REMFAULT 0x0010 622#define PHY_BMSR_CANAUTONEG 0x0008 623#define PHY_BMSR_LINKSTAT 0x0004 624#define PHY_BMSR_JABBER 0x0002 625#define PHY_BMSR_EXTENDED 0x0001 626