if_vrreg.h revision 1.1
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_vrreg.h,v 1.1 1999/01/21 11:55:22 sakamoto Exp $ 33 */ 34 35/* 36 * Rhine register definitions. 37 */ 38 39#define VR_PAR0 0x00 /* node address 0 to 4 */ 40#define VR_PAR1 0x04 /* node address 2 to 6 */ 41#define VR_RXCFG 0x06 /* receiver config register */ 42#define VR_TXCFG 0x07 /* transmit config register */ 43#define VR_COMMAND 0x08 /* command register */ 44#define VR_ISR 0x0C /* interrupt/status register */ 45#define VR_IMR 0x0E /* interrupt mask register */ 46#define VR_MAR0 0x10 /* multicast hash 0 */ 47#define VR_MAR1 0x14 /* multicast hash 1 */ 48#define VR_RXADDR 0x18 /* rx descriptor list start addr */ 49#define VR_TXADDR 0x1C /* tx descriptor list start addr */ 50#define VR_CURRXDESC0 0x20 51#define VR_CURRXDESC1 0x24 52#define VR_CURRXDESC2 0x28 53#define VR_CURRXDESC3 0x2C 54#define VR_NEXTRXDESC0 0x30 55#define VR_NEXTRXDESC1 0x34 56#define VR_NEXTRXDESC2 0x38 57#define VR_NEXTRXDESC3 0x3C 58#define VR_CURTXDESC0 0x40 59#define VR_CURTXDESC1 0x44 60#define VR_CURTXDESC2 0x48 61#define VR_CURTXDESC3 0x4C 62#define VR_NEXTTXDESC0 0x50 63#define VR_NEXTTXDESC1 0x54 64#define VR_NEXTTXDESC2 0x58 65#define VR_NEXTTXDESC3 0x5C 66#define VR_CURRXDMA 0x60 /* current RX DMA address */ 67#define VR_CURTXDMA 0x64 /* current TX DMA address */ 68#define VR_TALLYCNT 0x68 /* tally counter test register */ 69#define VR_PHYADDR 0x6C 70#define VR_MIISTAT 0x6D 71#define VR_BCR0 0x6E 72#define VR_BCR1 0x6F 73#define VR_MIICMD 0x70 74#define VR_MIIADDR 0x71 75#define VR_MIIDATA 0x72 76#define VR_EECSR 0x74 77#define VR_TEST 0x75 78#define VR_GPIO 0x76 79#define VR_CONFIG 0x78 80#define VR_MPA_CNT 0x7C 81#define VR_CRC_CNT 0x7E 82 83/* 84 * RX config bits. 85 */ 86#define VR_RXCFG_RX_ERRPKTS 0x01 87#define VR_RXCFG_RX_RUNT 0x02 88#define VR_RXCFG_RX_MULTI 0x04 89#define VR_RXCFG_RX_BROAD 0x08 90#define VR_RXCFG_RX_PROMISC 0x10 91#define VR_RXCFG_RX_THRESH 0xE0 92 93#define VR_RXTHRESH_32BYTES 0x00 94#define VR_RXTHRESH_64BYTES 0x20 95#define VR_RXTHRESH_128BYTES 0x40 96#define VR_RXTHRESH_256BYTES 0x60 97#define VR_RXTHRESH_512BYTES 0x80 98#define VR_RXTHRESH_768BYTES 0xA0 99#define VR_RXTHRESH_1024BYTES 0xC0 100#define VR_RXTHRESH_STORENFWD 0xE0 101 102/* 103 * TX config bits. 104 */ 105#define VR_TXCFG_RSVD0 0x01 106#define VR_TXCFG_LOOPBKMODE 0x06 107#define VR_TXCFG_BACKOFF 0x08 108#define VR_TXCFG_RSVD1 0x10 109#define VR_TXCFG_TX_THRESH 0xE0 110 111#define VR_TXTHRESH_32BYTES 0x00 112#define VR_TXTHRESH_64BYTES 0x20 113#define VR_TXTHRESH_128BYTES 0x40 114#define VR_TXTHRESH_256BYTES 0x60 115#define VR_TXTHRESH_512BYTES 0x80 116#define VR_TXTHRESH_768BYTES 0xA0 117#define VR_TXTHRESH_1024BYTES 0xC0 118#define VR_TXTHRESH_STORENFWD 0xE0 119 120/* 121 * Command register bits. 122 */ 123#define VR_CMD_INIT 0x0001 124#define VR_CMD_START 0x0002 125#define VR_CMD_STOP 0x0004 126#define VR_CMD_RX_ON 0x0008 127#define VR_CMD_TX_ON 0x0010 128#define VR_CMD_TX_GO 0x0020 129#define VR_CMD_RX_GO 0x0040 130#define VR_CMD_RSVD 0x0080 131#define VR_CMD_RX_EARLY 0x0100 132#define VR_CMD_TX_EARLY 0x0200 133#define VR_CMD_FULLDUPLEX 0x0400 134#define VR_CMD_TX_NOPOLL 0x0800 135 136#define VR_CMD_RESET 0x8000 137 138/* 139 * Interrupt status bits. 140 */ 141#define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 142#define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 143#define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 144#define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 145#define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 146#define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 147#define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 148#define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 149#define VR_ISR_RX_EARLY 0x0100 /* rx early */ 150#define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 151#define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 152#define VR_ISR_RX_DROPPED 0x0800 153#define VR_ISR_RX_NOBUF2 0x1000 154#define VR_ISR_TX_ABRT2 0x2000 155#define VR_ISR_LINKSTAT2 0x4000 156#define VR_ISR_MAGICPACKET 0x8000 157 158/* 159 * Interrupt mask bits. 160 */ 161#define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 162#define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 163#define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 164#define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 165#define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 166#define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 167#define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 168#define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 169#define VR_IMR_RX_EARLY 0x0100 /* rx early */ 170#define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 171#define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 172#define VR_IMR_RX_DROPPED 0x0800 173#define VR_IMR_RX_NOBUF2 0x1000 174#define VR_IMR_TX_ABRT2 0x2000 175#define VR_IMR_LINKSTAT2 0x4000 176#define VR_IMR_MAGICPACKET 0x8000 177 178#define VR_INTRS \ 179 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 180 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 181 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 182 183/* 184 * MII status register. 185 */ 186 187#define VR_MIISTAT_SPEED 0x01 188#define VR_MIISTAT_LINKFAULT 0x02 189#define VR_MIISTAT_MGTREADERR 0x04 190#define VR_MIISTAT_MIIERR 0x08 191#define VR_MIISTAT_PHYOPT 0x10 192#define VR_MIISTAT_MDC_SPEED 0x20 193#define VR_MIISTAT_RSVD 0x40 194#define VR_MIISTAT_GPIO1POLL 0x80 195 196/* 197 * MII command register bits. 198 */ 199#define VR_MIICMD_CLK 0x01 200#define VR_MIICMD_DATAOUT 0x02 201#define VR_MIICMD_DATAIN 0x04 202#define VR_MIICMD_DIR 0x08 203#define VR_MIICMD_DIRECTPGM 0x10 204#define VR_MIICMD_WRITE_ENB 0x20 205#define VR_MIICMD_READ_ENB 0x40 206#define VR_MIICMD_AUTOPOLL 0x80 207 208/* 209 * EEPROM control bits. 210 */ 211#define VR_EECSR_DATAIN 0x01 /* data out */ 212#define VR_EECSR_DATAOUT 0x02 /* data in */ 213#define VR_EECSR_CLK 0x04 /* clock */ 214#define VR_EECSR_CS 0x08 /* chip select */ 215#define VR_EECSR_DPM 0x10 216#define VR_EECSR_LOAD 0x20 217#define VR_EECSR_EMBP 0x40 218#define VR_EECSR_EEPR 0x80 219 220#define VR_EECMD_WRITE 0x140 221#define VR_EECMD_READ 0x180 222#define VR_EECMD_ERASE 0x1c0 223 224/* 225 * Test register bits. 226 */ 227#define VR_TEST_TEST0 0x01 228#define VR_TEST_TEST1 0x02 229#define VR_TEST_TEST2 0x04 230#define VR_TEST_TSTUD 0x08 231#define VR_TEST_TSTOV 0x10 232#define VR_TEST_BKOFF 0x20 233#define VR_TEST_FCOL 0x40 234#define VR_TEST_HBDES 0x80 235 236/* 237 * Config register bits. 238 */ 239#define VR_CFG_GPIO2OUTENB 0x00000001 240#define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 241#define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 242#define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 243#define VR_CFG_MIIOPT 0x00000010 244#define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 245#define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 246#define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 247#define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 248#define VR_CFG_MRREADWAIT 0x00000200 249#define VR_CFG_MRWRITEWAIT 0x00000400 250#define VR_CFG_RX_ARB 0x00000800 251#define VR_CFG_TX_ARB 0x00001000 252#define VR_CFG_READMULTI 0x00002000 253#define VR_CFG_TX_PACE 0x00004000 254#define VR_CFG_TX_QDIS 0x00008000 255#define VR_CFG_ROMSEL0 0x00010000 256#define VR_CFG_ROMSEL1 0x00020000 257#define VR_CFG_ROMSEL2 0x00040000 258#define VR_CFG_ROMTIMESEL 0x00080000 259#define VR_CFG_RSVD0 0x00100000 260#define VR_CFG_ROMDLY 0x00200000 261#define VR_CFG_ROMOPT 0x00400000 262#define VR_CFG_RSVD1 0x00800000 263#define VR_CFG_BACKOFFOPT 0x01000000 264#define VR_CFG_BACKOFFMOD 0x02000000 265#define VR_CFG_CAPEFFECT 0x04000000 266#define VR_CFG_BACKOFFRAND 0x08000000 267#define VR_CFG_MAGICKPACKET 0x10000000 268#define VR_CFG_PCIREADLINE 0x20000000 269#define VR_CFG_DIAG 0x40000000 270#define VR_CFG_GPIOEN 0x80000000 271 272/* 273 * Rhine TX/RX list structure. 274 */ 275 276struct vr_desc { 277 u_int32_t vr_status; 278 u_int32_t vr_ctl; 279 u_int32_t vr_ptr1; 280 u_int32_t vr_ptr2; 281}; 282 283#define vr_data vr_ptr1 284#define vr_next vr_ptr2 285 286 287#define VR_RXSTAT_RXERR 0x00000001 288#define VR_RXSTAT_CRCERR 0x00000002 289#define VR_RXSTAT_FRAMEALIGNERR 0x00000004 290#define VR_RXSTAT_FIFOOFLOW 0x00000008 291#define VR_RXSTAT_GIANT 0x00000010 292#define VR_RXSTAT_RUNT 0x00000020 293#define VR_RXSTAT_BUSERR 0x00000040 294#define VR_RXSTAT_BUFFERR 0x00000080 295#define VR_RXSTAT_LASTFRAG 0x00000100 296#define VR_RXSTAT_FIRSTFRAG 0x00000200 297#define VR_RXSTAT_RLINK 0x00000400 298#define VR_RXSTAT_RX_PHYS 0x00000800 299#define VR_RXSTAT_RX_BROAD 0x00001000 300#define VR_RXSTAT_RX_MULTI 0x00002000 301#define VR_RXSTAT_RX_OK 0x00004000 302#define VR_RXSTAT_RXLEN 0x07FF0000 303#define VR_RXSTAT_RXLEN_EXT 0x78000000 304#define VR_RXSTAT_OWN 0x80000000 305 306#define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 307#define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 308 309#define VR_RXCTL_BUFLEN 0x000007FF 310#define VR_RXCTL_BUFLEN_EXT 0x00007800 311#define VR_RXCTL_CHAIN 0x00008000 312#define VR_RXCTL_RX_INTR 0x00800000 313 314#define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 315 316#define VR_TXSTAT_DEFER 0x00000001 317#define VR_TXSTAT_UNDERRUN 0x00000002 318#define VR_TXSTAT_COLLCNT 0x00000078 319#define VR_TXSTAT_SQE 0x00000080 320#define VR_TXSTAT_ABRT 0x00000100 321#define VR_TXSTAT_LATECOLL 0x00000200 322#define VR_TXSTAT_CARRLOST 0x00000400 323#define VR_TXSTAT_BUSERR 0x00002000 324#define VR_TXSTAT_JABTIMEO 0x00004000 325#define VR_TXSTAT_ERRSUM 0x00008000 326#define VR_TXSTAT_OWN 0x80000000 327 328#define VR_TXCTL_BUFLEN 0x000007FF 329#define VR_TXCTL_BUFLEN_EXT 0x00007800 330#define VR_TXCTL_TLINK 0x00008000 331#define VR_TXCTL_FIRSTFRAG 0x00200000 332#define VR_TXCTL_LASTFRAG 0x00400000 333#define VR_TXCTL_FINT 0x00800000 334 335 336#define VR_MAXFRAGS 16 337#define VR_RX_LIST_CNT 64 338#define VR_TX_LIST_CNT 64 339#define VR_MIN_FRAMELEN 60 340#define VR_FRAMELEN 1536 341#define VR_RXLEN 1520 342 343#define VR_TXOWN(x) x->vr_ptr->vr_status 344 345struct vr_list_data { 346 struct vr_desc vr_rx_list[VR_RX_LIST_CNT]; 347 struct vr_desc vr_tx_list[VR_TX_LIST_CNT]; 348}; 349 350struct vr_chain { 351 struct vr_desc *vr_ptr; 352 struct mbuf *vr_mbuf; 353 struct vr_chain *vr_nextdesc; 354}; 355 356struct vr_chain_onefrag { 357 struct vr_desc *vr_ptr; 358 struct mbuf *vr_mbuf; 359 struct vr_chain_onefrag *vr_nextdesc; 360}; 361 362struct vr_chain_data { 363 struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT]; 364 struct vr_chain vr_tx_chain[VR_TX_LIST_CNT]; 365 366 struct vr_chain_onefrag *vr_rx_head; 367 368 struct vr_chain *vr_tx_head; 369 struct vr_chain *vr_tx_tail; 370 struct vr_chain *vr_tx_free; 371}; 372 373struct vr_type { 374 u_int16_t vr_vid; 375 u_int16_t vr_did; 376 char *vr_name; 377}; 378 379struct vr_mii_frame { 380 u_int8_t mii_stdelim; 381 u_int8_t mii_opcode; 382 u_int8_t mii_phyaddr; 383 u_int8_t mii_regaddr; 384 u_int8_t mii_turnaround; 385 u_int16_t mii_data; 386}; 387 388/* 389 * MII constants 390 */ 391#define VR_MII_STARTDELIM 0x01 392#define VR_MII_READOP 0x02 393#define VR_MII_WRITEOP 0x01 394#define VR_MII_TURNAROUND 0x02 395 396#define VR_FLAG_FORCEDELAY 1 397#define VR_FLAG_SCHEDDELAY 2 398#define VR_FLAG_DELAYTIMEO 3 399 400struct vr_softc { 401 struct arpcom arpcom; /* interface info */ 402 struct ifmedia ifmedia; /* media info */ 403 bus_space_handle_t vr_bhandle; /* bus space handle */ 404 bus_space_tag_t vr_btag; /* bus space tag */ 405 struct vr_type *vr_info; /* Rhine adapter info */ 406 struct vr_type *vr_pinfo; /* phy info */ 407 u_int8_t vr_unit; /* interface number */ 408 u_int8_t vr_type; 409 u_int8_t vr_phy_addr; /* PHY address */ 410 u_int8_t vr_tx_pend; /* TX pending */ 411 u_int8_t vr_want_auto; 412 u_int8_t vr_autoneg; 413 caddr_t vr_ldata_ptr; 414 struct vr_list_data *vr_ldata; 415 struct vr_chain_data vr_cdata; 416}; 417 418/* 419 * register space access macros 420 */ 421#define CSR_WRITE_4(sc, reg, val) \ 422 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val) 423#define CSR_WRITE_2(sc, reg, val) \ 424 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val) 425#define CSR_WRITE_1(sc, reg, val) \ 426 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val) 427 428#define CSR_READ_4(sc, reg) \ 429 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg) 430#define CSR_READ_2(sc, reg) \ 431 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg) 432#define CSR_READ_1(sc, reg) \ 433 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg) 434 435#define VR_TIMEOUT 1000 436 437/* 438 * General constants that are fun to know. 439 * 440 * VIA vendor ID 441 */ 442#define VIA_VENDORID 0x1106 443 444/* 445 * VIA Rhine device IDs. 446 */ 447#define VIA_DEVICEID_RHINE 0x3043 448#define VIA_DEVICEID_RHINE_II 0x6100 449 450 451/* 452 * Texas Instruments PHY identifiers 453 */ 454#define TI_PHY_VENDORID 0x4000 455#define TI_PHY_10BT 0x501F 456#define TI_PHY_100VGPMI 0x502F 457 458/* 459 * These ID values are for the NS DP83840A 10/100 PHY 460 */ 461#define NS_PHY_VENDORID 0x2000 462#define NS_PHY_83840A 0x5C0F 463 464/* 465 * Level 1 10/100 PHY 466 */ 467#define LEVEL1_PHY_VENDORID 0x7810 468#define LEVEL1_PHY_LXT970 0x000F 469 470/* 471 * Intel 82555 10/100 PHY 472 */ 473#define INTEL_PHY_VENDORID 0x0A28 474#define INTEL_PHY_82555 0x015F 475 476/* 477 * SEEQ 80220 10/100 PHY 478 */ 479#define SEEQ_PHY_VENDORID 0x0016 480#define SEEQ_PHY_80220 0xF83F 481 482 483/* 484 * PCI low memory base and low I/O base register, and 485 * other PCI registers. 486 */ 487 488#define VR_PCI_VENDOR_ID 0x00 489#define VR_PCI_DEVICE_ID 0x02 490#define VR_PCI_COMMAND 0x04 491#define VR_PCI_STATUS 0x06 492#define VR_PCI_CLASSCODE 0x09 493#define VR_PCI_LATENCY_TIMER 0x0D 494#define VR_PCI_HEADER_TYPE 0x0E 495#define VR_PCI_LOIO 0x10 496#define VR_PCI_LOMEM 0x14 497#define VR_PCI_BIOSROM 0x30 498#define VR_PCI_INTLINE 0x3C 499#define VR_PCI_INTPIN 0x3D 500#define VR_PCI_MINGNT 0x3E 501#define VR_PCI_MINLAT 0x0F 502#define VR_PCI_RESETOPT 0x48 503#define VR_PCI_EEPROM_DATA 0x4C 504 505/* power management registers */ 506#define VR_PCI_CAPID 0xDC /* 8 bits */ 507#define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 508#define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 509#define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 510 511#define VR_PSTATE_MASK 0x0003 512#define VR_PSTATE_D0 0x0000 513#define VR_PSTATE_D1 0x0002 514#define VR_PSTATE_D2 0x0002 515#define VR_PSTATE_D3 0x0003 516#define VR_PME_EN 0x0010 517#define VR_PME_STATUS 0x8000 518 519#define PHY_UNKNOWN 6 520 521#define VR_PHYADDR_MIN 0x00 522#define VR_PHYADDR_MAX 0x1F 523 524#define PHY_BMCR 0x00 525#define PHY_BMSR 0x01 526#define PHY_VENID 0x02 527#define PHY_DEVID 0x03 528#define PHY_ANAR 0x04 529#define PHY_LPAR 0x05 530#define PHY_ANEXP 0x06 531 532#define PHY_ANAR_NEXTPAGE 0x8000 533#define PHY_ANAR_RSVD0 0x4000 534#define PHY_ANAR_TLRFLT 0x2000 535#define PHY_ANAR_RSVD1 0x1000 536#define PHY_ANAR_RSVD2 0x0800 537#define PHY_ANAR_RSVD3 0x0400 538#define PHY_ANAR_100BT4 0x0200 539#define PHY_ANAR_100BTXFULL 0x0100 540#define PHY_ANAR_100BTXHALF 0x0080 541#define PHY_ANAR_10BTFULL 0x0040 542#define PHY_ANAR_10BTHALF 0x0020 543#define PHY_ANAR_PROTO4 0x0010 544#define PHY_ANAR_PROTO3 0x0008 545#define PHY_ANAR_PROTO2 0x0004 546#define PHY_ANAR_PROTO1 0x0002 547#define PHY_ANAR_PROTO0 0x0001 548 549/* 550 * These are the register definitions for the PHY (physical layer 551 * interface chip). 552 */ 553/* 554 * PHY BMCR Basic Mode Control Register 555 */ 556#define PHY_BMCR_RESET 0x8000 557#define PHY_BMCR_LOOPBK 0x4000 558#define PHY_BMCR_SPEEDSEL 0x2000 559#define PHY_BMCR_AUTONEGENBL 0x1000 560#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 561#define PHY_BMCR_ISOLATE 0x0400 562#define PHY_BMCR_AUTONEGRSTR 0x0200 563#define PHY_BMCR_DUPLEX 0x0100 564#define PHY_BMCR_COLLTEST 0x0080 565#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 566#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 567#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 568#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 569#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 570#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 571#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 572/* 573 * RESET: 1 == software reset, 0 == normal operation 574 * Resets status and control registers to default values. 575 * Relatches all hardware config values. 576 * 577 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 578 * 579 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 580 * Link speed is selected byt his bit or if auto-negotiation if bit 581 * 12 (AUTONEGENBL) is set (in which case the value of this register 582 * is ignored). 583 * 584 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 585 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 586 * determine speed and mode. Should be cleared and then set if PHY configured 587 * for no autoneg on startup. 588 * 589 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 590 * 591 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 592 * 593 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 594 * 595 * COLLTEST: 1 == collision test enabled, 0 == normal operation 596 */ 597 598/* 599 * PHY, BMSR Basic Mode Status Register 600 */ 601#define PHY_BMSR_100BT4 0x8000 602#define PHY_BMSR_100BTXFULL 0x4000 603#define PHY_BMSR_100BTXHALF 0x2000 604#define PHY_BMSR_10BTFULL 0x1000 605#define PHY_BMSR_10BTHALF 0x0800 606#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 607#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 608#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 609#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 610#define PHY_BMSR_MFPRESUP 0x0040 611#define PHY_BMSR_AUTONEGCOMP 0x0020 612#define PHY_BMSR_REMFAULT 0x0010 613#define PHY_BMSR_CANAUTONEG 0x0008 614#define PHY_BMSR_LINKSTAT 0x0004 615#define PHY_BMSR_JABBER 0x0002 616#define PHY_BMSR_EXTENDED 0x0001 617