1139823Simp/* $NetBSD: if_txpreg.h,v 1.11 2020/03/10 00:24:08 thorpej Exp $ */ 21541Srgrimes 31541Srgrimes/* 41541Srgrimes * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 51541Srgrimes * All rights reserved. 61541Srgrimes * 71541Srgrimes * Redistribution and use in source and binary forms, with or without 81541Srgrimes * modification, are permitted provided that the following conditions 91541Srgrimes * are met: 101541Srgrimes * 1. Redistributions of source code must retain the above copyright 111541Srgrimes * notice, this list of conditions and the following disclaimer. 121541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 131541Srgrimes * notice, this list of conditions and the following disclaimer in the 141541Srgrimes * documentation and/or other materials provided with the distribution. 151541Srgrimes * 161541Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 171541Srgrimes * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 181541Srgrimes * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 191541Srgrimes * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 201541Srgrimes * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 211541Srgrimes * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 221541Srgrimes * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231541Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 241541Srgrimes * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 251541Srgrimes * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 261541Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 271541Srgrimes */ 281541Srgrimes 2910942Swollman#ifndef _DEV_PCI_IF_TXPREG_H_ 3050477Speter#define _DEV_PCI_IF_TXPREG_H_ 311541Srgrimes 321541Srgrimes#define TXP_PCI_LOMEM 0x14 /* pci conf, memory map BAR */ 332169Spaul#define TXP_PCI_LOIO 0x10 /* pci conf, IO map BAR */ 3418940Sbde 352169Spaul/* 3678064Sume * Typhoon registers. 3778064Sume */ 381541Srgrimes#define TXP_SRR 0x00 /* soft reset register */ 391541Srgrimes#define TXP_ISR 0x04 /* interrupt status register */ 401541Srgrimes#define TXP_IER 0x08 /* interrupt enable register */ 411541Srgrimes#define TXP_IMR 0x0c /* interrupt mask register */ 4238513Sdfr#define TXP_SIR 0x10 /* self interrupt register */ 431541Srgrimes#define TXP_H2A_7 0x14 /* host->arm comm 7 */ 4419183Sfenner#define TXP_H2A_6 0x18 /* host->arm comm 6 */ 451541Srgrimes#define TXP_H2A_5 0x1c /* host->arm comm 5 */ 461541Srgrimes#define TXP_H2A_4 0x20 /* host->arm comm 4 */ 471541Srgrimes#define TXP_H2A_3 0x24 /* host->arm comm 3 */ 481541Srgrimes#define TXP_H2A_2 0x28 /* host->arm comm 2 */ 49100419Srwatson#define TXP_H2A_1 0x2c /* host->arm comm 1 */ 501541Srgrimes#define TXP_H2A_0 0x30 /* host->arm comm 0 */ 511541Srgrimes#define TXP_A2H_3 0x34 /* arm->host comm 3 */ 521541Srgrimes#define TXP_A2H_2 0x38 /* arm->host comm 2 */ 531541Srgrimes#define TXP_A2H_1 0x3c /* arm->host comm 1 */ 541541Srgrimes#define TXP_A2H_0 0x40 /* arm->host comm 0 */ 551541Srgrimes 561541Srgrimes/* 5774362Sphk * interrupt bits (IMR, ISR, IER) 581541Srgrimes */ 591541Srgrimes#define TXP_INT_RESERVED 0xffff0000 601541Srgrimes#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 6138513Sdfr#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 621541Srgrimes#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 63111244Ssilby#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 64168365Sandre#define TXP_INT_SELF 0x00000800 /* self interrupt */ 651541Srgrimes#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 66100419Srwatson#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 671541Srgrimes#define TXP_INT_DMA3 0x00000100 /* dma3 done */ 681541Srgrimes#define TXP_INT_DMA2 0x00000080 /* dma2 done */ 69152608Sandre#define TXP_INT_DMA1 0x00000040 /* dma1 done */ 70152608Sandre#define TXP_INT_DMA0 0x00000020 /* dma0 done */ 71152608Sandre#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 72152608Sandre#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 73152608Sandre#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 74152608Sandre#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 75152608Sandre#define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 76152608Sandre 77152608Sandre/* 78152608Sandre * soft reset register (SRR) 79152608Sandre */ 80152608Sandre#define TXP_SRR_ALL 0x0000007f /* full reset */ 81152608Sandre 821541Srgrimes/* 831541Srgrimes * Typhoon boot commands. 84170613Sbms */ 851541Srgrimes#define TXP_BOOTCMD_NULL 0x00 861541Srgrimes#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 871541Srgrimes#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 8878064Sume#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 89158563Sbms#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 901541Srgrimes 911541Srgrimes/* 921541Srgrimes * Typhoon runtime commands. 93158563Sbms */ 94158563Sbms#define TXP_CMD_GLOBAL_RESET 0x00 95170613Sbms#define TXP_CMD_TX_ENABLE 0x01 96228969Sjhb#define TXP_CMD_TX_DISABLE 0x02 971541Srgrimes#define TXP_CMD_RX_ENABLE 0x03 981541Srgrimes#define TXP_CMD_RX_DISABLE 0x04 991541Srgrimes#define TXP_CMD_RX_FILTER_WRITE 0x05 1001541Srgrimes#define TXP_CMD_RX_FILTER_READ 0x06 1011541Srgrimes#define TXP_CMD_READ_STATISTICS 0x07 1021541Srgrimes#define TXP_CMD_CYCLE_STATISTICS 0x08 1031541Srgrimes#define TXP_CMD_CLEAR_STATISTICS 0x09 1041541Srgrimes#define TXP_CMD_MEMORY_READ 0x0a 1051541Srgrimes#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 1061541Srgrimes#define TXP_CMD_VARIABLE_SECTION_READ 0x0c 1071541Srgrimes#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 1081541Srgrimes#define TXP_CMD_STATIC_SECTION_READ 0x0e 1091541Srgrimes#define TXP_CMD_STATIC_SECTION_WRITE 0x0f 11036192Sdg#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 1111541Srgrimes#define TXP_CMD_NVRAM_PAGE_READ 0x11 1121541Srgrimes#define TXP_CMD_NVRAM_PAGE_WRITE 0x12 1131541Srgrimes#define TXP_CMD_XCVR_SELECT 0x13 1141541Srgrimes#define TXP_CMD_TEST_MUX 0x14 1151541Srgrimes#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 1161541Srgrimes#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 1171541Srgrimes#define TXP_CMD_MAC_CONTROL_READ 0x17 11813765Smpp#define TXP_CMD_MAC_CONTROL_WRITE 0x18 1191541Srgrimes#define TXP_CMD_MAX_PKT_SIZE_READ 0x19 1201541Srgrimes#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 1211541Srgrimes#define TXP_CMD_MEDIA_STATUS_READ 0x1b 1221541Srgrimes#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 1231541Srgrimes#define TXP_CMD_NETWORK_DIAGS_READ 0x1d 1241541Srgrimes#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 12519183Sfenner#define TXP_CMD_PHY_MGMT_READ 0x1f 12621932Swollman#define TXP_CMD_PHY_MGMT_WRITE 0x20 12752904Sshin#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 12878064Sume#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 1291541Srgrimes#define TXP_CMD_GOTO_SLEEP 0x23 1301541Srgrimes#define TXP_CMD_FIREWALL_CONTROL 0x24 13155205Speter#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 13237625Sbde#define TXP_CMD_STATION_ADDRESS_WRITE 0x26 133195699Srwatson#define TXP_CMD_STATION_ADDRESS_READ 0x27 134195699Srwatson#define TXP_CMD_STATION_MASK_WRITE 0x28 135196039Srwatson#define TXP_CMD_STATION_MASK_READ 0x29 136196039Srwatson#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 137196039Srwatson#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 138196039Srwatson#define TXP_CMD_VLAN_MASK_READ 0x2c 139190951Srwatson#define TXP_CMD_VLAN_MASK_WRITE 0x2d 140190951Srwatson#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 141190951Srwatson#define TXP_CMD_BCAST_THROTTLE_READ 0x2f 142190951Srwatson#define TXP_CMD_DHCP_PREVENT_WRITE 0x30 143190951Srwatson#define TXP_CMD_DHCP_PREVENT_READ 0x31 144196039Srwatson#define TXP_CMD_RECV_BUFFER_CONTROL 0x32 145196039Srwatson#define TXP_CMD_SOFTWARE_RESET 0x33 146196039Srwatson#define TXP_CMD_CREATE_SA 0x34 147196039Srwatson#define TXP_CMD_DELETE_SA 0x35 148196039Srwatson#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 149196039Srwatson#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 150196039Srwatson#define TXP_CMD_RANDOM_NUMBER_READ 0x38 151196039Srwatson#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 152196039Srwatson#define TXP_CMD_MATRIX_DETAIL_READ 0x3a 153196039Srwatson#define TXP_CMD_FILTER_ARRAY_READ 0x3b 154170613Sbms#define TXP_CMD_FILTER_DETAIL_READ 0x3c 155170613Sbms#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 156170613Sbms#define TXP_CMD_FILTER_TCL_WRITE 0x3e 157170613Sbms#define TXP_CMD_FILTER_TBL_READ 0x3f 158170613Sbms#define TXP_CMD_VERSIONS_READ 0x43 159168365Sandre#define TXP_CMD_FILTER_DEFINE 0x45 160168365Sandre#define TXP_CMD_ADD_WAKEUP_PKT 0x46 1611541Srgrimes#define TXP_CMD_ADD_SLEEP_PKT 0x47 162168365Sandre#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 163168365Sandre#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 164168365Sandre#define TXP_CMD_GET_IP_ADDRESS 0x4a 165126239Smlaier#define TXP_CMD_READ_PCI_REG 0x4c 166126239Smlaier#define TXP_CMD_WRITE_PCI_REG 0x4d 167147744Sthompsa#define TXP_CMD_OFFLOAD_READ 0x4e 168147744Sthompsa#define TXP_CMD_OFFLOAD_WRITE 0x4f 169147744Sthompsa#define TXP_CMD_HELLO_RESPONSE 0x57 170147744Sthompsa#define TXP_CMD_ENABLE_RX_FILTER 0x58 171147744Sthompsa#define TXP_CMD_RX_FILTER_CAPABILITY 0x59 172147744Sthompsa#define TXP_CMD_HALT 0x5d 17338482Swollman#define TXP_CMD_READ_IPSEC_INFO 0x54 17419669Sbde#define TXP_CMD_GET_IPSEC_ENABLE 0x67 17518940Sbde#define TXP_CMD_INVALID 0xffff 17638482Swollman 17718940Sbde#define TXP_FRAGMENT 0x0000 178195699Srwatson#define TXP_TXFRAME 0x0001 179195699Srwatson#define TXP_COMMAND 0x0002 180195699Srwatson#define TXP_OPTION 0x0003 181195699Srwatson#define TXP_RECEIVE 0x0004 182122723Sandre#define TXP_RESPONSE 0x0005 183195699Srwatson 184122723Sandre#define TXP_TYPE_IPSEC 0x0000 185207369Sbz#define TXP_TYPE_TCPSEGMENT 0x0001 186195699Srwatson 187195699Srwatson#define TXP_PFLAG_NOCRC 0x0000 188207369Sbz#define TXP_PFLAG_IPCKSUM 0x0001 189207369Sbz#define TXP_PFLAG_TCPCKSUM 0x0002 190207369Sbz#define TXP_PFLAG_TCPSEGMENT 0x0004 191207369Sbz#define TXP_PFLAG_INSERTVLAN 0x0008 192193502Sluigi#define TXP_PFLAG_IPSEC 0x0010 193195727Srwatson#define TXP_PFLAG_PRIORITY 0x0020 194195727Srwatson#define TXP_PFLAG_UDPCKSUM 0x0040 195195727Srwatson#define TXP_PFLAG_PADFRAME 0x0080 196195727Srwatson 197195699Srwatson#define TXP_MISC_FIRSTDESC 0x0000 198195727Srwatson#define TXP_MISC_LASTDESC 0x0001 199195699Srwatson 200195727Srwatson#define TXP_ERR_INTERNAL 0x0000 201195727Srwatson#define TXP_ERR_FIFOUNDERRUN 0x0001 202207369Sbz#define TXP_ERR_BADSSD 0x0002 203195699Srwatson#define TXP_ERR_RUNT 0x0003 204170613Sbms#define TXP_ERR_CRC 0x0004 205170613Sbms#define TXP_ERR_OVERSIZE 0x0005 206170613Sbms#define TXP_ERR_ALIGNMENT 0x0006 207170613Sbms#define TXP_ERR_DRIBBLEBIT 0x0007 208168365Sandre 209168365Sandre#define TXP_PROTO_UNKNOWN 0x0000 210168365Sandre#define TXP_PROTO_IP 0x0001 211118622Shsu#define TXP_PROTO_IPX 0x0002 212168365Sandre#define TXP_PROTO_RESERVED 0x0003 213168365Sandre 214204140Sbz#define TXP_STAT_PROTO 0x0001 215204140Sbz#define TXP_STAT_VLAN 0x0002 216204140Sbz#define TXP_STAT_IPFRAGMENT 0x0004 217168365Sandre#define TXP_STAT_IPSEC 0x0008 218168365Sandre#define TXP_STAT_IPCKSUMBAD 0x0010 219168365Sandre#define TXP_STAT_TCPCKSUMBAD 0x0020 220168365Sandre#define TXP_STAT_UDPCKSUMBAD 0x0040 221105194Ssam#define TXP_STAT_IPCKSUMGOOD 0x0080 222105194Ssam#define TXP_STAT_TCPCKSUMGOOD 0x0100 223212155Sbz#define TXP_STAT_UDPCKSUMGOOD 0x0200 224212155Sbz 225133920Sandrestruct txp_tx_desc { 226168365Sandre volatile u_int8_t tx_flags; /* type/descriptor flags */ 22787120Sru volatile u_int8_t tx_numdesc; /* number of descriptors */ 228178888Sjulian volatile u_int16_t tx_totlen; /* total packet length */ 229168365Sandre volatile u_int32_t tx_addrlo; /* virt addr low word */ 230168365Sandre volatile u_int32_t tx_addrhi; /* virt addr high word */ 231168365Sandre volatile u_int32_t tx_pflags; /* processing flags */ 232133720Sdwmalone}; 23398663Sluigi#define TX_FLAGS_TYPE_M 0x07 /* type mask */ 23498663Sluigi#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 23598663Sluigi#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 236193731Szec#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 237193731Szec#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 238193731Szec#define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 23998663Sluigi#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 24098663Sluigi#define TX_FLAGS_RESP 0x40 /* response requested */ 24192723Salfred#define TX_FLAGS_VALID 0x80 /* valid descriptor */ 24292723Salfred 24392723Salfred#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 24492723Salfred#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 245106968Sluigi#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 246106968Sluigi#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 247106968Sluigi#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 2487083Swollman#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 249197952Sjulian#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 250197952Sjulian#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 251120386Ssam#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 25260765Sjlemon#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 25360765Sjlemon#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 254201735Sluigi#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 255201735Sluigi 256201735Sluigistruct txp_rx_desc { 257201735Sluigi volatile u_int8_t rx_flags; /* type/descriptor flags */ 258201735Sluigi volatile u_int8_t rx_numdesc; /* number of descriptors */ 259201735Sluigi volatile u_int16_t rx_len; /* frame length */ 260201735Sluigi volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */ 261201735Sluigi volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */ 262201735Sluigi volatile u_int32_t rx_stat; /* status */ 263201735Sluigi volatile u_int16_t rx_filter; /* filter status */ 264201735Sluigi volatile u_int16_t rx_hash; /* hash status */ 265201735Sluigi volatile u_int32_t rx_vlan; /* vlan tag/priority */ 266201735Sluigi}; 267201735Sluigi 268201735Sluigi/* txp_rx_desc.rx_flags */ 269201735Sluigi#define RX_FLAGS_TYPE_M 0x07 /* type mask */ 270201735Sluigi#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 271201735Sluigi#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 272201735Sluigi#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 273201735Sluigi#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 274201735Sluigi#define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 275201735Sluigi#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 276201735Sluigi#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 277201735Sluigi#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 278201735Sluigi#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 279201735Sluigi#define RX_FLAGS_ERROR 0x40 /* error in packet */ 280201735Sluigi 281201735Sluigi/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 282201735Sluigi#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 283201735Sluigi#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 284201735Sluigi#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 285201735Sluigi#define RX_ERROR_RUNT 0x00000003 /* runt packet */ 286201735Sluigi#define RX_ERROR_CRC 0x00000004 /* bad crc */ 287201735Sluigi#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 288201735Sluigi#define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 289201735Sluigi#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 290223666Sae 291201735Sluigi/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 292193502Sluigi#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 293197952Sjulian#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 294197952Sjulian#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 295197952Sjulian#define RX_STAT_PROTO_IP 0x00000002 /* IP */ 296197952Sjulian#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 297197952Sjulian#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 298197952Sjulian#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 299197952Sjulian#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 300201735Sluigi#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 301201735Sluigi#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 302201735Sluigi#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 303201735Sluigi#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 304201735Sluigi#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 305201735Sluigi#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 306193502Sluigi 307201735Sluigi 308195699Srwatsonstruct txp_rxbuf_desc { 309195699Srwatson volatile u_int32_t rb_paddrlo; 310195727Srwatson volatile u_int32_t rb_paddrhi; 311195699Srwatson volatile u_int32_t rb_vaddrlo; 312195699Srwatson volatile u_int32_t rb_vaddrhi; 313195699Srwatson}; 31455205Speter 31517072Sjulian/* Extension descriptor */ 31637625Sbdestruct txp_ext_desc { 317 volatile u_int32_t ext_1; 318 volatile u_int32_t ext_2; 319 volatile u_int32_t ext_3; 320 volatile u_int32_t ext_4; 321}; 322 323struct txp_cmd_desc { 324 volatile u_int8_t cmd_flags; 325 volatile u_int8_t cmd_numdesc; 326 volatile u_int16_t cmd_id; 327 volatile u_int16_t cmd_seq; 328 volatile u_int16_t cmd_par1; 329 volatile u_int32_t cmd_par2; 330 volatile u_int32_t cmd_par3; 331}; 332#define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 333#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 334#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 335#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 336#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 337#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 338#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 339#define CMD_FLAGS_RESP 0x40 /* response requested */ 340#define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 341 342struct txp_rsp_desc { 343 volatile u_int8_t rsp_flags; 344 volatile u_int8_t rsp_numdesc; 345 volatile u_int16_t rsp_id; 346 volatile u_int16_t rsp_seq; 347 volatile u_int16_t rsp_par1; 348 volatile u_int32_t rsp_par2; 349 volatile u_int32_t rsp_par3; 350}; 351#define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 352#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 353#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 354#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 355#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 356#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 357#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 358#define RSP_FLAGS_ERROR 0x40 /* response error */ 359 360struct txp_frag_desc { 361 volatile u_int8_t frag_flags; /* type/descriptor flags */ 362 volatile u_int8_t frag_rsvd1; 363 volatile u_int16_t frag_len; /* bytes in this fragment */ 364 volatile u_int32_t frag_addrlo; /* phys addr low word */ 365 volatile u_int32_t frag_addrhi; /* phys addr high word */ 366 volatile u_int32_t frag_rsvd2; 367}; 368#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 369#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 370#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 371#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 372#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 373#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 374#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 375#define FRAG_FLAGS_VALID 0x80 /* valid descriptor */ 376 377struct txp_opt_desc { 378 u_int8_t opt_desctype:3, 379 opt_rsvd:1, 380 opt_type:4; 381 382 u_int8_t opt_num; 383 u_int16_t opt_dep1; 384 u_int32_t opt_dep2; 385 u_int32_t opt_dep3; 386 u_int32_t opt_dep4; 387}; 388 389struct txp_ipsec_desc { 390 u_int8_t ipsec_desctpe:3, 391 ipsec_rsvd:1, 392 ipsec_type:4; 393 394 u_int8_t ipsec_num; 395 u_int16_t ipsec_flags; 396 u_int16_t ipsec_ah1; 397 u_int16_t ipsec_esp1; 398 u_int16_t ipsec_ah2; 399 u_int16_t ipsec_esp2; 400 u_int32_t ipsec_rsvd1; 401}; 402 403struct txp_tcpseg_desc { 404 u_int8_t tcpseg_desctype:3, 405 tcpseg_rsvd:1, 406 tcpseg_type:4; 407 408 u_int8_t tcpseg_num; 409 410 u_int16_t tcpseg_mss:12, 411 tcpseg_misc:4; 412 413 u_int32_t tcpseg_respaddr; 414 u_int32_t tcpseg_txbytes; 415 u_int32_t tcpseg_lss; 416}; 417 418/* 419 * Transceiver types 420 */ 421#define TXP_XCVR_10_HDX 0 422#define TXP_XCVR_10_FDX 1 423#define TXP_XCVR_100_HDX 2 424#define TXP_XCVR_100_FDX 3 425#define TXP_XCVR_AUTO 4 426 427#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 428#define TXP_MEDIA_CD 0x0010 /* collision detection */ 429#define TXP_MEDIA_CS 0x0020 /* carrier sense */ 430#define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 431#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 432 433/* 434 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 435 */ 436#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 437#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 438#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 439#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 440#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 441 442/* multicast polynomial */ 443#define TXP_POLYNOMIAL 0x04c11db7 444 445/* 446 * boot record (pointers to rings) 447 */ 448struct txp_boot_record { 449 volatile u_int32_t br_hostvar_lo; /* host ring pointer */ 450 volatile u_int32_t br_hostvar_hi; 451 volatile u_int32_t br_txlopri_lo; /* tx low pri ring */ 452 volatile u_int32_t br_txlopri_hi; 453 volatile u_int32_t br_txlopri_siz; 454 volatile u_int32_t br_txhipri_lo; /* tx high pri ring */ 455 volatile u_int32_t br_txhipri_hi; 456 volatile u_int32_t br_txhipri_siz; 457 volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */ 458 volatile u_int32_t br_rxlopri_hi; 459 volatile u_int32_t br_rxlopri_siz; 460 volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */ 461 volatile u_int32_t br_rxbuf_hi; 462 volatile u_int32_t br_rxbuf_siz; 463 volatile u_int32_t br_cmd_lo; /* command ring */ 464 volatile u_int32_t br_cmd_hi; 465 volatile u_int32_t br_cmd_siz; 466 volatile u_int32_t br_resp_lo; /* response ring */ 467 volatile u_int32_t br_resp_hi; 468 volatile u_int32_t br_resp_siz; 469 volatile u_int32_t br_zero_lo; /* zero word */ 470 volatile u_int32_t br_zero_hi; 471 volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */ 472 volatile u_int32_t br_rxhipri_hi; 473 volatile u_int32_t br_rxhipri_siz; 474}; 475 476/* 477 * hostvar structure (shared with typhoon) 478 */ 479struct txp_hostvar { 480 volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */ 481 volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */ 482 volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */ 483 volatile u_int32_t hv_resp_read_idx; /* host->arm */ 484 volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */ 485 volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */ 486 volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */ 487 volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */ 488 volatile u_int32_t hv_cmd_read_idx; /* arm->host */ 489 volatile u_int32_t hv_resp_write_idx; /* arm->host */ 490 volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */ 491}; 492 493/* 494 * TYPHOON status register state (in TXP_A2H_0) 495 */ 496#define STAT_ROM_CODE 0x00000001 497#define STAT_ROM_EEPROM_LOAD 0x00000002 498#define STAT_WAITING_FOR_BOOT 0x00000007 499#define STAT_RUNNING 0x00000009 500#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 501#define STAT_WAITING_FOR_SEGMENT 0x00000010 502#define STAT_SLEEPING 0x00000011 503#define STAT_HALTED 0x00000014 504 505#define TX_ENTRIES 256 506#define RX_ENTRIES 128 507#define RXBUF_ENTRIES 256 508#define CMD_ENTRIES 32 509#define RSP_ENTRIES 32 510 511#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 512#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 513#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 514#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 515#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 516#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 517#define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 518#define OFFLOAD_FILTER 0x00000100 /* filter enable */ 519#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 520#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 521 522/* 523 * Macros for converting array indices to offsets within the descriptor 524 * arrays. The chip operates on offsets, but it's much easier for us 525 * to operate on indices. Assumes descriptor entries are 16 bytes. 526 */ 527#define TXP_IDX2OFFSET(idx) ((idx) << 4) 528#define TXP_OFFSET2IDX(off) ((off) >> 4) 529 530struct txp_dma_alloc { 531 void * dma_vaddr; 532 bus_dmamap_t dma_map; 533#define dma_paddr dma_map->dm_segs[0].ds_addr 534 bus_dma_segment_t dma_seg; 535 int dma_nseg; 536}; 537 538struct txp_cmd_ring { 539 struct txp_cmd_desc *base; 540 u_int32_t lastwrite; 541 u_int32_t size; 542}; 543 544struct txp_rsp_ring { 545 struct txp_rsp_desc *base; 546 u_int32_t lastwrite; 547 u_int32_t size; 548}; 549 550struct txp_tx_ring { 551 struct txp_tx_desc *r_desc; /* base address of descs */ 552 u_int32_t r_reg; /* register to activate */ 553 u_int32_t r_prod; /* producer */ 554 u_int32_t r_cons; /* consumer */ 555 u_int32_t r_cnt; /* # descs in use */ 556 volatile u_int32_t *r_off; /* hostvar index pointer */ 557}; 558 559struct txp_swdesc { 560 struct mbuf * sd_mbuf; 561 bus_dmamap_t sd_map; 562}; 563 564struct txp_rx_ring { 565 struct txp_rx_desc *r_desc; /* base address of descs */ 566 volatile u_int32_t *r_roff; /* hv read offset ptr */ 567 volatile u_int32_t *r_woff; /* hv write offset ptr */ 568}; 569 570struct txp_softc { 571 device_t sc_dev; /* base device */ 572 struct ethercom sc_arpcom; /* ethernet common */ 573 struct txp_hostvar *sc_hostvar; 574 struct txp_boot_record *sc_boot; 575 bus_space_handle_t sc_bh; /* bus handle (regs) */ 576 bus_space_tag_t sc_bt; /* bus tag (regs) */ 577 bus_dma_tag_t sc_dmat; /* dma tag */ 578 struct txp_cmd_ring sc_cmdring; 579 struct txp_rsp_ring sc_rspring; 580 struct txp_swdesc sc_txd[TX_ENTRIES]; 581 void * sc_ih; 582 struct callout sc_tick; 583 struct ifmedia sc_ifmedia; 584 struct txp_tx_ring sc_txhir, sc_txlor; 585 struct txp_rxbuf_desc *sc_rxbufs; 586 struct txp_rx_ring sc_rxhir, sc_rxlor; 587 struct txp_swdesc sc_rxd[RXBUF_ENTRIES]; 588 struct txp_swdesc *sc_rxd_pool[RXBUF_ENTRIES]; 589 unsigned int sc_txd_pool_ptr; 590 u_int16_t sc_xcvr; 591 u_int16_t sc_seq; 592 struct txp_dma_alloc sc_boot_dma, sc_host_dma, sc_zero_dma; 593 struct txp_dma_alloc sc_rxhiring_dma, sc_rxloring_dma; 594 struct txp_dma_alloc sc_txhiring_dma, sc_txloring_dma; 595 struct txp_dma_alloc sc_cmdring_dma, sc_rspring_dma; 596 struct txp_dma_alloc sc_rxbufring_dma; 597 int sc_cold; 598 u_int32_t sc_rx_capability, sc_tx_capability; 599 int sc_flags; 600#define TXP_USESUBSYSTEM 0x1 /* use PCI subsys reg for detail info */ 601#define TXP_SERVERVERSION 0x2 602#define TXP_FIBER 0x4 603}; 604 605#define TXP_DEVNAME(sc) ((sc)->sc_cold ? "" : device_xname((sc)->sc_dev)) 606 607struct txp_fw_file_header { 608 u_int8_t magicid[8]; /* TYPHOON\0 */ 609 u_int32_t version; 610 u_int32_t nsections; 611 u_int32_t addr; 612 u_int32_t hmac[5]; 613}; 614 615struct txp_fw_section_header { 616 u_int32_t nbytes; 617 u_int16_t cksum; 618 u_int16_t reserved; 619 u_int32_t addr; 620}; 621 622#define TXP_MAX_SEGLEN 0xffff 623#define TXP_MAX_PKTLEN 0x0800 624 625#define TXP_MAXTXSEGS 16 626 627#define WRITE_REG(sc,reg,val) \ 628 bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val) 629#define READ_REG(sc,reg) \ 630 bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg) 631 632#endif /* _DEV_PCI_IF_TXPREG_H_ */ 633