if_stgereg.h revision 1.7
1/* $NetBSD: if_stgereg.h,v 1.7 2019/12/26 15:23:11 msaitoh Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _DEV_PCI_IF_STGEREG_H_ 33#define _DEV_PCI_IF_STGEREG_H_ 34 35 36#include <net/if_ether.h> 37#include <sys/bus.h> 38 39/* 40 * Register description for the Sundance Tech. TC9021 10/100/1000 41 * Ethernet controller. 42 * 43 * Note that while DMA addresses are all in 64-bit fields, only 44 * the lower 40 bits of a DMA address are valid. 45 */ 46 47/* 48 * TC9021 buffer fragment descriptor. 49 */ 50struct stge_frag { 51 uint64_t frag_word0; /* address, length */ 52} __packed; 53 54#define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 55#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 56#define FRAG_LEN(x) (((uint64_t)(x)) << 48) 57#define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 58 59/* 60 * TC9021 Transmit Frame Descriptor. Note the number of fragments 61 * here is arbitrary, but we can't have any more than 15. 62 */ 63#define STGE_NTXFRAGS 12 64struct stge_tfd { 65 uint64_t tfd_next; /* next TFD in list */ 66 uint64_t tfd_control; /* control bits */ 67 /* the buffer fragments */ 68 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 69} __packed; 70 71#define TFD_FrameId(x) ((x) << 0) 72#define TFD_FrameId_MAX 0xffff 73#define TFD_WordAlign(x) ((x) << 16) 74#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 75#define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 76#define TFD_WordAlign_disable 1 /* disable alignment */ 77#define TFD_TCPChecksumEnable (1ULL << 18) 78#define TFD_UDPChecksumEnable (1ULL << 19) 79#define TFD_IPChecksumEnable (1ULL << 20) 80#define TFD_FcsAppendDisable (1ULL << 21) 81#define TFD_TxIndicate (1ULL << 22) 82#define TFD_TxDMAIndicate (1ULL << 23) 83#define TFD_FragCount(x) ((x) << 24) 84#define TFD_VLANTagInsert (1ULL << 28) 85#define TFD_TFDDone (1ULL << 31) 86#define TFD_VID(x) (((uint64_t)(x)) << 32) 87#define TFD_CFI (1ULL << 44) 88#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 89 90/* 91 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 92 * in it, and the chip tells us the beginning and end of the frame. 93 */ 94struct stge_rfd { 95 uint64_t rfd_next; /* next RFD in list */ 96 uint64_t rfd_status; /* status bits */ 97 struct stge_frag rfd_frag; /* the buffer */ 98} __packed; 99 100#define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 101#define RFD_RxFIFOOverrun (1ULL << 16) 102#define RFD_RxRuntFrame (1ULL << 17) 103#define RFD_RxAlignmentError (1ULL << 18) 104#define RFD_RxFCSError (1ULL << 19) 105#define RFD_RxOversizedFrame (1ULL << 20) 106#define RFD_RxLengthError (1ULL << 21) 107#define RFD_VLANDetected (1ULL << 22) 108#define RFD_TCPDetected (1ULL << 23) 109#define RFD_TCPError (1ULL << 24) 110#define RFD_UDPDetected (1ULL << 25) 111#define RFD_UDPError (1ULL << 26) 112#define RFD_IPDetected (1ULL << 27) 113#define RFD_IPError (1ULL << 28) 114#define RFD_FrameStart (1ULL << 29) 115#define RFD_FrameEnd (1ULL << 30) 116#define RFD_RFDDone (1ULL << 31) 117#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 118 119/* 120 * PCI configuration registers used by the TC9021. 121 */ 122 123#define STGE_PCI_IOBA (PCI_MAPREG_START + 0x00) 124#define STGE_PCI_MMBA (PCI_MAPREG_START + 0x04) 125 126/* 127 * EEPROM offsets. 128 */ 129#define STGE_EEPROM_ConfigParam 0x00 130#define STGE_EEPROM_AsicCtrl 0x01 131#define STGE_EEPROM_SubSystemVendorId 0x02 132#define STGE_EEPROM_SubSystemId 0x03 133#define STGE_EEPROM_StationAddress0 0x10 134#define STGE_EEPROM_StationAddress1 0x11 135#define STGE_EEPROM_StationAddress2 0x12 136 137/* 138 * The TC9021 register space. 139 */ 140 141#define STGE_DMACtrl 0x00 142#define DMAC_RxDMAComplete (1U << 3) 143#define DMAC_RxDMAPollNow (1U << 4) 144#define DMAC_TxDMAComplete (1U << 11) 145#define DMAC_TxDMAPollNow (1U << 12) 146#define DMAC_TxDMAInProg (1U << 15) 147#define DMAC_RxEarlyDisable (1U << 16) 148#define DMAC_MWIDisable (1U << 18) 149#define DMAC_TxWiteBackDisable (1U << 19) 150#define DMAC_TxBurstLimit(x) ((x) << 20) 151#define DMAC_TargetAbort (1U << 30) 152#define DMAC_MasterAbort (1U << 31) 153 154#define STGE_RxDMAStatus 0x08 155 156#define STGE_TFDListPtrLo 0x10 157 158#define STGE_TFDListPtrHi 0x14 159 160#define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 161 162#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 163 164#define STGE_TxDMAPollPeriod 0x1a /* 8-bit */ 165 166#define STGE_RFDListPtrLo 0x1c 167 168#define STGE_RFDListPtrHi 0x20 169 170#define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 171 172#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 173 174#define STGE_RxDMAPollPeriod 0x26 /* 8-bit */ 175 176#define STGE_RxDMAIntCtrl 0x28 177#define RDIC_RxFrameCount(x) ((x) & 0xff) 178#define RDIC_PriorityThresh(x) ((x) << 10) 179#define RDIC_RxDMAWaitTime(x) ((x) << 16) 180 181#define STGE_DebugCtrl 0x2c /* 16-bit */ 182#define DC_GPIO0Ctrl (1U << 0) 183#define DC_GPIO1Ctrl (1U << 1) 184#define DC_GPIO0 (1U << 2) 185#define DC_GPIO1 (1U << 3) 186 187#define STGE_AsicCtrl 0x30 188#define AC_ExpRomDisable (1U << 0) 189#define AC_ExpRomSize (1U << 1) 190#define AC_PhySpeed10 (1U << 4) 191#define AC_PhySpeed100 (1U << 5) 192#define AC_PhySpeed1000 (1U << 6) 193#define AC_PhyMedia (1U << 7) 194#define AC_ForcedConfig(x) ((x) << 8) 195#define AC_ForcedConfig_MASK AC_ForcedConfig(7) 196#define AC_D3ResetDisable (1U << 11) 197#define AC_SpeedupMode (1U << 13) 198#define AC_LEDMode (1U << 14) 199#define AC_RstOutPolarity (1U << 15) 200#define AC_GlobalReset (1U << 16) 201#define AC_RxReset (1U << 17) 202#define AC_TxReset (1U << 18) 203#define AC_DMA (1U << 19) 204#define AC_FIFO (1U << 20) 205#define AC_Network (1U << 21) 206#define AC_Host (1U << 22) 207#define AC_AutoInit (1U << 23) 208#define AC_RstOut (1U << 24) 209#define AC_InterruptRequest (1U << 25) 210#define AC_ResetBusy (1U << 26) 211 212#define STGE_FIFOCtrl 0x38 /* 16-bit */ 213#define FC_RAMTestMode (1U << 0) 214#define FC_Transmitting (1U << 14) 215#define FC_Receiving (1U << 15) 216 217#define STGE_RxEarlyThresh 0x3a /* 16-bit */ 218 219#define STGE_FlowOffThresh 0x3c /* 16-bit */ 220 221#define STGE_FlowOnTresh 0x3e /* 16-bit */ 222 223#define STGE_TxStartThresh 0x44 /* 16-bit */ 224 225#define STGE_EepromData 0x48 /* 16-bit */ 226 227#define STGE_EepromCtrl 0x4a /* 16-bit */ 228#define EC_EepromAddress(x) ((x) & 0xff) 229#define EC_EepromOpcode(x) ((x) << 8) 230#define EC_OP_WE 0 231#define EC_OP_WR 1 232#define EC_OP_RR 2 233#define EC_OP_ER 3 234#define EC_EepromBusy (1U << 15) 235 236#define STGE_ExpRomAddr 0x4c 237 238#define STGE_ExpRomData 0x50 /* 8-bit */ 239 240#define STGE_WakeEvent 0x51 /* 8-bit */ 241 242#define STGE_Countdown 0x54 243#define CD_Count(x) ((x) & 0xffff) 244#define CD_CountdownSpeed (1U << 24) 245#define CD_CountdownMode (1U << 25) 246#define CD_CountdownIntEnabled (1U << 26) 247 248#define STGE_IntStatusAck 0x5a /* 16-bit */ 249 250#define STGE_IntStatus 0x5e /* 16-bit */ 251 252#define STGE_IntEnable 0x5c /* 16-bit */ 253 254#define IS_InterruptStatus (1U << 0) 255#define IS_HostError (1U << 1) 256#define IS_TxComplete (1U << 2) 257#define IS_MACControlFrame (1U << 3) 258#define IS_RxComplete (1U << 4) 259#define IS_RxEarly (1U << 5) 260#define IS_InRequested (1U << 6) 261#define IS_UpdateStats (1U << 7) 262#define IS_LinkEvent (1U << 8) 263#define IS_TxDMAComplete (1U << 9) 264#define IS_RxDMAComplete (1U << 10) 265#define IS_RFDListEnd (1U << 11) 266#define IS_RxDMAPriority (1U << 12) 267 268#define STGE_TxStatus 0x60 269#define TS_TxError (1U << 0) 270#define TS_LateCollision (1U << 2) 271#define TS_MaxCollisions (1U << 3) 272#define TS_TxUnderrun (1U << 4) 273#define TS_TxIndicateReqd (1U << 6) 274#define TS_TxComplete (1U << 7) 275#define TS_TxFrameId_get(x) ((x) >> 16) 276 277#define STGE_MACCtrl 0x6c 278#define MC_IFSSelect(x) ((x) & 3) 279#define MC_DuplexSelect (1U << 5) 280#define MC_RcvLargeFrames (1U << 6) 281#define MC_TxFlowControlEnable (1U << 7) 282#define MC_RxFlowControlEnable (1U << 8) 283#define MC_RcvFCS (1U << 9) 284#define MC_FIFOLoopback (1U << 10) 285#define MC_MACLoopback (1U << 11) 286#define MC_AutoVLANtagging (1U << 12) 287#define MC_AutoVLANuntagging (1U << 13) 288#define MC_CollisionDetect (1U << 16) 289#define MC_CarrierSense (1U << 17) 290#define MC_StatisticsEnable (1U << 21) 291#define MC_StatisticsDisable (1U << 22) 292#define MC_StatisticsEnabled (1U << 23) 293#define MC_TxEnable (1U << 24) 294#define MC_TxDisable (1U << 25) 295#define MC_TxEnabled (1U << 26) 296#define MC_RxEnable (1U << 27) 297#define MC_RxDisable (1U << 28) 298#define MC_RxEnabled (1U << 29) 299#define MC_Paused (1U << 30) 300 301#define STGE_VLANTag 0x70 302 303#define STGE_PhyCtrl 0x76 /* 8-bit */ 304#define PC_MgmtClk (1U << 0) 305#define PC_MgmtData (1U << 1) 306#define PC_MgmtDir (1U << 2) /* MAC->PHY */ 307#define PC_PhyDuplexPolarity (1U << 3) 308#define PC_PhyDuplexStatus (1U << 4) 309#define PC_PhyLnkPolarity (1U << 5) 310#define PC_LinkSpeed(x) (((x) >> 6) & 3) 311#define PC_LinkSpeed_Down 0 312#define PC_LinkSpeed_10 1 313#define PC_LinkSpeed_100 2 314#define PC_LinkSpeed_1000 3 315 316#define STGE_StationAddress0 0x78 /* 16-bit */ 317 318#define STGE_StationAddress1 0x7a /* 16-bit */ 319 320#define STGE_StationAddress2 0x7c /* 16-bit */ 321 322#define STGE_VLANHashTable 0x7e /* 16-bit */ 323 324#define STGE_VLANId 0x80 325 326#define STGE_MaxFrameSize 0x86 327 328#define STGE_ReceiveMode 0x88 /* 16-bit */ 329#define RM_ReceiveUnicast (1U << 0) 330#define RM_ReceiveMulticast (1U << 1) 331#define RM_ReceiveBroadcast (1U << 2) 332#define RM_ReceiveAllFrames (1U << 3) 333#define RM_ReceiveMulticastHash (1U << 4) 334#define RM_ReceiveIPMulticast (1U << 5) 335#define RM_ReceiveVLANMatch (1U << 8) 336#define RM_ReceiveVLANHash (1U << 9) 337 338#define STGE_HashTable0 0x8c 339 340#define STGE_HashTable1 0x90 341 342#define STGE_RMONStatisticsMask 0x98 /* set to disable */ 343 344#define STGE_StatisticsMask 0x9c /* set to disable */ 345 346#define STGE_RxJumboFrames 0xbc /* 16-bit */ 347 348#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 349 350#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 351 352#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 353 354#define STGE_TxJumboFrames 0xf4 /* 16-bit */ 355 356/* 357 * TC9021 statistics. Available memory and I/O mapped. 358 */ 359 360#define STGE_OctetRcvOk 0xa8 361 362#define STGE_McstOctetRcvdOk 0xac 363 364#define STGE_BcstOctetRcvdOk 0xb0 365 366#define STGE_FramesRcvdOk 0xb4 367 368#define STGE_McstFramesRcvdOk 0xb8 369 370#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 371 372#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 373 374#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 375 376#define STGE_InRangeLengthErrors 0xca /* 16-bit */ 377 378#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 379 380#define STGE_FramesLostRxErrors 0xce /* 16-bit */ 381 382#define STGE_OctetXmtdOk 0xd0 383 384#define STGE_McstOctetXmtdOk 0xd4 385 386#define STGE_BcstOctetXmtdOk 0xd8 387 388#define STGE_FramesXmtdOk 0xdc 389 390#define STGE_McstFramesXmtdOk 0xe0 391 392#define STGE_FramesWDeferredXmt 0xe4 393 394#define STGE_LateCollisions 0xe8 395 396#define STGE_MultiColFrames 0xec 397 398#define STGE_SingleColFrames 0xf0 399 400#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 401 402#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 403 404#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 405 406#define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 407 408#define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 409 410/* 411 * RMON-compatible statistics. Only accessible if memory-mapped. 412 */ 413 414#define STGE_EtherStatsCollisions 0x100 415 416#define STGE_EtherStatsOctetsTransmit 0x104 417 418#define STGE_EtherStatsPktsTransmit 0x108 419 420#define STGE_EtherStatsPkts64OctetsTransmit 0x10c 421 422#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 423 424#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 425 426#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 427 428#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 429 430#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 431 432#define STGE_EtherStatsCRCAlignErrors 0x124 433 434#define STGE_EtherStatsUndersizePkts 0x128 435 436#define STGE_EtherStatsFragments 0x12c 437 438#define STGE_EtherStatsJabbers 0x130 439 440#define STGE_EtherStatsOctets 0x134 441 442#define STGE_EtherStatsPkts 0x138 443 444#define STGE_EtherStatsPkts64Octets 0x13c 445 446#define STGE_EtherStatsPkts65to127Octets 0x140 447 448#define STGE_EtherStatsPkts128to255Octets 0x144 449 450#define STGE_EtherStatsPkts256to511Octets 0x148 451 452#define STGE_EtherStatsPkts512to1023Octets 0x14c 453 454#define STGE_EtherStatsPkts1024to1518Octets 0x150 455 456/* 457 * Transmit descriptor list size. 458 */ 459#define STGE_NTXDESC 256 460#define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 461#define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 462 463/* 464 * Receive descriptor list size. 465 */ 466#define STGE_NRXDESC 256 467#define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 468#define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 469 470/* 471 * Only interrupt every N frames. Must be a power-of-two. 472 */ 473#define STGE_TXINTR_SPACING 16 474#define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 475 476/* 477 * Control structures are DMA'd to the TC9021 chip. We allocate them in 478 * a single clump that maps to a single DMA segment to make several things 479 * easier. 480 */ 481struct stge_control_data { 482 /* 483 * The transmit descriptors. 484 */ 485 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 486 487 /* 488 * The receive descriptors. 489 */ 490 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 491}; 492 493/* 494 * Software state for transmit and receive jobs. 495 */ 496struct stge_descsoft { 497 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 498 bus_dmamap_t ds_dmamap; /* our DMA map */ 499}; 500 501/* 502 * Software state per device. 503 */ 504struct stge_softc { 505 device_t sc_dev; /* generic device information */ 506 bus_space_tag_t sc_st; /* bus space tag */ 507 bus_space_handle_t sc_sh; /* bus space handle */ 508 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 509 struct ethercom sc_ethercom; /* ethernet common data */ 510 int sc_rev; /* silicon revision */ 511 512 void *sc_ih; /* interrupt cookie */ 513 514 struct mii_data sc_mii; /* MII/media information */ 515 516 callout_t sc_tick_ch; /* tick callout */ 517 518 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 519#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 520 521 /* 522 * Software state for transmit and receive descriptors. 523 */ 524 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 525 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 526 527 /* 528 * Control data structures. 529 */ 530 struct stge_control_data *sc_control_data; 531#define sc_txdescs sc_control_data->scd_txdescs 532#define sc_rxdescs sc_control_data->scd_rxdescs 533 534#ifdef STGE_EVENT_COUNTERS 535 /* 536 * Event counters. 537 */ 538 struct evcnt sc_ev_txstall; /* Tx stalled */ 539 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 540 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 541 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 542 543 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 544 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 545 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 546 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 547 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 548 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 549 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 550 551 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 552 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 553 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 554 555 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 556 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 557 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 558#endif /* STGE_EVENT_COUNTERS */ 559 560 int sc_txpending; /* number of Tx requests pending */ 561 int sc_txdirty; /* first dirty Tx descriptor */ 562 int sc_txlast; /* last used Tx descriptor */ 563 564 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 565 int sc_rxdiscard; 566 int sc_rxlen; 567 struct mbuf *sc_rxhead; 568 struct mbuf *sc_rxtail; 569 struct mbuf **sc_rxtailp; 570 571 int sc_txthresh; /* Tx threshold */ 572 uint32_t sc_usefiber:1; /* if we're fiber */ 573 uint32_t sc_stge1023:1; /* are we a 1023 */ 574 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 575 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 576 uint16_t sc_IntEnable; /* prototype IntEnable register */ 577 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 578 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 579}; 580 581#endif /* _DEV_PCI_IF_STGEREG_H_ */ 582