if_ixlvar.h revision 1.5
1/* $NetBSD: if_ixlvar.h,v 1.5 2020/01/31 02:16:26 yamaguchi Exp $ */ 2 3/* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _DEV_PCI_IF_IXLVAR_H_ 30#define _DEV_PCI_IF_IXLVAR_H_ 31 32enum i40e_filter_pctype { 33 /* Note: Values 0-28 are reserved for future use. 34 * Value 29, 30, 32 are not supported on XL710 and X710. 35 */ 36 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 37 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 38 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 39 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 40 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 41 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 42 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 43 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 44 /* Note: Values 37-38 are reserved for future use. 45 * Value 39, 40, 42 are not supported on XL710 and X710. 46 */ 47 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 48 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 49 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 50 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 51 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 52 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 53 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 54 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 55 /* Note: Value 47 is reserved for future use */ 56 I40E_FILTER_PCTYPE_FCOE_OX = 48, 57 I40E_FILTER_PCTYPE_FCOE_RX = 49, 58 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 59 /* Note: Values 51-62 are reserved for future use */ 60 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 61}; 62 63enum i40e_reset_type { 64 I40E_RESET_POR = 0, 65 I40E_RESET_CORER = 1, 66 I40E_RESET_GLOBR = 2, 67 I40E_RESET_EMPR = 3, 68}; 69 70struct ixl_aq_desc { 71 uint16_t iaq_flags; 72#define IXL_AQ_DD (1U << 0) 73#define IXL_AQ_CMP (1U << 1) 74#define IXL_AQ_ERR (1U << 2) 75#define IXL_AQ_VFE (1U << 3) 76#define IXL_AQ_LB (1U << 9) 77#define IXL_AQ_RD (1U << 10) 78#define IXL_AQ_VFC (1U << 11) 79#define IXL_AQ_BUF (1U << 12) 80#define IXL_AQ_SI (1U << 13) 81#define IXL_AQ_EI (1U << 14) 82#define IXL_AQ_FE (1U << 15) 83 84#define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 85 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 86 "\003ERR" "\002CMP" "\001DD" 87 88 uint16_t iaq_opcode; 89 90 uint16_t iaq_datalen; 91 uint16_t iaq_retval; 92 93 uint64_t iaq_cookie; 94 95 uint32_t iaq_param[4]; 96/* iaq_data_hi iaq_param[2] */ 97/* iaq_data_lo iaq_param[3] */ 98} __packed __aligned(16); 99 100/* aq commands */ 101#define IXL_AQ_OP_GET_VERSION 0x0001 102#define IXL_AQ_OP_DRIVER_VERSION 0x0002 103#define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 104#define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 105#define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 106#define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 107#define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 108#define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 109#define IXL_AQ_OP_LIST_DEV_CAP 0x000b 110#define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 111#define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 112#define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 113#define IXL_AQ_OP_RX_CTL_REG_READ 0x0206 114#define IXL_AQ_OP_RX_CTL_REG_WRITE 0x0207 115#define IXL_AQ_OP_ADD_VSI 0x0210 116#define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 117#define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 118#define IXL_AQ_OP_ADD_VEB 0x0230 119#define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 120#define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 121#define IXL_AQ_OP_ADD_MACVLAN 0x0250 122#define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 123#define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 124#define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 125#define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 126#define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 127#define IXL_AQ_OP_PHY_RESTART_AN 0x0605 128#define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 129#define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 130#define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 131#define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 132#define IXL_AQ_OP_NVM_READ 0x0701 133#define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 134#define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 135#define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 136#define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 137#define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 138#define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 139#define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 140#define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 141#define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 142 143struct ixl_aq_mac_addresses { 144 uint8_t pf_lan[ETHER_ADDR_LEN]; 145 uint8_t pf_san[ETHER_ADDR_LEN]; 146 uint8_t port[ETHER_ADDR_LEN]; 147 uint8_t pf_wol[ETHER_ADDR_LEN]; 148} __packed; 149 150#define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 151#define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 152#define IXL_AQ_MAC_PORT_VALID (1U << 6) 153#define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 154 155struct ixl_aq_capability { 156 uint16_t cap_id; 157#define IXL_AQ_CAP_SWITCH_MODE 0x0001 158#define IXL_AQ_CAP_MNG_MODE 0x0002 159#define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 160#define IXL_AQ_CAP_OS2BMC_CAP 0x0004 161#define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 162#define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 163#define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 164#define IXL_AQ_CAP_SRIOV 0x0012 165#define IXL_AQ_CAP_VF 0x0013 166#define IXL_AQ_CAP_VMDQ 0x0014 167#define IXL_AQ_CAP_8021QBG 0x0015 168#define IXL_AQ_CAP_8021QBR 0x0016 169#define IXL_AQ_CAP_VSI 0x0017 170#define IXL_AQ_CAP_DCB 0x0018 171#define IXL_AQ_CAP_FCOE 0x0021 172#define IXL_AQ_CAP_ISCSI 0x0022 173#define IXL_AQ_CAP_RSS 0x0040 174#define IXL_AQ_CAP_RXQ 0x0041 175#define IXL_AQ_CAP_TXQ 0x0042 176#define IXL_AQ_CAP_MSIX 0x0043 177#define IXL_AQ_CAP_VF_MSIX 0x0044 178#define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 179#define IXL_AQ_CAP_1588 0x0046 180#define IXL_AQ_CAP_IWARP 0x0051 181#define IXL_AQ_CAP_LED 0x0061 182#define IXL_AQ_CAP_SDP 0x0062 183#define IXL_AQ_CAP_MDIO 0x0063 184#define IXL_AQ_CAP_WSR_PROT 0x0064 185#define IXL_AQ_CAP_NVM_MGMT 0x0080 186#define IXL_AQ_CAP_FLEX10 0x00F1 187#define IXL_AQ_CAP_CEM 0x00F2 188 uint8_t major_rev; 189 uint8_t minor_rev; 190 uint32_t number; 191 uint32_t logical_id; 192 uint32_t phys_id; 193 uint8_t _reserved[16]; 194} __packed __aligned(4); 195 196#define IXL_LLDP_SHUTDOWN 0x1 197 198struct ixl_aq_switch_config { 199 uint16_t num_reported; 200 uint16_t num_total; 201 uint8_t _reserved[12]; 202} __packed __aligned(4); 203 204struct ixl_aq_switch_config_element { 205 uint8_t type; 206#define IXL_AQ_SW_ELEM_TYPE_MAC 1 207#define IXL_AQ_SW_ELEM_TYPE_PF 2 208#define IXL_AQ_SW_ELEM_TYPE_VF 3 209#define IXL_AQ_SW_ELEM_TYPE_EMP 4 210#define IXL_AQ_SW_ELEM_TYPE_BMC 5 211#define IXL_AQ_SW_ELEM_TYPE_PV 16 212#define IXL_AQ_SW_ELEM_TYPE_VEB 17 213#define IXL_AQ_SW_ELEM_TYPE_PA 18 214#define IXL_AQ_SW_ELEM_TYPE_VSI 19 215 uint8_t revision; 216#define IXL_AQ_SW_ELEM_REV_1 1 217 uint16_t seid; 218 219 uint16_t uplink_seid; 220 uint16_t downlink_seid; 221 222 uint8_t _reserved[3]; 223 uint8_t connection_type; 224#define IXL_AQ_CONN_TYPE_REGULAR 0x1 225#define IXL_AQ_CONN_TYPE_DEFAULT 0x2 226#define IXL_AQ_CONN_TYPE_CASCADED 0x3 227 228 uint16_t scheduler_id; 229 uint16_t element_info; 230} __packed __aligned(4); 231 232#define IXL_PHY_TYPE_SGMII 0x00 233#define IXL_PHY_TYPE_1000BASE_KX 0x01 234#define IXL_PHY_TYPE_10GBASE_KX4 0x02 235#define IXL_PHY_TYPE_10GBASE_KR 0x03 236#define IXL_PHY_TYPE_40GBASE_KR4 0x04 237#define IXL_PHY_TYPE_XAUI 0x05 238#define IXL_PHY_TYPE_XFI 0x06 239#define IXL_PHY_TYPE_SFI 0x07 240#define IXL_PHY_TYPE_XLAUI 0x08 241#define IXL_PHY_TYPE_XLPPI 0x09 242#define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 243#define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 244#define IXL_PHY_TYPE_10GBASE_AOC 0x0c 245#define IXL_PHY_TYPE_40GBASE_AOC 0x0d 246#define IXL_PHY_TYPE_100BASE_TX 0x11 247#define IXL_PHY_TYPE_1000BASE_T 0x12 248#define IXL_PHY_TYPE_10GBASE_T 0x13 249#define IXL_PHY_TYPE_10GBASE_SR 0x14 250#define IXL_PHY_TYPE_10GBASE_LR 0x15 251#define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 252#define IXL_PHY_TYPE_10GBASE_CR1 0x17 253#define IXL_PHY_TYPE_40GBASE_CR4 0x18 254#define IXL_PHY_TYPE_40GBASE_SR4 0x19 255#define IXL_PHY_TYPE_40GBASE_LR4 0x1a 256#define IXL_PHY_TYPE_1000BASE_SX 0x1b 257#define IXL_PHY_TYPE_1000BASE_LX 0x1c 258#define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 259#define IXL_PHY_TYPE_20GBASE_KR2 0x1e 260 261#define IXL_PHY_TYPE_25GBASE_KR 0x1f 262#define IXL_PHY_TYPE_25GBASE_CR 0x20 263#define IXL_PHY_TYPE_25GBASE_SR 0x21 264#define IXL_PHY_TYPE_25GBASE_LR 0x22 265#define IXL_PHY_TYPE_25GBASE_AOC 0x23 266#define IXL_PHY_TYPE_25GBASE_ACC 0x24 267 268#define IXL_PHY_LINK_SPEED_100MB (1 << 1) 269#define IXL_PHY_LINK_SPEED_1000MB (1 << 2) 270#define IXL_PHY_LINK_SPEED_10GB (1 << 3) 271#define IXL_PHY_LINK_SPEED_40GB (1 << 4) 272#define IXL_PHY_LINK_SPEED_20GB (1 << 5) 273#define IXL_PHY_LINK_SPEED_25GB (1 << 6) 274 275#define IXL_PHY_ABILITY_PAUSE_TX (1 << 0) 276#define IXL_PHY_ABILITY_PAUSE_RX (1 << 1) 277#define IXL_PHY_ABILITY_LOWPOW (1 << 2) 278#define IXL_PHY_ABILITY_LINKUP (1 << 3) 279#define IXL_PHY_ABILITY_AUTONEGO (1 << 4) 280#define IXL_PHY_ABILITY_MODQUAL (1 << 5) 281 282struct ixl_aq_module_desc { 283 uint8_t oui[3]; 284 uint8_t _reserved1; 285 uint8_t part_number[16]; 286 uint8_t revision[4]; 287 uint8_t _reserved2[8]; 288} __packed __aligned(4); 289 290struct ixl_aq_phy_abilities { 291 uint32_t phy_type; 292 293 uint8_t link_speed; 294 uint8_t abilities; 295 uint16_t eee_capability; 296 297 uint32_t eeer_val; 298 299 uint8_t d3_lpan; 300 uint8_t phy_type_ext; 301#define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 302#define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 303#define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 304#define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 305 uint8_t fec_cfg_curr_mod_ext_info; 306#define IXL_AQ_ENABLE_FEC_KR 0x01 307#define IXL_AQ_ENABLE_FEC_RS 0x02 308#define IXL_AQ_REQUEST_FEC_KR 0x04 309#define IXL_AQ_REQUEST_FEC_RS 0x08 310#define IXL_AQ_ENABLE_FEC_AUTO 0x10 311#define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 312#define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 313 uint8_t ext_comp_code; 314 315 uint8_t phy_id[4]; 316 317 uint8_t module_type[3]; 318#define IXL_SFF8024_ID_SFP 0x03 319#define IXL_SFF8024_ID_QSFP 0x0c 320#define IXL_SFF8024_ID_QSFP_PLUS 0x0d 321#define IXL_SFF8024_ID_QSFP28 0x11 322 uint8_t qualified_module_count; 323#define IXL_AQ_PHY_MAX_QMS 16 324 struct ixl_aq_module_desc 325 qualified_module[IXL_AQ_PHY_MAX_QMS]; 326} __packed __aligned(4); 327 328struct ixl_aq_phy_param { 329 uint32_t phy_types; 330 uint8_t link_speed; 331 uint8_t abilities; 332#define IXL_AQ_PHY_ABILITY_AUTO_LINK (1 << 5) 333 uint16_t eee_capability; 334 uint32_t eeer_val; 335 uint8_t d3_lpan; 336 uint8_t phy_type_ext; 337 uint8_t fec_cfg; 338 uint8_t config; 339} __packed __aligned(4); 340 341struct ixl_aq_link_param { 342 uint8_t notify; 343#define IXL_AQ_LINK_NOTIFY 0x03 344 uint8_t _reserved1; 345 uint8_t phy; 346 uint8_t speed; 347 uint8_t status; 348 uint8_t _reserved2[11]; 349} __packed __aligned(4); 350 351struct ixl_aq_vsi_param { 352 uint16_t uplink_seid; 353 uint8_t connect_type; 354#define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 355#define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 356#define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 357 uint8_t _reserved1; 358 359 uint8_t vf_id; 360 uint8_t _reserved2; 361 uint16_t vsi_flags; 362#define IXL_AQ_VSI_TYPE_SHIFT 0x0 363#define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 364#define IXL_AQ_VSI_TYPE_VF 0x0 365#define IXL_AQ_VSI_TYPE_VMDQ2 0x1 366#define IXL_AQ_VSI_TYPE_PF 0x2 367#define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 368#define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 369 370 uint32_t addr_hi; 371 uint32_t addr_lo; 372} __packed __aligned(16); 373 374struct ixl_aq_add_macvlan { 375 uint16_t num_addrs; 376 uint16_t seid0; 377 uint16_t seid1; 378 uint16_t seid2; 379 uint32_t addr_hi; 380 uint32_t addr_lo; 381} __packed __aligned(16); 382 383struct ixl_aq_add_macvlan_elem { 384 uint8_t macaddr[6]; 385 uint16_t vlan; 386 uint16_t flags; 387#define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 388#define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 389 uint16_t queue; 390 uint32_t _reserved; 391} __packed __aligned(16); 392 393struct ixl_aq_remove_macvlan { 394 uint16_t num_addrs; 395 uint16_t seid0; 396 uint16_t seid1; 397 uint16_t seid2; 398 uint32_t addr_hi; 399 uint32_t addr_lo; 400} __packed __aligned(16); 401 402struct ixl_aq_remove_macvlan_elem { 403 uint8_t macaddr[6]; 404 uint16_t vlan; 405 uint8_t flags; 406#define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 407#define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 408 uint8_t _reserved[7]; 409} __packed __aligned(16); 410 411struct ixl_aq_vsi_reply { 412 uint16_t seid; 413 uint16_t vsi_number; 414 415 uint16_t vsis_used; 416 uint16_t vsis_free; 417 418 uint32_t addr_hi; 419 uint32_t addr_lo; 420} __packed __aligned(16); 421 422struct ixl_aq_vsi_data { 423 /* first 96 byte are written by SW */ 424 uint16_t valid_sections; 425#define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 426#define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 427#define IXL_AQ_VSI_VALID_VLAN (1 << 2) 428#define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 429#define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 430#define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 431#define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 432#define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 433#define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 434#define IXL_AQ_VSI_VALID_SCHED (1 << 9) 435 /* switch section */ 436 uint16_t switch_id; 437#define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 438#define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 439#define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 440#define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 441 442 uint8_t _reserved1[2]; 443 /* security section */ 444 uint8_t sec_flags; 445#define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 446#define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 447#define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 448 uint8_t _reserved2; 449 450 /* vlan section */ 451 uint16_t pvid; 452 uint16_t fcoe_pvid; 453 454 uint8_t port_vlan_flags; 455#define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 456#define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 457#define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 458#define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 459#define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 460#define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 461#define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 462#define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 463#define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 464#define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 465#define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 466#define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 467 uint8_t _reserved3[3]; 468 469 /* ingress egress up section */ 470 uint32_t ingress_table; 471#define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 472#define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 473 uint32_t egress_table; 474 475 /* cascaded pv section */ 476 uint16_t cas_pv_tag; 477 uint8_t cas_pv_flags; 478#define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 479#define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 480#define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 481#define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 482#define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 483#define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 484#define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 485#define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 486 (1 << 6) 487 uint8_t _reserved4; 488 489 /* queue mapping section */ 490 uint16_t mapping_flags; 491#define IXL_AQ_VSI_QUE_MAP_MASK 0x1 492#define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 493#define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 494 uint16_t queue_mapping[16]; 495#define IXL_AQ_VSI_QUEUE_SHIFT 0x0 496#define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 497 uint16_t tc_mapping[8]; 498#define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 499#define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 500#define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 501#define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 502 503 /* queueing option section */ 504 uint8_t queueing_opt_flags; 505#define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 506#define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 507#define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 508#define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 509#define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 510#define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 511 uint8_t _reserved5[3]; 512 513 /* scheduler section */ 514 uint8_t up_enable_bits; 515 uint8_t _reserved6; 516 517 /* outer up section */ 518 uint32_t outer_up_table; /* same as ingress/egress tables */ 519 uint8_t _reserved7[8]; 520 521 /* last 32 bytes are written by FW */ 522 uint16_t qs_handle[8]; 523#define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 524 uint16_t stat_counter_idx; 525 uint16_t sched_id; 526 527 uint8_t _reserved8[12]; 528} __packed __aligned(8); 529 530CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 531 532struct ixl_aq_vsi_promisc_param { 533 uint16_t flags; 534 uint16_t valid_flags; 535#define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 536#define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 537#define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 538#define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 539#define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 540#define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 541 542 uint16_t seid; 543#define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 544 uint16_t vlan; 545#define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 546 uint32_t reserved[2]; 547} __packed __aligned(8); 548 549struct ixl_aq_veb_param { 550 uint16_t uplink_seid; 551 uint16_t downlink_seid; 552 uint16_t veb_flags; 553#define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 554#define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 555#define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 556#define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 557 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 558#define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 559#define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 560#define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 561 uint8_t enable_tcs; 562 uint8_t _reserved[9]; 563} __packed __aligned(16); 564 565struct ixl_aq_veb_reply { 566 uint16_t _reserved1; 567 uint16_t _reserved2; 568 uint16_t _reserved3; 569 uint16_t switch_seid; 570 uint16_t veb_seid; 571#define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 572#define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 573#define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 574#define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 575 uint16_t statistic_index; 576 uint16_t vebs_used; 577 uint16_t vebs_free; 578} __packed __aligned(16); 579 580/* GET PHY ABILITIES param[0] */ 581#define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 582#define IXL_AQ_PHY_REPORT_INIT (1 << 1) 583 584struct ixl_aq_phy_reg_access { 585 uint8_t phy_iface; 586#define IXL_AQ_PHY_IF_INTERNAL 0 587#define IXL_AQ_PHY_IF_EXTERNAL 1 588#define IXL_AQ_PHY_IF_MODULE 2 589 uint8_t dev_addr; 590 uint16_t recall; 591#define IXL_AQ_PHY_QSFP_DEV_ADDR 0 592#define IXL_AQ_PHY_QSFP_LAST 1 593 uint32_t reg; 594 uint32_t val; 595 uint32_t _reserved2; 596} __packed __aligned(16); 597 598/* RESTART_AN param[0] */ 599#define IXL_AQ_PHY_RESTART_AN (1 << 1) 600#define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 601 602struct ixl_aq_link_status { /* this occupies the iaq_param space */ 603 uint16_t command_flags; /* only field set on command */ 604#define IXL_AQ_LSE_MASK 0x3 605#define IXL_AQ_LSE_NOP 0x0 606#define IXL_AQ_LSE_DISABLE 0x2 607#define IXL_AQ_LSE_ENABLE 0x3 608#define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 609 uint8_t phy_type; 610 uint8_t link_speed; 611#define IXL_AQ_LINK_SPEED_100MB (1 << 1) 612#define IXL_AQ_LINK_SPEED_1000MB (1 << 2) 613#define IXL_AQ_LINK_SPEED_10GB (1 << 3) 614#define IXL_AQ_LINK_SPEED_40GB (1 << 4) 615#define IXL_AQ_LINK_SPEED_25GB (1 << 6) 616 uint8_t link_info; 617#define IXL_AQ_LINK_UP_FUNCTION 0x01 618#define IXL_AQ_LINK_FAULT 0x02 619#define IXL_AQ_LINK_FAULT_TX 0x04 620#define IXL_AQ_LINK_FAULT_RX 0x08 621#define IXL_AQ_LINK_FAULT_REMOTE 0x10 622#define IXL_AQ_LINK_UP_PORT 0x20 623#define IXL_AQ_MEDIA_AVAILABLE 0x40 624#define IXL_AQ_SIGNAL_DETECT 0x80 625 uint8_t an_info; 626#define IXL_AQ_AN_COMPLETED 0x01 627#define IXL_AQ_LP_AN_ABILITY 0x02 628#define IXL_AQ_PD_FAULT 0x04 629#define IXL_AQ_FEC_EN 0x08 630#define IXL_AQ_PHY_LOW_POWER 0x10 631#define IXL_AQ_LINK_PAUSE_TX 0x20 632#define IXL_AQ_LINK_PAUSE_RX 0x40 633#define IXL_AQ_QUALIFIED_MODULE 0x80 634 635 uint8_t ext_info; 636#define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 637#define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 638#define IXL_AQ_LINK_TX_SHIFT 0x02 639#define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 640#define IXL_AQ_LINK_TX_ACTIVE 0x00 641#define IXL_AQ_LINK_TX_DRAINED 0x01 642#define IXL_AQ_LINK_TX_FLUSHED 0x03 643#define IXL_AQ_LINK_FORCED_40G 0x10 644/* 25G Error Codes */ 645#define IXL_AQ_25G_NO_ERR 0X00 646#define IXL_AQ_25G_NOT_PRESENT 0X01 647#define IXL_AQ_25G_NVM_CRC_ERR 0X02 648#define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 649#define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 650#define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 651 uint8_t loopback; 652 uint16_t max_frame_size; 653 654 uint8_t config; 655#define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 656#define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 657#define IXL_AQ_CONFIG_CRC_ENA 0x04 658#define IXL_AQ_CONFIG_PACING_MASK 0x78 659 uint8_t power_desc; 660#define IXL_AQ_LINK_POWER_CLASS_1 0x00 661#define IXL_AQ_LINK_POWER_CLASS_2 0x01 662#define IXL_AQ_LINK_POWER_CLASS_3 0x02 663#define IXL_AQ_LINK_POWER_CLASS_4 0x03 664#define IXL_AQ_PWR_CLASS_MASK 0x03 665 666 uint8_t reserved[4]; 667} __packed __aligned(4); 668 669/* event mask command flags for param[2] */ 670#define IXL_AQ_PHY_EV_MASK 0x3ff 671#define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 672#define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 673#define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 674#define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 675#define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 676#define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 677#define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 678#define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 679#define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 680 681struct ixl_aq_req_resource_param { 682 uint16_t resource_id; 683#define IXL_AQ_RESOURCE_ID_NVM 0x0001 684#define IXL_AQ_RESOURCE_ID_SDP 0x0002 685 686 uint16_t access_type; 687#define IXL_AQ_RESOURCE_ACCES_READ 0x01 688#define IXL_AQ_RESOURCE_ACCES_WRITE 0x02 689 690 uint16_t timeout; 691 uint32_t resource_num; 692 uint32_t reserved; 693} __packed __aligned(8); 694 695struct ixl_aq_rel_resource_param { 696 uint16_t resource_id; 697/* defined in ixl_aq_req_resource_param */ 698 uint16_t _reserved1[3]; 699 uint32_t resource_num; 700 uint32_t _reserved2; 701} __packed __aligned(8); 702 703struct ixl_aq_nvm_param { 704 uint8_t command_flags; 705#define IXL_AQ_NVM_LAST_CMD (1 << 0) 706#define IXL_AQ_NVM_FLASH_ONLY (1 << 7) 707 uint8_t module_pointer; 708 uint16_t length; 709 uint32_t offset; 710 uint32_t addr_hi; 711 uint32_t addr_lo; 712} __packed __aligned(4); 713 714/* aq response codes */ 715#define IXL_AQ_RC_OK 0 /* success */ 716#define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 717#define IXL_AQ_RC_ENOENT 2 /* No such element */ 718#define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 719#define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 720#define IXL_AQ_RC_EIO 5 /* I/O error */ 721#define IXL_AQ_RC_ENXIO 6 /* No such resource */ 722#define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 723#define IXL_AQ_RC_EAGAIN 8 /* Try again */ 724#define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 725#define IXL_AQ_RC_EACCES 10 /* Permission denied */ 726#define IXL_AQ_RC_EFAULT 11 /* Bad address */ 727#define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 728#define IXL_AQ_RC_EEXIST 13 /* object already exists */ 729#define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 730#define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 731#define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 732#define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 733#define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 734#define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 735#define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 736#define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 737#define IXL_AQ_RC_EFBIG 22 /* file too large */ 738 739struct ixl_tx_desc { 740 uint64_t addr; 741 uint64_t cmd; 742#define IXL_TX_DESC_DTYPE_SHIFT 0 743#define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 744#define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 745#define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 746#define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 747#define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 748#define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 749#define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 750#define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 751#define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 752#define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 753#define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 754 755#define IXL_TX_DESC_CMD_SHIFT 4 756#define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 757#define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 758#define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 759#define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 760#define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 761#define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 762#define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 763#define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 764#define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 765#define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 766#define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 767#define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 768#define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 769#define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 770#define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 771#define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 772#define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 773 774#define IXL_TX_DESC_MACLEN_SHIFT 16 775#define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 776#define IXL_TX_DESC_IPLEN_SHIFT 23 777#define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 778#define IXL_TX_DESC_L4LEN_SHIFT 30 779#define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 780#define IXL_TX_DESC_FCLEN_SHIFT 30 781#define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 782 783#define IXL_TX_DESC_BSIZE_SHIFT 34 784#define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 785#define IXL_TX_DESC_BSIZE_MASK \ 786 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 787#define IXL_TX_DESC_L2TAG1_SHIFT 48 788} __packed __aligned(16); 789 790struct ixl_rx_rd_desc_16 { 791 uint64_t paddr; /* packet addr */ 792 uint64_t haddr; /* header addr */ 793} __packed __aligned(16); 794 795struct ixl_rx_rd_desc_32 { 796 uint64_t paddr; /* packet addr */ 797 uint64_t haddr; /* header addr */ 798 uint64_t _reserved1; 799 uint64_t _reserved2; 800} __packed __aligned(16); 801 802struct ixl_rx_wb_desc_16 { 803 uint64_t qword0; 804#define IXL_RX_DESC_L2TAG1_SHIFT 16 805#define IXL_RX_DESC_L2TAG1_MASK (0xffffULL << IXL_RX_DESC_L2TAG1_SHIFT) 806 uint64_t qword1; 807#define IXL_RX_DESC_DD (1 << 0) 808#define IXL_RX_DESC_EOP (1 << 1) 809#define IXL_RX_DESC_L2TAG1P (1 << 2) 810#define IXL_RX_DESC_L3L4P (1 << 3) 811#define IXL_RX_DESC_CRCP (1 << 4) 812#define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 813#define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 814#define IXL_RX_DESC_UMB_SHIFT 9 815#define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 816#define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 817#define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 818#define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 819#define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 820#define IXL_RX_DESC_FLM (1 << 11) 821#define IXL_RX_DESC_FLTSTAT_SHIFT 12 822#define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 823#define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 824#define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 825#define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 826#define IXL_RX_DESC_LPBK (1 << 14) 827#define IXL_RX_DESC_IPV6EXTADD (1 << 15) 828#define IXL_RX_DESC_INT_UDP_0 (1 << 18) 829 830#define IXL_RX_DESC_RXE (1 << 19) 831#define IXL_RX_DESC_HBO (1 << 21) 832#define IXL_RX_DESC_IPE (1 << 22) 833#define IXL_RX_DESC_L4E (1 << 23) 834#define IXL_RX_DESC_EIPE (1 << 24) 835#define IXL_RX_DESC_OVERSIZE (1 << 25) 836 837#define IXL_RX_DESC_PTYPE_SHIFT 30 838#define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 839 840#define IXL_RX_DESC_PLEN_SHIFT 38 841#define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 842#define IXL_RX_DESC_HLEN_SHIFT 42 843#define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 844} __packed __aligned(16); 845 846enum ixl_rx_desc_ptype { 847 IXL_RX_DESC_PTYPE_IPV4FRAG = 22, 848 IXL_RX_DESC_PTYPE_IPV4 = 23, 849 IXL_RX_DESC_PTYPE_UDPV4 = 24, 850 IXL_RX_DESC_PTYPE_TCPV4 = 26, 851 IXL_RX_DESC_PTYPE_SCTPV4 = 27, 852 IXL_RX_DESC_PTYPE_ICMPV4 = 28, 853 854 IXL_RX_DESC_PTYPE_IPV6FRAG = 88, 855 IXL_RX_DESC_PTYPE_IPV6 = 89, 856 IXL_RX_DESC_PTYPE_UDPV6 = 90, 857 IXL_RX_DESC_PTYPE_TCPV6 = 92, 858 IXL_RX_DESC_PTYPE_SCTPV6 = 93, 859 IXL_RX_DESC_PTYPE_ICMPV6 = 94, 860}; 861 862struct ixl_rx_wb_desc_32 { 863 uint64_t qword0; 864 uint64_t qword1; 865 uint64_t qword2; 866 uint64_t qword3; 867} __packed __aligned(16); 868 869enum i40e_mac_type { 870 I40E_MAC_XL710, 871 I40E_MAC_X722, 872 I40E_MAC_X722_VF, 873 I40E_MAC_VF, 874 I40E_MAC_GENERIC 875}; 876 877#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 878#define I40E_SR_BOOT_CONFIG_PTR 0x17 879#define I40E_NVM_OEM_VER_OFF 0x83 880#define I40E_SR_NVM_EETRACK_LO 0x2D 881#define I40E_SR_NVM_EETRACK_HI 0x2E 882 883#define IXL_NVM_VERSION_LO_SHIFT 0 884#define IXL_NVM_VERSION_LO_MASK (0xffUL << IXL_NVM_VERSION_LO_SHIFT) 885#define IXL_NVM_VERSION_HI_SHIFT 12 886#define IXL_NVM_VERSION_HI_MASK (0xfUL << IXL_NVM_VERSION_HI_SHIFT) 887#define IXL_NVM_OEMVERSION_SHIFT 24 888#define IXL_NVM_OEMVERSION_MASK (0xffUL << IXL_NVM_OEMVERSION_SHIFT) 889#define IXL_NVM_OEMBUILD_SHIFT 8 890#define IXL_NVM_OEMBUILD_MASK (0xffffUL << IXL_NVM_OEMBUILD_SHIFT) 891#define IXL_NVM_OEMPATCH_SHIFT 0 892#define IXL_NVM_OEMPATCH_MASK (0xff << IXL_NVM_OEMPATCH_SHIFT) 893#endif 894