if_ixlvar.h revision 1.1
1/* $NetBSD: if_ixlvar.h,v 1.1 2019/12/10 12:08:52 yamaguchi Exp $ */ 2 3/* 4 * Copyright (c) 2019 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _DEV_PCI_IF_IXLVAR_H_ 30#define _DEV_PCI_IF_IXLVAR_H_ 31 32enum i40e_filter_pctype { 33 /* Note: Values 0-28 are reserved for future use. 34 * Value 29, 30, 32 are not supported on XL710 and X710. 35 */ 36 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 37 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 38 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 39 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 40 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 41 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 42 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 43 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 44 /* Note: Values 37-38 are reserved for future use. 45 * Value 39, 40, 42 are not supported on XL710 and X710. 46 */ 47 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 48 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 49 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 50 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 51 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 52 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 53 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 54 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 55 /* Note: Value 47 is reserved for future use */ 56 I40E_FILTER_PCTYPE_FCOE_OX = 48, 57 I40E_FILTER_PCTYPE_FCOE_RX = 49, 58 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 59 /* Note: Values 51-62 are reserved for future use */ 60 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 61}; 62 63enum i40e_reset_type { 64 I40E_RESET_POR = 0, 65 I40E_RESET_CORER = 1, 66 I40E_RESET_GLOBR = 2, 67 I40E_RESET_EMPR = 3, 68}; 69 70struct ixl_aq_desc { 71 uint16_t iaq_flags; 72#define IXL_AQ_DD (1U << 0) 73#define IXL_AQ_CMP (1U << 1) 74#define IXL_AQ_ERR (1U << 2) 75#define IXL_AQ_VFE (1U << 3) 76#define IXL_AQ_LB (1U << 9) 77#define IXL_AQ_RD (1U << 10) 78#define IXL_AQ_VFC (1U << 11) 79#define IXL_AQ_BUF (1U << 12) 80#define IXL_AQ_SI (1U << 13) 81#define IXL_AQ_EI (1U << 14) 82#define IXL_AQ_FE (1U << 15) 83 84#define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 85 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 86 "\003ERR" "\002CMP" "\001DD" 87 88 uint16_t iaq_opcode; 89 90 uint16_t iaq_datalen; 91 uint16_t iaq_retval; 92 93 uint64_t iaq_cookie; 94 95 uint32_t iaq_param[4]; 96/* iaq_data_hi iaq_param[2] */ 97/* iaq_data_lo iaq_param[3] */ 98} __packed __aligned(16); 99 100/* aq commands */ 101#define IXL_AQ_OP_GET_VERSION 0x0001 102#define IXL_AQ_OP_DRIVER_VERSION 0x0002 103#define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 104#define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 105#define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 106#define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 107#define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 108#define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 109#define IXL_AQ_OP_LIST_DEV_CAP 0x000b 110#define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 111#define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 112#define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 113#define IXL_AQ_OP_RX_CTL_REG_READ 0x0206 114#define IXL_AQ_OP_RX_CTL_REG_WRITE 0x0207 115#define IXL_AQ_OP_ADD_VSI 0x0210 116#define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 117#define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 118#define IXL_AQ_OP_ADD_VEB 0x0230 119#define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 120#define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 121#define IXL_AQ_OP_ADD_MACVLAN 0x0250 122#define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 123#define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 124#define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 125#define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 126#define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 127#define IXL_AQ_OP_PHY_RESTART_AN 0x0605 128#define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 129#define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 130#define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 131#define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 132#define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 133#define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 134#define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 135#define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 136#define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 137#define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 138#define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 139#define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 140#define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 141 142struct ixl_aq_mac_addresses { 143 uint8_t pf_lan[ETHER_ADDR_LEN]; 144 uint8_t pf_san[ETHER_ADDR_LEN]; 145 uint8_t port[ETHER_ADDR_LEN]; 146 uint8_t pf_wol[ETHER_ADDR_LEN]; 147} __packed; 148 149#define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 150#define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 151#define IXL_AQ_MAC_PORT_VALID (1U << 6) 152#define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 153 154struct ixl_aq_capability { 155 uint16_t cap_id; 156#define IXL_AQ_CAP_SWITCH_MODE 0x0001 157#define IXL_AQ_CAP_MNG_MODE 0x0002 158#define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 159#define IXL_AQ_CAP_OS2BMC_CAP 0x0004 160#define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 161#define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 162#define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 163#define IXL_AQ_CAP_SRIOV 0x0012 164#define IXL_AQ_CAP_VF 0x0013 165#define IXL_AQ_CAP_VMDQ 0x0014 166#define IXL_AQ_CAP_8021QBG 0x0015 167#define IXL_AQ_CAP_8021QBR 0x0016 168#define IXL_AQ_CAP_VSI 0x0017 169#define IXL_AQ_CAP_DCB 0x0018 170#define IXL_AQ_CAP_FCOE 0x0021 171#define IXL_AQ_CAP_ISCSI 0x0022 172#define IXL_AQ_CAP_RSS 0x0040 173#define IXL_AQ_CAP_RXQ 0x0041 174#define IXL_AQ_CAP_TXQ 0x0042 175#define IXL_AQ_CAP_MSIX 0x0043 176#define IXL_AQ_CAP_VF_MSIX 0x0044 177#define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 178#define IXL_AQ_CAP_1588 0x0046 179#define IXL_AQ_CAP_IWARP 0x0051 180#define IXL_AQ_CAP_LED 0x0061 181#define IXL_AQ_CAP_SDP 0x0062 182#define IXL_AQ_CAP_MDIO 0x0063 183#define IXL_AQ_CAP_WSR_PROT 0x0064 184#define IXL_AQ_CAP_NVM_MGMT 0x0080 185#define IXL_AQ_CAP_FLEX10 0x00F1 186#define IXL_AQ_CAP_CEM 0x00F2 187 uint8_t major_rev; 188 uint8_t minor_rev; 189 uint32_t number; 190 uint32_t logical_id; 191 uint32_t phys_id; 192 uint8_t _reserved[16]; 193} __packed __aligned(4); 194 195#define IXL_LLDP_SHUTDOWN 0x1 196 197struct ixl_aq_switch_config { 198 uint16_t num_reported; 199 uint16_t num_total; 200 uint8_t _reserved[12]; 201} __packed __aligned(4); 202 203struct ixl_aq_switch_config_element { 204 uint8_t type; 205#define IXL_AQ_SW_ELEM_TYPE_MAC 1 206#define IXL_AQ_SW_ELEM_TYPE_PF 2 207#define IXL_AQ_SW_ELEM_TYPE_VF 3 208#define IXL_AQ_SW_ELEM_TYPE_EMP 4 209#define IXL_AQ_SW_ELEM_TYPE_BMC 5 210#define IXL_AQ_SW_ELEM_TYPE_PV 16 211#define IXL_AQ_SW_ELEM_TYPE_VEB 17 212#define IXL_AQ_SW_ELEM_TYPE_PA 18 213#define IXL_AQ_SW_ELEM_TYPE_VSI 19 214 uint8_t revision; 215#define IXL_AQ_SW_ELEM_REV_1 1 216 uint16_t seid; 217 218 uint16_t uplink_seid; 219 uint16_t downlink_seid; 220 221 uint8_t _reserved[3]; 222 uint8_t connection_type; 223#define IXL_AQ_CONN_TYPE_REGULAR 0x1 224#define IXL_AQ_CONN_TYPE_DEFAULT 0x2 225#define IXL_AQ_CONN_TYPE_CASCADED 0x3 226 227 uint16_t scheduler_id; 228 uint16_t element_info; 229} __packed __aligned(4); 230 231#define IXL_PHY_TYPE_SGMII 0x00 232#define IXL_PHY_TYPE_1000BASE_KX 0x01 233#define IXL_PHY_TYPE_10GBASE_KX4 0x02 234#define IXL_PHY_TYPE_10GBASE_KR 0x03 235#define IXL_PHY_TYPE_40GBASE_KR4 0x04 236#define IXL_PHY_TYPE_XAUI 0x05 237#define IXL_PHY_TYPE_XFI 0x06 238#define IXL_PHY_TYPE_SFI 0x07 239#define IXL_PHY_TYPE_XLAUI 0x08 240#define IXL_PHY_TYPE_XLPPI 0x09 241#define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 242#define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 243#define IXL_PHY_TYPE_10GBASE_AOC 0x0c 244#define IXL_PHY_TYPE_40GBASE_AOC 0x0d 245#define IXL_PHY_TYPE_100BASE_TX 0x11 246#define IXL_PHY_TYPE_1000BASE_T 0x12 247#define IXL_PHY_TYPE_10GBASE_T 0x13 248#define IXL_PHY_TYPE_10GBASE_SR 0x14 249#define IXL_PHY_TYPE_10GBASE_LR 0x15 250#define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 251#define IXL_PHY_TYPE_10GBASE_CR1 0x17 252#define IXL_PHY_TYPE_40GBASE_CR4 0x18 253#define IXL_PHY_TYPE_40GBASE_SR4 0x19 254#define IXL_PHY_TYPE_40GBASE_LR4 0x1a 255#define IXL_PHY_TYPE_1000BASE_SX 0x1b 256#define IXL_PHY_TYPE_1000BASE_LX 0x1c 257#define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 258#define IXL_PHY_TYPE_20GBASE_KR2 0x1e 259 260#define IXL_PHY_TYPE_25GBASE_KR 0x1f 261#define IXL_PHY_TYPE_25GBASE_CR 0x20 262#define IXL_PHY_TYPE_25GBASE_SR 0x21 263#define IXL_PHY_TYPE_25GBASE_LR 0x22 264#define IXL_PHY_TYPE_25GBASE_AOC 0x23 265#define IXL_PHY_TYPE_25GBASE_ACC 0x24 266 267struct ixl_aq_module_desc { 268 uint8_t oui[3]; 269 uint8_t _reserved1; 270 uint8_t part_number[16]; 271 uint8_t revision[4]; 272 uint8_t _reserved2[8]; 273} __packed __aligned(4); 274 275struct ixl_aq_phy_abilities { 276 uint32_t phy_type; 277 278 uint8_t link_speed; 279#define IXL_AQ_PHY_LINK_SPEED_100MB (1 << 1) 280#define IXL_AQ_PHY_LINK_SPEED_1000MB (1 << 2) 281#define IXL_AQ_PHY_LINK_SPEED_10GB (1 << 3) 282#define IXL_AQ_PHY_LINK_SPEED_40GB (1 << 4) 283#define IXL_AQ_PHY_LINK_SPEED_20GB (1 << 5) 284#define IXL_AQ_PHY_LINK_SPEED_25GB (1 << 6) 285 uint8_t abilities; 286 uint16_t eee_capability; 287 288 uint32_t eeer_val; 289 290 uint8_t d3_lpan; 291 uint8_t phy_type_ext; 292#define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 293#define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 294#define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 295#define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 296 uint8_t fec_cfg_curr_mod_ext_info; 297#define IXL_AQ_ENABLE_FEC_KR 0x01 298#define IXL_AQ_ENABLE_FEC_RS 0x02 299#define IXL_AQ_REQUEST_FEC_KR 0x04 300#define IXL_AQ_REQUEST_FEC_RS 0x08 301#define IXL_AQ_ENABLE_FEC_AUTO 0x10 302#define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 303#define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 304 uint8_t ext_comp_code; 305 306 uint8_t phy_id[4]; 307 308 uint8_t module_type[3]; 309#define IXL_SFF8024_ID_SFP 0x03 310#define IXL_SFF8024_ID_QSFP 0x0c 311#define IXL_SFF8024_ID_QSFP_PLUS 0x0d 312#define IXL_SFF8024_ID_QSFP28 0x11 313 uint8_t qualified_module_count; 314#define IXL_AQ_PHY_MAX_QMS 16 315 struct ixl_aq_module_desc 316 qualified_module[IXL_AQ_PHY_MAX_QMS]; 317} __packed __aligned(4); 318 319struct ixl_aq_link_param { 320 uint8_t notify; 321#define IXL_AQ_LINK_NOTIFY 0x03 322 uint8_t _reserved1; 323 uint8_t phy; 324 uint8_t speed; 325 uint8_t status; 326 uint8_t _reserved2[11]; 327} __packed __aligned(4); 328 329struct ixl_aq_vsi_param { 330 uint16_t uplink_seid; 331 uint8_t connect_type; 332#define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 333#define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 334#define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 335 uint8_t _reserved1; 336 337 uint8_t vf_id; 338 uint8_t _reserved2; 339 uint16_t vsi_flags; 340#define IXL_AQ_VSI_TYPE_SHIFT 0x0 341#define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 342#define IXL_AQ_VSI_TYPE_VF 0x0 343#define IXL_AQ_VSI_TYPE_VMDQ2 0x1 344#define IXL_AQ_VSI_TYPE_PF 0x2 345#define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 346#define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 347 348 uint32_t addr_hi; 349 uint32_t addr_lo; 350} __packed __aligned(16); 351 352struct ixl_aq_add_macvlan { 353 uint16_t num_addrs; 354 uint16_t seid0; 355 uint16_t seid1; 356 uint16_t seid2; 357 uint32_t addr_hi; 358 uint32_t addr_lo; 359} __packed __aligned(16); 360 361struct ixl_aq_add_macvlan_elem { 362 uint8_t macaddr[6]; 363 uint16_t vlan; 364 uint16_t flags; 365#define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 366#define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 367 uint16_t queue; 368 uint32_t _reserved; 369} __packed __aligned(16); 370 371struct ixl_aq_remove_macvlan { 372 uint16_t num_addrs; 373 uint16_t seid0; 374 uint16_t seid1; 375 uint16_t seid2; 376 uint32_t addr_hi; 377 uint32_t addr_lo; 378} __packed __aligned(16); 379 380struct ixl_aq_remove_macvlan_elem { 381 uint8_t macaddr[6]; 382 uint16_t vlan; 383 uint8_t flags; 384#define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 385#define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 386 uint8_t _reserved[7]; 387} __packed __aligned(16); 388 389struct ixl_aq_vsi_reply { 390 uint16_t seid; 391 uint16_t vsi_number; 392 393 uint16_t vsis_used; 394 uint16_t vsis_free; 395 396 uint32_t addr_hi; 397 uint32_t addr_lo; 398} __packed __aligned(16); 399 400struct ixl_aq_vsi_data { 401 /* first 96 byte are written by SW */ 402 uint16_t valid_sections; 403#define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 404#define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 405#define IXL_AQ_VSI_VALID_VLAN (1 << 2) 406#define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 407#define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 408#define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 409#define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 410#define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 411#define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 412#define IXL_AQ_VSI_VALID_SCHED (1 << 9) 413 /* switch section */ 414 uint16_t switch_id; 415#define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 416#define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 417#define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 418#define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 419 420 uint8_t _reserved1[2]; 421 /* security section */ 422 uint8_t sec_flags; 423#define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 424#define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 425#define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 426 uint8_t _reserved2; 427 428 /* vlan section */ 429 uint16_t pvid; 430 uint16_t fcoe_pvid; 431 432 uint8_t port_vlan_flags; 433#define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 434#define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 435#define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 436#define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 437#define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 438#define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 439#define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 440#define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 441#define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 442#define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 443#define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 444#define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 445 uint8_t _reserved3[3]; 446 447 /* ingress egress up section */ 448 uint32_t ingress_table; 449#define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 450#define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 451 uint32_t egress_table; 452 453 /* cascaded pv section */ 454 uint16_t cas_pv_tag; 455 uint8_t cas_pv_flags; 456#define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 457#define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 458#define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 459#define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 460#define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 461#define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 462#define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 463#define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 464 (1 << 6) 465 uint8_t _reserved4; 466 467 /* queue mapping section */ 468 uint16_t mapping_flags; 469#define IXL_AQ_VSI_QUE_MAP_MASK 0x1 470#define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 471#define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 472 uint16_t queue_mapping[16]; 473#define IXL_AQ_VSI_QUEUE_SHIFT 0x0 474#define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 475 uint16_t tc_mapping[8]; 476#define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 477#define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 478#define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 479#define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 480 481 /* queueing option section */ 482 uint8_t queueing_opt_flags; 483#define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 484#define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 485#define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 486#define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 487#define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 488#define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 489 uint8_t _reserved5[3]; 490 491 /* scheduler section */ 492 uint8_t up_enable_bits; 493 uint8_t _reserved6; 494 495 /* outer up section */ 496 uint32_t outer_up_table; /* same as ingress/egress tables */ 497 uint8_t _reserved7[8]; 498 499 /* last 32 bytes are written by FW */ 500 uint16_t qs_handle[8]; 501#define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 502 uint16_t stat_counter_idx; 503 uint16_t sched_id; 504 505 uint8_t _reserved8[12]; 506} __packed __aligned(8); 507 508CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 509 510struct ixl_aq_vsi_promisc_param { 511 uint16_t flags; 512 uint16_t valid_flags; 513#define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 514#define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 515#define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 516#define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 517#define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 518#define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 519 520 uint16_t seid; 521#define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 522 uint16_t vlan; 523#define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 524 uint32_t reserved[2]; 525} __packed __aligned(8); 526 527struct ixl_aq_veb_param { 528 uint16_t uplink_seid; 529 uint16_t downlink_seid; 530 uint16_t veb_flags; 531#define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 532#define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 533#define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 534#define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 535 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 536#define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 537#define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 538#define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 539 uint8_t enable_tcs; 540 uint8_t _reserved[9]; 541} __packed __aligned(16); 542 543struct ixl_aq_veb_reply { 544 uint16_t _reserved1; 545 uint16_t _reserved2; 546 uint16_t _reserved3; 547 uint16_t switch_seid; 548 uint16_t veb_seid; 549#define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 550#define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 551#define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 552#define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 553 uint16_t statistic_index; 554 uint16_t vebs_used; 555 uint16_t vebs_free; 556} __packed __aligned(16); 557 558/* GET PHY ABILITIES param[0] */ 559#define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 560#define IXL_AQ_PHY_REPORT_INIT (1 << 1) 561 562struct ixl_aq_phy_reg_access { 563 uint8_t phy_iface; 564#define IXL_AQ_PHY_IF_INTERNAL 0 565#define IXL_AQ_PHY_IF_EXTERNAL 1 566#define IXL_AQ_PHY_IF_MODULE 2 567 uint8_t dev_addr; 568 uint16_t recall; 569#define IXL_AQ_PHY_QSFP_DEV_ADDR 0 570#define IXL_AQ_PHY_QSFP_LAST 1 571 uint32_t reg; 572 uint32_t val; 573 uint32_t _reserved2; 574} __packed __aligned(16); 575 576/* RESTART_AN param[0] */ 577#define IXL_AQ_PHY_RESTART_AN (1 << 1) 578#define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 579 580struct ixl_aq_link_status { /* this occupies the iaq_param space */ 581 uint16_t command_flags; /* only field set on command */ 582#define IXL_AQ_LSE_MASK 0x3 583#define IXL_AQ_LSE_NOP 0x0 584#define IXL_AQ_LSE_DISABLE 0x2 585#define IXL_AQ_LSE_ENABLE 0x3 586#define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 587 uint8_t phy_type; 588 uint8_t link_speed; 589#define IXL_AQ_LINK_SPEED_100MB (1 << 1) 590#define IXL_AQ_LINK_SPEED_1000MB (1 << 2) 591#define IXL_AQ_LINK_SPEED_10GB (1 << 3) 592#define IXL_AQ_LINK_SPEED_40GB (1 << 4) 593#define IXL_AQ_LINK_SPEED_25GB (1 << 6) 594 uint8_t link_info; 595#define IXL_AQ_LINK_UP_FUNCTION 0x01 596#define IXL_AQ_LINK_FAULT 0x02 597#define IXL_AQ_LINK_FAULT_TX 0x04 598#define IXL_AQ_LINK_FAULT_RX 0x08 599#define IXL_AQ_LINK_FAULT_REMOTE 0x10 600#define IXL_AQ_LINK_UP_PORT 0x20 601#define IXL_AQ_MEDIA_AVAILABLE 0x40 602#define IXL_AQ_SIGNAL_DETECT 0x80 603 uint8_t an_info; 604#define IXL_AQ_AN_COMPLETED 0x01 605#define IXL_AQ_LP_AN_ABILITY 0x02 606#define IXL_AQ_PD_FAULT 0x04 607#define IXL_AQ_FEC_EN 0x08 608#define IXL_AQ_PHY_LOW_POWER 0x10 609#define IXL_AQ_LINK_PAUSE_TX 0x20 610#define IXL_AQ_LINK_PAUSE_RX 0x40 611#define IXL_AQ_QUALIFIED_MODULE 0x80 612 613 uint8_t ext_info; 614#define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 615#define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 616#define IXL_AQ_LINK_TX_SHIFT 0x02 617#define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 618#define IXL_AQ_LINK_TX_ACTIVE 0x00 619#define IXL_AQ_LINK_TX_DRAINED 0x01 620#define IXL_AQ_LINK_TX_FLUSHED 0x03 621#define IXL_AQ_LINK_FORCED_40G 0x10 622/* 25G Error Codes */ 623#define IXL_AQ_25G_NO_ERR 0X00 624#define IXL_AQ_25G_NOT_PRESENT 0X01 625#define IXL_AQ_25G_NVM_CRC_ERR 0X02 626#define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 627#define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 628#define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 629 uint8_t loopback; 630 uint16_t max_frame_size; 631 632 uint8_t config; 633#define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 634#define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 635#define IXL_AQ_CONFIG_CRC_ENA 0x04 636#define IXL_AQ_CONFIG_PACING_MASK 0x78 637 uint8_t power_desc; 638#define IXL_AQ_LINK_POWER_CLASS_1 0x00 639#define IXL_AQ_LINK_POWER_CLASS_2 0x01 640#define IXL_AQ_LINK_POWER_CLASS_3 0x02 641#define IXL_AQ_LINK_POWER_CLASS_4 0x03 642#define IXL_AQ_PWR_CLASS_MASK 0x03 643 644 uint8_t reserved[4]; 645} __packed __aligned(4); 646 647/* event mask command flags for param[2] */ 648#define IXL_AQ_PHY_EV_MASK 0x3ff 649#define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 650#define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 651#define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 652#define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 653#define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 654#define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 655#define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 656#define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 657#define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 658 659/* aq response codes */ 660#define IXL_AQ_RC_OK 0 /* success */ 661#define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 662#define IXL_AQ_RC_ENOENT 2 /* No such element */ 663#define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 664#define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 665#define IXL_AQ_RC_EIO 5 /* I/O error */ 666#define IXL_AQ_RC_ENXIO 6 /* No such resource */ 667#define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 668#define IXL_AQ_RC_EAGAIN 8 /* Try again */ 669#define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 670#define IXL_AQ_RC_EACCES 10 /* Permission denied */ 671#define IXL_AQ_RC_EFAULT 11 /* Bad address */ 672#define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 673#define IXL_AQ_RC_EEXIST 13 /* object already exists */ 674#define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 675#define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 676#define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 677#define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 678#define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 679#define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 680#define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 681#define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 682#define IXL_AQ_RC_EFBIG 22 /* file too large */ 683 684struct ixl_tx_desc { 685 uint64_t addr; 686 uint64_t cmd; 687#define IXL_TX_DESC_DTYPE_SHIFT 0 688#define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 689#define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 690#define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 691#define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 692#define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 693#define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 694#define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 695#define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 696#define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 697#define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 698#define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 699 700#define IXL_TX_DESC_CMD_SHIFT 4 701#define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 702#define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 703#define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 704#define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 705#define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 706#define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 707#define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 708#define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 709#define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 710#define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 711#define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 712#define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 713#define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 714#define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 715#define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 716#define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 717#define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 718 719#define IXL_TX_DESC_MACLEN_SHIFT 16 720#define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 721#define IXL_TX_DESC_IPLEN_SHIFT 23 722#define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 723#define IXL_TX_DESC_L4LEN_SHIFT 30 724#define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 725#define IXL_TX_DESC_FCLEN_SHIFT 30 726#define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 727 728#define IXL_TX_DESC_BSIZE_SHIFT 34 729#define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 730#define IXL_TX_DESC_BSIZE_MASK \ 731 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 732} __packed __aligned(16); 733 734struct ixl_rx_rd_desc_16 { 735 uint64_t paddr; /* packet addr */ 736 uint64_t haddr; /* header addr */ 737} __packed __aligned(16); 738 739struct ixl_rx_rd_desc_32 { 740 uint64_t paddr; /* packet addr */ 741 uint64_t haddr; /* header addr */ 742 uint64_t _reserved1; 743 uint64_t _reserved2; 744} __packed __aligned(16); 745 746struct ixl_rx_wb_desc_16 { 747 uint64_t qword0; 748 uint64_t qword1; 749#define IXL_RX_DESC_DD (1 << 0) 750#define IXL_RX_DESC_EOP (1 << 1) 751#define IXL_RX_DESC_L2TAG1P (1 << 2) 752#define IXL_RX_DESC_L3L4P (1 << 3) 753#define IXL_RX_DESC_CRCP (1 << 4) 754#define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 755#define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 756#define IXL_RX_DESC_UMB_SHIFT 9 757#define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 758#define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 759#define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 760#define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 761#define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 762#define IXL_RX_DESC_FLM (1 << 11) 763#define IXL_RX_DESC_FLTSTAT_SHIFT 12 764#define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 765#define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 766#define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 767#define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 768#define IXL_RX_DESC_LPBK (1 << 14) 769#define IXL_RX_DESC_IPV6EXTADD (1 << 15) 770#define IXL_RX_DESC_INT_UDP_0 (1 << 18) 771 772#define IXL_RX_DESC_RXE (1 << 19) 773#define IXL_RX_DESC_HBO (1 << 21) 774#define IXL_RX_DESC_IPE (1 << 22) 775#define IXL_RX_DESC_L4E (1 << 23) 776#define IXL_RX_DESC_EIPE (1 << 24) 777#define IXL_RX_DESC_OVERSIZE (1 << 25) 778 779#define IXL_RX_DESC_PTYPE_SHIFT 30 780#define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 781 782#define IXL_RX_DESC_PLEN_SHIFT 38 783#define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 784#define IXL_RX_DESC_HLEN_SHIFT 42 785#define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 786} __packed __aligned(16); 787 788struct ixl_rx_wb_desc_32 { 789 uint64_t qword0; 790 uint64_t qword1; 791 uint64_t qword2; 792 uint64_t qword3; 793} __packed __aligned(16); 794 795enum i40e_mac_type { 796 I40E_MAC_XL710, 797 I40E_MAC_X722, 798 I40E_MAC_X722_VF, 799 I40E_MAC_VF, 800 I40E_MAC_GENERIC 801}; 802 803#endif 804