if_cas.c revision 1.38
1/* $NetBSD: if_cas.c,v 1.38 2020/01/30 05:24:53 thorpej Exp $ */ 2/* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4/* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34/* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46#include <sys/cdefs.h> 47__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.38 2020/01/30 05:24:53 thorpej Exp $"); 48 49#ifndef _MODULE 50#include "opt_inet.h" 51#endif 52 53#include <sys/param.h> 54#include <sys/systm.h> 55#include <sys/callout.h> 56#include <sys/mbuf.h> 57#include <sys/syslog.h> 58#include <sys/malloc.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/ioctl.h> 62#include <sys/errno.h> 63#include <sys/device.h> 64#include <sys/module.h> 65 66#include <machine/endian.h> 67 68#include <net/if.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71#include <net/if_ether.h> 72 73#ifdef INET 74#include <netinet/in.h> 75#include <netinet/in_systm.h> 76#include <netinet/in_var.h> 77#include <netinet/ip.h> 78#include <netinet/tcp.h> 79#include <netinet/udp.h> 80#endif 81 82#include <net/bpf.h> 83 84#include <sys/bus.h> 85#include <sys/intr.h> 86#include <sys/rndsource.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90#include <dev/mii/mii_bitbang.h> 91 92#include <dev/pci/pcivar.h> 93#include <dev/pci/pcireg.h> 94#include <dev/pci/pcidevs.h> 95#include <prop/proplib.h> 96 97#include <dev/pci/if_casreg.h> 98#include <dev/pci/if_casvar.h> 99 100#define TRIES 10000 101 102static bool cas_estintr(struct cas_softc *sc, int); 103bool cas_shutdown(device_t, int); 104static bool cas_suspend(device_t, const pmf_qual_t *); 105static bool cas_resume(device_t, const pmf_qual_t *); 106static int cas_detach(device_t, int); 107static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 108 109int cas_match(device_t, cfdata_t, void *); 110void cas_attach(device_t, device_t, void *); 111 112 113CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 114 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 115 DVF_DETACH_SHUTDOWN); 116 117int cas_pci_readvpd(struct cas_softc *, struct pci_attach_args *, uint8_t *); 118 119void cas_config(struct cas_softc *, const uint8_t *); 120void cas_start(struct ifnet *); 121void cas_stop(struct ifnet *, int); 122int cas_ioctl(struct ifnet *, u_long, void *); 123void cas_tick(void *); 124void cas_watchdog(struct ifnet *); 125int cas_init(struct ifnet *); 126void cas_init_regs(struct cas_softc *); 127int cas_ringsize(int); 128int cas_cringsize(int); 129int cas_meminit(struct cas_softc *); 130void cas_mifinit(struct cas_softc *); 131int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 132 uint32_t, uint32_t); 133void cas_reset(struct cas_softc *); 134int cas_reset_rx(struct cas_softc *); 135int cas_reset_tx(struct cas_softc *); 136int cas_disable_rx(struct cas_softc *); 137int cas_disable_tx(struct cas_softc *); 138void cas_rxdrain(struct cas_softc *); 139int cas_add_rxbuf(struct cas_softc *, int); 140void cas_iff(struct cas_softc *); 141int cas_encap(struct cas_softc *, struct mbuf *, uint32_t *); 142 143/* MII methods & callbacks */ 144int cas_mii_readreg(device_t, int, int, uint16_t*); 145int cas_mii_writereg(device_t, int, int, uint16_t); 146void cas_mii_statchg(struct ifnet *); 147int cas_pcs_readreg(device_t, int, int, uint16_t *); 148int cas_pcs_writereg(device_t, int, int, uint16_t); 149 150int cas_mediachange(struct ifnet *); 151void cas_mediastatus(struct ifnet *, struct ifmediareq *); 152 153int cas_eint(struct cas_softc *, u_int); 154int cas_rint(struct cas_softc *); 155int cas_tint(struct cas_softc *, uint32_t); 156int cas_pint(struct cas_softc *); 157int cas_intr(void *); 158 159#ifdef CAS_DEBUG 160#define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 161 printf x 162#else 163#define DPRINTF(sc, x) /* nothing */ 164#endif 165 166static const struct cas_pci_dev { 167 uint16_t cpd_vendor; 168 uint16_t cpd_device; 169 int cpd_variant; 170} cas_pci_devlist[] = { 171 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_CASSINI, CAS_CAS }, 172 { PCI_VENDOR_NS, PCI_PRODUCT_NS_SATURN, CAS_SATURN }, 173 { 0, 0, 0 } 174}; 175 176#define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 177#define CAS_PHY_INTERFACE "phy-interface" 178#define CAS_PHY_TYPE "phy-type" 179#define CAS_PHY_TYPE_PCS "pcs" 180 181int 182cas_match(device_t parent, cfdata_t cf, void *aux) 183{ 184 struct pci_attach_args *pa = aux; 185 int i; 186 187 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 188 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 189 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) 190 return 1; 191 } 192 193 return 0; 194} 195 196#define PROMHDR_PTR_DATA 0x18 197#define PROMDATA_PTR_VPD 0x08 198#define PROMDATA_DATA2 0x0a 199 200static const uint8_t cas_promhdr[] = { 0x55, 0xaa }; 201static const uint8_t cas_promdat[] = { 202 'P', 'C', 'I', 'R', 203 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 204 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 205}; 206static const uint8_t cas_promdat_ns[] = { 207 'P', 'C', 'I', 'R', 208 PCI_VENDOR_NS & 0xff, PCI_VENDOR_NS >> 8, 209 PCI_PRODUCT_NS_SATURN & 0xff, PCI_PRODUCT_NS_SATURN >> 8 210}; 211 212static const uint8_t cas_promdat2[] = { 213 0x18, 0x00, /* structure length */ 214 0x00, /* structure revision */ 215 0x00, /* interface revision */ 216 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 217 PCI_CLASS_NETWORK /* class code */ 218}; 219 220#define CAS_LMA_MAXNUM 4 221int 222cas_pci_readvpd(struct cas_softc *sc, struct pci_attach_args *pa, 223 uint8_t *enaddr) 224{ 225 struct pci_vpd_largeres *res; 226 struct pci_vpd *vpd; 227 bus_space_handle_t romh; 228 bus_space_tag_t romt; 229 bus_size_t romsize = 0; 230 uint8_t enaddrs[CAS_LMA_MAXNUM][ETHER_ADDR_LEN]; 231 bool pcs[4] = {false, false, false, false}; 232 uint8_t buf[32], *desc; 233 pcireg_t address; 234 int dataoff, vpdoff, len, lma = 0, phy = 0; 235 int i, rv = -1; 236 237 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 238 &romt, &romh, NULL, &romsize)) 239 return (-1); 240 241 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 242 address |= PCI_MAPREG_ROM_ENABLE; 243 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 244 245 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 246 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 247 goto fail; 248 249 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 250 if (dataoff < 0x1c) 251 goto fail; 252 253 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 254 if ((bcmp(buf, cas_promdat, sizeof(cas_promdat)) && 255 bcmp(buf, cas_promdat_ns, sizeof(cas_promdat_ns))) || 256 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 257 goto fail; 258 259 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 260 if (vpdoff < 0x1c) 261 goto fail; 262 263next: 264 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 265 if (!PCI_VPDRES_ISLARGE(buf[0])) 266 goto fail; 267 268 res = (struct pci_vpd_largeres *)buf; 269 vpdoff += sizeof(*res); 270 271 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 272 switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 273 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 274 /* Skip identifier string. */ 275 vpdoff += len; 276 goto next; 277 278 case PCI_VPDRES_TYPE_VPD: 279#ifdef CAS_DEBUG 280 printf("\n"); 281 for (i = 0; i < len; i++) { 282 uint8_t byte; 283 if (i % 16 == 0) 284 printf("%04x :", i); 285 byte = bus_space_read_1(romt, romh, vpdoff + i); 286 printf(" %02x", byte); 287 if (i % 16 == 15) 288 printf("\n"); 289 } 290 printf("\n"); 291#endif 292 293 while (len > 0) { 294 bus_space_read_region_1(romt, romh, vpdoff, 295 buf, sizeof(buf)); 296 297 vpd = (struct pci_vpd *)buf; 298 vpdoff += sizeof(*vpd) + vpd->vpd_len; 299 len -= sizeof(*vpd) + vpd->vpd_len; 300 301 /* 302 * We're looking for an "Enhanced" VPD... 303 */ 304 if (vpd->vpd_key0 != 'Z') 305 continue; 306 307 desc = buf + sizeof(*vpd); 308 309 /* 310 * ...which is an instance property... 311 */ 312 if (desc[0] != 'I') 313 continue; 314 desc += 3; 315 316 if (desc[0] == 'B' || desc[1] == ETHER_ADDR_LEN) { 317 /* 318 * ...that's a byte array with the proper 319 * length for a MAC address... 320 */ 321 desc += 2; 322 323 /* 324 * ...named "local-mac-address". 325 */ 326 if (strcmp(desc, CAS_LOCAL_MAC_ADDRESS) != 0) 327 continue; 328 desc += sizeof(CAS_LOCAL_MAC_ADDRESS); 329 330 if (lma == CAS_LMA_MAXNUM) 331 continue; 332 333 memcpy(enaddrs[lma], desc, ETHER_ADDR_LEN); 334 lma++; 335 rv = 0; 336 continue; 337 } else if (desc[0] == 'S') { 338 size_t k; 339 340 /* String */ 341 desc += 2; 342#ifdef CAS_DEBUG 343 /* ...named "pcs". */ 344 printf("STR: \"%s\"\n", desc); 345 if (strcmp(desc, CAS_PHY_TYPE_PCS) != 0) 346 continue; 347 desc += sizeof(CAS_PHY_TYPE_PCS); 348 printf("STR: \"%s\"\n", desc); 349#endif 350 /* ...named "phy-interface" or "phy-type". */ 351 if (strcmp(desc, CAS_PHY_INTERFACE) == 0) 352 k = sizeof(CAS_PHY_INTERFACE); 353 else if (strcmp(desc, CAS_PHY_TYPE) == 0) 354 k = sizeof(CAS_PHY_TYPE); 355 else 356 continue; 357 358 desc += k; 359#ifdef CAS_DEBUG 360 printf("STR: \"%s\"\n", desc); 361#endif 362 if (strcmp(desc, CAS_PHY_TYPE_PCS) == 0) 363 pcs[phy] = true; 364 phy++; 365 continue; 366 } 367 } 368 break; 369 370 default: 371 goto fail; 372 } 373 374 /* 375 * Multi port card has bridge chip. The device number is fixed: 376 * e.g. 377 * p0: 005:00:0 378 * p1: 005:01:0 379 * p2: 006:02:0 380 * p3: 006:03:0 381 */ 382 if (enaddr != 0) { 383 i = 0; 384 if ((lma > 1) && (pa->pa_device < CAS_LMA_MAXNUM) 385 && (pa->pa_device < lma)) 386 i = pa->pa_device; 387 memcpy(enaddr, enaddrs[i], ETHER_ADDR_LEN); 388 } 389 if (pcs[pa->pa_device]) 390 sc->sc_flags |= CAS_SERDES; 391 fail: 392 if (romsize != 0) 393 bus_space_unmap(romt, romh, romsize); 394 395 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 396 address &= ~PCI_MAPREG_ROM_ENABLE; 397 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 398 399 return (rv); 400} 401 402void 403cas_attach(device_t parent, device_t self, void *aux) 404{ 405 struct pci_attach_args *pa = aux; 406 struct cas_softc *sc = device_private(self); 407 int i; 408 prop_data_t data; 409 uint8_t enaddr[ETHER_ADDR_LEN]; 410 411 sc->sc_dev = self; 412 pci_aprint_devinfo(pa, NULL); 413 sc->sc_rev = PCI_REVISION(pa->pa_class); 414 sc->sc_dmatag = pa->pa_dmat; 415 416 sc->sc_variant = CAS_UNKNOWN; 417 for (i = 0; cas_pci_devlist[i].cpd_vendor != 0; i++) { 418 if ((PCI_VENDOR(pa->pa_id) == cas_pci_devlist[i].cpd_vendor) && 419 (PCI_PRODUCT(pa->pa_id) == cas_pci_devlist[i].cpd_device)) { 420 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 421 break; 422 } 423 } 424 aprint_debug_dev(sc->sc_dev, "variant = %d\n", sc->sc_variant); 425 if (sc->sc_variant == CAS_UNKNOWN) { 426 aprint_error_dev(sc->sc_dev, "unknown adaptor\n"); 427 return; 428 } 429 430#define PCI_CAS_BASEADDR 0x10 431 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 432 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 433 aprint_error_dev(sc->sc_dev, 434 "unable to map device registers\n"); 435 return; 436 } 437 438 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 439 "mac-address")) != NULL) 440 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 441 if (cas_pci_readvpd(sc, pa, (data == NULL) ? enaddr : 0) != 0) { 442 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 443 memset(enaddr, 0, sizeof(enaddr)); 444 } 445 446 sc->sc_burst = 16; /* XXX */ 447 448 sc->sc_att_stage = CAS_ATT_BACKEND_0; 449 450 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 451 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 452 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 453 return; 454 } 455 sc->sc_pc = pa->pa_pc; 456 if (!cas_estintr(sc, CAS_INTR_PCI)) { 457 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 458 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 459 return; 460 } 461 462 sc->sc_att_stage = CAS_ATT_BACKEND_1; 463 464 /* 465 * call the main configure 466 */ 467 cas_config(sc, enaddr); 468 469 if (pmf_device_register1(sc->sc_dev, 470 cas_suspend, cas_resume, cas_shutdown)) 471 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 472 else 473 aprint_error_dev(sc->sc_dev, 474 "could not establish power handlers\n"); 475 476 sc->sc_att_stage = CAS_ATT_FINISHED; 477 /*FALLTHROUGH*/ 478} 479 480/* 481 * cas_config: 482 * 483 * Attach a Cassini interface to the system. 484 */ 485void 486cas_config(struct cas_softc *sc, const uint8_t *enaddr) 487{ 488 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 489 struct mii_data *mii = &sc->sc_mii; 490 struct mii_softc *child; 491 uint32_t reg; 492 int i, error; 493 494 /* Make sure the chip is stopped. */ 495 ifp->if_softc = sc; 496 cas_reset(sc); 497 498 /* 499 * Allocate the control data structures, and create and load the 500 * DMA map for it. 501 */ 502 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 503 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 504 1, &sc->sc_cdnseg, 0)) != 0) { 505 aprint_error_dev(sc->sc_dev, 506 "unable to allocate control data, error = %d\n", 507 error); 508 cas_partial_detach(sc, CAS_ATT_0); 509 } 510 511 /* XXX should map this in with correct endianness */ 512 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, 513 sc->sc_cdnseg, sizeof(struct cas_control_data), 514 (void **)&sc->sc_control_data, BUS_DMA_COHERENT)) != 0) { 515 aprint_error_dev(sc->sc_dev, 516 "unable to map control data, error = %d\n", error); 517 cas_partial_detach(sc, CAS_ATT_1); 518 } 519 520 if ((error = bus_dmamap_create(sc->sc_dmatag, 521 sizeof(struct cas_control_data), 1, 522 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "unable to create control data DMA map, error = %d\n", 525 error); 526 cas_partial_detach(sc, CAS_ATT_2); 527 } 528 529 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 530 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 531 0)) != 0) { 532 aprint_error_dev(sc->sc_dev, 533 "unable to load control data DMA map, error = %d\n", 534 error); 535 cas_partial_detach(sc, CAS_ATT_3); 536 } 537 538 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 539 540 /* 541 * Create the receive buffer DMA maps. 542 */ 543 for (i = 0; i < CAS_NRXDESC; i++) { 544 bus_dma_segment_t seg; 545 char *kva; 546 int rseg; 547 548 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 549 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 550 aprint_error_dev(sc->sc_dev, 551 "unable to alloc rx DMA mem %d, error = %d\n", 552 i, error); 553 cas_partial_detach(sc, CAS_ATT_5); 554 } 555 sc->sc_rxsoft[i].rxs_dmaseg = seg; 556 557 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 558 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 559 aprint_error_dev(sc->sc_dev, 560 "unable to alloc rx DMA mem %d, error = %d\n", 561 i, error); 562 cas_partial_detach(sc, CAS_ATT_5); 563 } 564 sc->sc_rxsoft[i].rxs_kva = kva; 565 566 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 567 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 568 aprint_error_dev(sc->sc_dev, 569 "unable to create rx DMA map %d, error = %d\n", 570 i, error); 571 cas_partial_detach(sc, CAS_ATT_5); 572 } 573 574 if ((error = bus_dmamap_load(sc->sc_dmatag, 575 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 576 BUS_DMA_NOWAIT)) != 0) { 577 aprint_error_dev(sc->sc_dev, 578 "unable to load rx DMA map %d, error = %d\n", 579 i, error); 580 cas_partial_detach(sc, CAS_ATT_5); 581 } 582 } 583 584 /* 585 * Create the transmit buffer DMA maps. 586 */ 587 for (i = 0; i < CAS_NTXDESC; i++) { 588 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 589 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 590 &sc->sc_txd[i].sd_map)) != 0) { 591 aprint_error_dev(sc->sc_dev, 592 "unable to create tx DMA map %d, error = %d\n", 593 i, error); 594 cas_partial_detach(sc, CAS_ATT_6); 595 } 596 sc->sc_txd[i].sd_mbuf = NULL; 597 } 598 599 /* 600 * From this point forward, the attachment cannot fail. A failure 601 * before this point releases all resources that may have been 602 * allocated. 603 */ 604 605 /* Announce ourselves. */ 606 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 607 ether_sprintf(enaddr)); 608 aprint_naive(": Ethernet controller\n"); 609 610 /* Get RX FIFO size */ 611 sc->sc_rxfifosize = 16 * 1024; 612 613 /* Initialize ifnet structure. */ 614 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 615 ifp->if_softc = sc; 616 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 617 ifp->if_start = cas_start; 618 ifp->if_ioctl = cas_ioctl; 619 ifp->if_watchdog = cas_watchdog; 620 ifp->if_stop = cas_stop; 621 ifp->if_init = cas_init; 622 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 623 IFQ_SET_READY(&ifp->if_snd); 624 625 /* Initialize ifmedia structures and MII info */ 626 mii->mii_ifp = ifp; 627 mii->mii_readreg = cas_mii_readreg; 628 mii->mii_writereg = cas_mii_writereg; 629 mii->mii_statchg = cas_mii_statchg; 630 631 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 632 sc->sc_ethercom.ec_mii = mii; 633 634 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 635 636 cas_mifinit(sc); 637 638 if (sc->sc_mif_config & (CAS_MIF_CONFIG_MDI1 | CAS_MIF_CONFIG_MDI0)) { 639 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 640 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 641 bus_space_write_4(sc->sc_memt, sc->sc_memh, 642 CAS_MIF_CONFIG, sc->sc_mif_config); 643 } 644 /* Enable/unfreeze the GMII pins of Saturn. */ 645 if (sc->sc_variant == CAS_SATURN) { 646 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, 647 CAS_SATURN_PCFG) & ~CAS_SATURN_PCFG_FSI; 648 if ((sc->sc_mif_config & CAS_MIF_CONFIG_MDI0) != 0) 649 reg |= CAS_SATURN_PCFG_FSI; 650 bus_space_write_4(sc->sc_memt, sc->sc_memh, 651 CAS_SATURN_PCFG, reg); 652 /* Read to flush */ 653 bus_space_read_4(sc->sc_memt, sc->sc_memh, 654 CAS_SATURN_PCFG); 655 DELAY(10000); 656 } 657 } 658 659 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 660 MII_OFFSET_ANY, 0); 661 662 child = LIST_FIRST(&mii->mii_phys); 663 if (child == NULL && 664 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) { 665 /* 666 * Try the external PCS SERDES if we didn't find any 667 * MII devices. 668 */ 669 bus_space_write_4(sc->sc_memt, sc->sc_memh, 670 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 671 672 bus_space_write_4(sc->sc_memt, sc->sc_memh, 673 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 674 675 mii->mii_readreg = cas_pcs_readreg; 676 mii->mii_writereg = cas_pcs_writereg; 677 678 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 679 MII_OFFSET_ANY, MIIF_NOISOLATE); 680 } 681 682 child = LIST_FIRST(&mii->mii_phys); 683 if (child == NULL) { 684 /* No PHY attached */ 685 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 686 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL); 687 } else { 688 /* 689 * Walk along the list of attached MII devices and 690 * establish an `MII instance' to `phy number' 691 * mapping. We'll use this mapping in media change 692 * requests to determine which phy to use to program 693 * the MIF configuration register. 694 */ 695 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 696 /* 697 * Note: we support just two PHYs: the built-in 698 * internal device and an external on the MII 699 * connector. 700 */ 701 if (child->mii_phy > 1 || child->mii_inst > 1) { 702 aprint_error_dev(sc->sc_dev, 703 "cannot accommodate MII device %s" 704 " at phy %d, instance %d\n", 705 device_xname(child->mii_dev), 706 child->mii_phy, child->mii_inst); 707 continue; 708 } 709 710 sc->sc_phys[child->mii_inst] = child->mii_phy; 711 } 712 713 /* 714 * XXX - we can really do the following ONLY if the 715 * phy indeed has the auto negotiation capability!! 716 */ 717 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 718 } 719 720 /* claim 802.1q capability */ 721 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 722 723 /* Attach the interface. */ 724 if_attach(ifp); 725 if_deferred_start_init(ifp, NULL); 726 ether_ifattach(ifp, enaddr); 727 728 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 729 RND_TYPE_NET, RND_FLAG_DEFAULT); 730 731 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 732 NULL, device_xname(sc->sc_dev), "interrupts"); 733 734 callout_init(&sc->sc_tick_ch, 0); 735 736 return; 737} 738 739int 740cas_detach(device_t self, int flags) 741{ 742 int i; 743 struct cas_softc *sc = device_private(self); 744 bus_space_tag_t t = sc->sc_memt; 745 bus_space_handle_t h = sc->sc_memh; 746 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 747 748 /* 749 * Free any resources we've allocated during the failed attach 750 * attempt. Do this in reverse order and fall through. 751 */ 752 switch (sc->sc_att_stage) { 753 case CAS_ATT_FINISHED: 754 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 755 pmf_device_deregister(self); 756 cas_stop(&sc->sc_ethercom.ec_if, 1); 757 evcnt_detach(&sc->sc_ev_intr); 758 759 rnd_detach_source(&sc->rnd_source); 760 761 ether_ifdetach(ifp); 762 if_detach(ifp); 763 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 764 765 callout_destroy(&sc->sc_tick_ch); 766 767 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 768 769 /*FALLTHROUGH*/ 770 case CAS_ATT_MII: 771 case CAS_ATT_7: 772 case CAS_ATT_6: 773 for (i = 0; i < CAS_NTXDESC; i++) { 774 if (sc->sc_txd[i].sd_map != NULL) 775 bus_dmamap_destroy(sc->sc_dmatag, 776 sc->sc_txd[i].sd_map); 777 } 778 /*FALLTHROUGH*/ 779 case CAS_ATT_5: 780 for (i = 0; i < CAS_NRXDESC; i++) { 781 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 782 bus_dmamap_unload(sc->sc_dmatag, 783 sc->sc_rxsoft[i].rxs_dmamap); 784 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 785 bus_dmamap_destroy(sc->sc_dmatag, 786 sc->sc_rxsoft[i].rxs_dmamap); 787 if (sc->sc_rxsoft[i].rxs_kva != NULL) 788 bus_dmamem_unmap(sc->sc_dmatag, 789 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 790 /* XXX need to check that bus_dmamem_alloc suceeded 791 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 792 */ 793 bus_dmamem_free(sc->sc_dmatag, 794 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 795 } 796 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 797 /*FALLTHROUGH*/ 798 case CAS_ATT_4: 799 case CAS_ATT_3: 800 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 801 /*FALLTHROUGH*/ 802 case CAS_ATT_2: 803 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 804 sizeof(struct cas_control_data)); 805 /*FALLTHROUGH*/ 806 case CAS_ATT_1: 807 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 808 /*FALLTHROUGH*/ 809 case CAS_ATT_0: 810 sc->sc_att_stage = CAS_ATT_0; 811 /*FALLTHROUGH*/ 812 case CAS_ATT_BACKEND_2: 813 case CAS_ATT_BACKEND_1: 814 if (sc->sc_ih != NULL) { 815 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 816 sc->sc_ih = NULL; 817 } 818 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 819 /*FALLTHROUGH*/ 820 case CAS_ATT_BACKEND_0: 821 break; 822 } 823 return 0; 824} 825 826static void 827cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 828{ 829 cfattach_t ca = device_cfattach(sc->sc_dev); 830 831 sc->sc_att_stage = stage; 832 (*ca->ca_detach)(sc->sc_dev, 0); 833} 834 835void 836cas_tick(void *arg) 837{ 838 struct cas_softc *sc = arg; 839 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 840 bus_space_tag_t t = sc->sc_memt; 841 bus_space_handle_t mac = sc->sc_memh; 842 int s; 843 uint32_t v; 844 845 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 846 847 /* unload collisions counters */ 848 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 849 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 850 if_statadd_ref(nsr, if_collisions, v + 851 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 852 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT)); 853 if_statadd_ref(nsr, if_oerrors, v); 854 855 /* read error counters */ 856 if_statadd_ref(nsr, if_ierrors, 857 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 858 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 859 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 860 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL)); 861 862 IF_STAT_PUTREF(ifp); 863 864 /* clear the hardware counters */ 865 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 866 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 867 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 868 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 869 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 870 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 871 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 872 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 873 874 s = splnet(); 875 mii_tick(&sc->sc_mii); 876 splx(s); 877 878 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 879} 880 881int 882cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 883 uint32_t clr, uint32_t set) 884{ 885 int i; 886 uint32_t reg; 887 888 for (i = TRIES; i--; DELAY(100)) { 889 reg = bus_space_read_4(sc->sc_memt, h, r); 890 if ((reg & clr) == 0 && (reg & set) == set) 891 return (1); 892 } 893 894 return (0); 895} 896 897void 898cas_reset(struct cas_softc *sc) 899{ 900 bus_space_tag_t t = sc->sc_memt; 901 bus_space_handle_t h = sc->sc_memh; 902 int s; 903 904 s = splnet(); 905 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 906 cas_reset_rx(sc); 907 cas_reset_tx(sc); 908 909 /* Disable interrupts */ 910 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 911 912 /* Do a full reset */ 913 bus_space_write_4(t, h, CAS_RESET, 914 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 915 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 916 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 917 splx(s); 918} 919 920 921/* 922 * cas_rxdrain: 923 * 924 * Drain the receive queue. 925 */ 926void 927cas_rxdrain(struct cas_softc *sc) 928{ 929 /* Nothing to do yet. */ 930} 931 932/* 933 * Reset the whole thing. 934 */ 935void 936cas_stop(struct ifnet *ifp, int disable) 937{ 938 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 939 struct cas_sxd *sd; 940 uint32_t i; 941 942 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 943 944 callout_stop(&sc->sc_tick_ch); 945 946 /* 947 * Mark the interface down and cancel the watchdog timer. 948 */ 949 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 950 ifp->if_timer = 0; 951 952 mii_down(&sc->sc_mii); 953 954 cas_reset_rx(sc); 955 cas_reset_tx(sc); 956 957 /* 958 * Release any queued transmit buffers. 959 */ 960 for (i = 0; i < CAS_NTXDESC; i++) { 961 sd = &sc->sc_txd[i]; 962 if (sd->sd_mbuf != NULL) { 963 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 964 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 965 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 966 m_freem(sd->sd_mbuf); 967 sd->sd_mbuf = NULL; 968 } 969 } 970 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 971 972 if (disable) 973 cas_rxdrain(sc); 974} 975 976 977/* 978 * Reset the receiver 979 */ 980int 981cas_reset_rx(struct cas_softc *sc) 982{ 983 bus_space_tag_t t = sc->sc_memt; 984 bus_space_handle_t h = sc->sc_memh; 985 986 /* 987 * Resetting while DMA is in progress can cause a bus hang, so we 988 * disable DMA first. 989 */ 990 cas_disable_rx(sc); 991 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 992 /* Wait till it finishes */ 993 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 994 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 995 /* Wait 5ms extra. */ 996 delay(5000); 997 998 /* Finally, reset the ERX */ 999 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 1000 /* Wait till it finishes */ 1001 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 1002 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 1003 return (1); 1004 } 1005 return (0); 1006} 1007 1008 1009/* 1010 * Reset the transmitter 1011 */ 1012int 1013cas_reset_tx(struct cas_softc *sc) 1014{ 1015 bus_space_tag_t t = sc->sc_memt; 1016 bus_space_handle_t h = sc->sc_memh; 1017 1018 /* 1019 * Resetting while DMA is in progress can cause a bus hang, so we 1020 * disable DMA first. 1021 */ 1022 cas_disable_tx(sc); 1023 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 1024 /* Wait till it finishes */ 1025 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 1026 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 1027 /* Wait 5ms extra. */ 1028 delay(5000); 1029 1030 /* Finally, reset the ETX */ 1031 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 1032 /* Wait till it finishes */ 1033 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 1034 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 1035 return (1); 1036 } 1037 return (0); 1038} 1039 1040/* 1041 * Disable receiver. 1042 */ 1043int 1044cas_disable_rx(struct cas_softc *sc) 1045{ 1046 bus_space_tag_t t = sc->sc_memt; 1047 bus_space_handle_t h = sc->sc_memh; 1048 uint32_t cfg; 1049 1050 /* Flip the enable bit */ 1051 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1052 cfg &= ~CAS_MAC_RX_ENABLE; 1053 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 1054 1055 /* Wait for it to finish */ 1056 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 1057} 1058 1059/* 1060 * Disable transmitter. 1061 */ 1062int 1063cas_disable_tx(struct cas_softc *sc) 1064{ 1065 bus_space_tag_t t = sc->sc_memt; 1066 bus_space_handle_t h = sc->sc_memh; 1067 uint32_t cfg; 1068 1069 /* Flip the enable bit */ 1070 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 1071 cfg &= ~CAS_MAC_TX_ENABLE; 1072 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 1073 1074 /* Wait for it to finish */ 1075 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 1076} 1077 1078/* 1079 * Initialize interface. 1080 */ 1081int 1082cas_meminit(struct cas_softc *sc) 1083{ 1084 int i; 1085 1086 /* 1087 * Initialize the transmit descriptor ring. 1088 */ 1089 for (i = 0; i < CAS_NTXDESC; i++) { 1090 sc->sc_txdescs[i].cd_flags = 0; 1091 sc->sc_txdescs[i].cd_addr = 0; 1092 } 1093 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 1094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1095 1096 /* 1097 * Initialize the receive descriptor and receive job 1098 * descriptor rings. 1099 */ 1100 for (i = 0; i < CAS_NRXDESC; i++) 1101 CAS_INIT_RXDESC(sc, i, i); 1102 sc->sc_rxdptr = 0; 1103 sc->sc_rxptr = 0; 1104 1105 /* 1106 * Initialize the receive completion ring. 1107 */ 1108 for (i = 0; i < CAS_NRXCOMP; i++) { 1109 sc->sc_rxcomps[i].cc_word[0] = 0; 1110 sc->sc_rxcomps[i].cc_word[1] = 0; 1111 sc->sc_rxcomps[i].cc_word[2] = 0; 1112 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 1113 CAS_CDRXCSYNC(sc, i, 1114 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1115 } 1116 1117 return (0); 1118} 1119 1120int 1121cas_ringsize(int sz) 1122{ 1123 switch (sz) { 1124 case 32: 1125 return CAS_RING_SZ_32; 1126 case 64: 1127 return CAS_RING_SZ_64; 1128 case 128: 1129 return CAS_RING_SZ_128; 1130 case 256: 1131 return CAS_RING_SZ_256; 1132 case 512: 1133 return CAS_RING_SZ_512; 1134 case 1024: 1135 return CAS_RING_SZ_1024; 1136 case 2048: 1137 return CAS_RING_SZ_2048; 1138 case 4096: 1139 return CAS_RING_SZ_4096; 1140 case 8192: 1141 return CAS_RING_SZ_8192; 1142 default: 1143 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1144 sz); 1145 return CAS_RING_SZ_32; 1146 } 1147} 1148 1149int 1150cas_cringsize(int sz) 1151{ 1152 int i; 1153 1154 for (i = 0; i < 9; i++) 1155 if (sz == (128 << i)) 1156 return i; 1157 1158 aprint_error("cas: invalid completion ring size %d\n", sz); 1159 return 128; 1160} 1161 1162/* 1163 * Initialization of interface; set up initialization block 1164 * and transmit/receive descriptor rings. 1165 */ 1166int 1167cas_init(struct ifnet *ifp) 1168{ 1169 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1170 bus_space_tag_t t = sc->sc_memt; 1171 bus_space_handle_t h = sc->sc_memh; 1172 int s; 1173 u_int max_frame_size; 1174 uint32_t v; 1175 1176 s = splnet(); 1177 1178 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1179 /* 1180 * Initialization sequence. The numbered steps below correspond 1181 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1182 * Channel Engine manual (part of the PCIO manual). 1183 * See also the STP2002-STQ document from Sun Microsystems. 1184 */ 1185 1186 /* step 1 & 2. Reset the Ethernet Channel */ 1187 cas_stop(ifp, 0); 1188 cas_reset(sc); 1189 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1190 1191 /* Re-initialize the MIF */ 1192 cas_mifinit(sc); 1193 1194 /* step 3. Setup data structures in host memory */ 1195 cas_meminit(sc); 1196 1197 /* step 4. TX MAC registers & counters */ 1198 cas_init_regs(sc); 1199 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1200 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1201 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1202 1203 /* step 5. RX MAC registers & counters */ 1204 cas_iff(sc); 1205 1206 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1207 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1208 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1209 (((uint64_t)CAS_CDTXADDR(sc, 0)) >> 32)); 1210 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1211 1212 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1213 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1214 (((uint64_t)CAS_CDRXADDR(sc, 0)) >> 32)); 1215 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1216 1217 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1218 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1219 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1220 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1221 1222 if (CAS_PLUS(sc)) { 1223 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1224 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1225 (((uint64_t)CAS_CDRXADDR2(sc, 0)) >> 32)); 1226 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1227 CAS_CDRXADDR2(sc, 0)); 1228 } 1229 1230 /* step 8. Global Configuration & Interrupt Mask */ 1231 cas_estintr(sc, CAS_INTR_REG); 1232 1233 /* step 9. ETX Configuration: use mostly default values */ 1234 1235 /* Enable DMA */ 1236 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1237 bus_space_write_4(t, h, CAS_TX_CONFIG, 1238 v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29)); 1239 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1240 1241 /* step 10. ERX Configuration */ 1242 1243 /* Encode Receive Descriptor ring size */ 1244 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1245 if (CAS_PLUS(sc)) 1246 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1247 1248 /* Encode Receive Completion ring size */ 1249 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1250 1251 /* Enable DMA */ 1252 bus_space_write_4(t, h, CAS_RX_CONFIG, 1253 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN); 1254 1255 /* 1256 * The following value is for an OFF Threshold of about 3/4 full 1257 * and an ON Threshold of 1/4 full. 1258 */ 1259 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1260 (3 * sc->sc_rxfifosize / 256) | 1261 ((sc->sc_rxfifosize / 256) << 12)); 1262 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1263 1264 /* step 11. Configure Media */ 1265 mii_ifmedia_change(&sc->sc_mii); 1266 1267 /* step 12. RX_MAC Configuration Register */ 1268 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1269 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1270 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1271 1272 /* step 14. Issue Transmit Pending command */ 1273 1274 /* step 15. Give the receiver a swift kick */ 1275 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1276 if (CAS_PLUS(sc)) 1277 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1278 1279 /* Start the one second timer. */ 1280 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1281 1282 ifp->if_flags |= IFF_RUNNING; 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 ifp->if_timer = 0; 1285 splx(s); 1286 1287 return (0); 1288} 1289 1290void 1291cas_init_regs(struct cas_softc *sc) 1292{ 1293 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1294 bus_space_tag_t t = sc->sc_memt; 1295 bus_space_handle_t h = sc->sc_memh; 1296 const u_char *laddr = CLLADDR(ifp->if_sadl); 1297 uint32_t v, r; 1298 1299 /* These regs are not cleared on reset */ 1300 sc->sc_inited = 0; 1301 if (!sc->sc_inited) { 1302 /* Load recommended values */ 1303 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1304 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1305 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1306 1307 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1308 /* Max frame and max burst size */ 1309 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1310 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1311 1312 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1313 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1314 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1315 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1316 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1317 ((laddr[5]<<8)|laddr[4])&0x3ff); 1318 1319 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1320 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1321 bus_space_write_4(t, h, r, 0); 1322 1323 /* MAC control addr set to 0:1:c2:0:1:80 */ 1324 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1325 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1326 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1327 1328 /* MAC filter addr set to 0:0:0:0:0:0 */ 1329 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1330 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1331 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1332 1333 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1334 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1335 1336 /* Hash table initialized to 0 */ 1337 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1338 bus_space_write_4(t, h, r, 0); 1339 1340 sc->sc_inited = 1; 1341 } 1342 1343 /* Counters need to be zeroed */ 1344 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1345 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1346 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1347 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1348 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1349 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1350 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1351 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1352 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1353 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1354 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1355 1356 /* Un-pause stuff */ 1357 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1358 1359 /* 1360 * Set the station address. 1361 */ 1362 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1363 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1364 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1365} 1366 1367/* 1368 * Receive interrupt. 1369 */ 1370int 1371cas_rint(struct cas_softc *sc) 1372{ 1373 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1374 bus_space_tag_t t = sc->sc_memt; 1375 bus_space_handle_t h = sc->sc_memh; 1376 struct cas_rxsoft *rxs; 1377 struct mbuf *m; 1378 uint64_t word[4]; 1379 int len, off, idx; 1380 int i, skip; 1381 void *cp; 1382 1383 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1384 CAS_CDRXCSYNC(sc, i, 1385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1386 1387 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1388 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1389 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1390 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1391 1392 /* Stop if the hardware still owns the descriptor. */ 1393 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1394 break; 1395 1396 len = CAS_RC1_HDR_LEN(word[1]); 1397 if (len > 0) { 1398 off = CAS_RC1_HDR_OFF(word[1]); 1399 idx = CAS_RC1_HDR_IDX(word[1]); 1400 rxs = &sc->sc_rxsoft[idx]; 1401 1402 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1403 idx, off, len)); 1404 1405 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1406 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1407 1408 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1409 m = m_devget(cp, len, 0, ifp); 1410 1411 if (word[0] & CAS_RC0_RELEASE_HDR) 1412 cas_add_rxbuf(sc, idx); 1413 1414 if (m != NULL) { 1415 1416 /* 1417 * Pass this up to any BPF listeners, but only 1418 * pass it up the stack if its for us. 1419 */ 1420 m->m_pkthdr.csum_flags = 0; 1421 if_percpuq_enqueue(ifp->if_percpuq, m); 1422 } else 1423 if_statinc(ifp, if_ierrors); 1424 } 1425 1426 len = CAS_RC0_DATA_LEN(word[0]); 1427 if (len > 0) { 1428 off = CAS_RC0_DATA_OFF(word[0]); 1429 idx = CAS_RC0_DATA_IDX(word[0]); 1430 rxs = &sc->sc_rxsoft[idx]; 1431 1432 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1433 idx, off, len)); 1434 1435 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1436 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1437 1438 /* XXX We should not be copying the packet here. */ 1439 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1440 m = m_devget(cp, len, 0, ifp); 1441 1442 if (word[0] & CAS_RC0_RELEASE_DATA) 1443 cas_add_rxbuf(sc, idx); 1444 1445 if (m != NULL) { 1446 /* 1447 * Pass this up to any BPF listeners, but only 1448 * pass it up the stack if its for us. 1449 */ 1450 m->m_pkthdr.csum_flags = 0; 1451 if_percpuq_enqueue(ifp->if_percpuq, m); 1452 } else 1453 if_statinc(ifp, if_ierrors); 1454 } 1455 1456 if (word[0] & CAS_RC0_SPLIT) 1457 aprint_error_dev(sc->sc_dev, "split packet\n"); 1458 1459 skip = CAS_RC0_SKIP(word[0]); 1460 } 1461 1462 while (sc->sc_rxptr != i) { 1463 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1464 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1465 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1466 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1467 CAS_DMA_WRITE(CAS_RC3_OWN); 1468 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1470 1471 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1472 } 1473 1474 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1475 1476 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1477 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1478 1479 return (1); 1480} 1481 1482/* 1483 * cas_add_rxbuf: 1484 * 1485 * Add a receive buffer to the indicated descriptor. 1486 */ 1487int 1488cas_add_rxbuf(struct cas_softc *sc, int idx) 1489{ 1490 bus_space_tag_t t = sc->sc_memt; 1491 bus_space_handle_t h = sc->sc_memh; 1492 1493 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1494 1495 if ((sc->sc_rxdptr % 4) == 0) 1496 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1497 1498 if (++sc->sc_rxdptr == CAS_NRXDESC) 1499 sc->sc_rxdptr = 0; 1500 1501 return (0); 1502} 1503 1504int 1505cas_eint(struct cas_softc *sc, u_int status) 1506{ 1507 char bits[128]; 1508 if ((status & CAS_INTR_MIF) != 0) { 1509 DPRINTF(sc, ("%s: link status changed\n", 1510 device_xname(sc->sc_dev))); 1511 return (1); 1512 } 1513 1514 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1515 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1516 return (1); 1517} 1518 1519int 1520cas_pint(struct cas_softc *sc) 1521{ 1522 bus_space_tag_t t = sc->sc_memt; 1523 bus_space_handle_t seb = sc->sc_memh; 1524 uint32_t status; 1525 1526 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1527 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1528#ifdef CAS_DEBUG 1529 if (status) 1530 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1531#endif 1532 return (1); 1533} 1534 1535int 1536cas_intr(void *v) 1537{ 1538 struct cas_softc *sc = (struct cas_softc *)v; 1539 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1540 bus_space_tag_t t = sc->sc_memt; 1541 bus_space_handle_t seb = sc->sc_memh; 1542 uint32_t status; 1543 int r = 0; 1544#ifdef CAS_DEBUG 1545 char bits[128]; 1546#endif 1547 1548 sc->sc_ev_intr.ev_count++; 1549 1550 status = bus_space_read_4(t, seb, CAS_STATUS); 1551#ifdef CAS_DEBUG 1552 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1553#endif 1554 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1555 device_xname(sc->sc_dev), (status>>19), bits)); 1556 1557 if ((status & CAS_INTR_PCS) != 0) 1558 r |= cas_pint(sc); 1559 1560 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1561 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1562 r |= cas_eint(sc, status); 1563 1564 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1565 r |= cas_tint(sc, status); 1566 1567 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1568 r |= cas_rint(sc); 1569 1570 /* We should eventually do more than just print out error stats. */ 1571 if (status & CAS_INTR_TX_MAC) { 1572 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1573#ifdef CAS_DEBUG 1574 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1575 printf("%s: MAC tx fault, status %x\n", 1576 device_xname(sc->sc_dev), txstat); 1577#endif 1578 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1579 cas_init(ifp); 1580 } 1581 if (status & CAS_INTR_RX_MAC) { 1582 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1583#ifdef CAS_DEBUG 1584 if (rxstat & ~CAS_MAC_RX_DONE) 1585 printf("%s: MAC rx fault, status %x\n", 1586 device_xname(sc->sc_dev), rxstat); 1587#endif 1588 /* 1589 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1590 * due to a silicon bug so handle them silently. 1591 */ 1592 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1593 if_statinc(ifp, if_ierrors); 1594 cas_init(ifp); 1595 } 1596#ifdef CAS_DEBUG 1597 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1598 printf("%s: MAC rx fault, status %x\n", 1599 device_xname(sc->sc_dev), rxstat); 1600#endif 1601 } 1602 rnd_add_uint32(&sc->rnd_source, status); 1603 return (r); 1604} 1605 1606 1607void 1608cas_watchdog(struct ifnet *ifp) 1609{ 1610 struct cas_softc *sc = ifp->if_softc; 1611 1612 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1613 "CAS_MAC_RX_CONFIG %x\n", 1614 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1615 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1616 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1617 1618 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1619 if_statinc(ifp, if_oerrors); 1620 1621 /* Try to get more packets going. */ 1622 cas_init(ifp); 1623} 1624 1625/* 1626 * Initialize the MII Management Interface 1627 */ 1628void 1629cas_mifinit(struct cas_softc *sc) 1630{ 1631 bus_space_tag_t t = sc->sc_memt; 1632 bus_space_handle_t mif = sc->sc_memh; 1633 1634 /* Configure the MIF in frame mode */ 1635 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1636 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1637 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1638} 1639 1640/* 1641 * MII interface 1642 * 1643 * The Cassini MII interface supports at least three different operating modes: 1644 * 1645 * Bitbang mode is implemented using data, clock and output enable registers. 1646 * 1647 * Frame mode is implemented by loading a complete frame into the frame 1648 * register and polling the valid bit for completion. 1649 * 1650 * Polling mode uses the frame register but completion is indicated by 1651 * an interrupt. 1652 * 1653 */ 1654int 1655cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1656{ 1657 struct cas_softc *sc = device_private(self); 1658 bus_space_tag_t t = sc->sc_memt; 1659 bus_space_handle_t mif = sc->sc_memh; 1660 int n; 1661 uint32_t v; 1662 1663#ifdef CAS_DEBUG 1664 if (sc->sc_debug) 1665 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1666#endif 1667 1668 /* Construct the frame command */ 1669 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1670 CAS_MIF_FRAME_READ; 1671 1672 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1673 for (n = 0; n < 100; n++) { 1674 DELAY(1); 1675 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1676 if (v & CAS_MIF_FRAME_TA0) { 1677 *val = v & CAS_MIF_FRAME_DATA; 1678 return 0; 1679 } 1680 } 1681 1682 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1683 return ETIMEDOUT; 1684} 1685 1686int 1687cas_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1688{ 1689 struct cas_softc *sc = device_private(self); 1690 bus_space_tag_t t = sc->sc_memt; 1691 bus_space_handle_t mif = sc->sc_memh; 1692 int n; 1693 uint32_t v; 1694 1695#ifdef CAS_DEBUG 1696 if (sc->sc_debug) 1697 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1698 phy, reg, val); 1699#endif 1700 1701 /* Construct the frame command */ 1702 v = CAS_MIF_FRAME_WRITE | 1703 (phy << CAS_MIF_PHY_SHIFT) | 1704 (reg << CAS_MIF_REG_SHIFT) | 1705 (val & CAS_MIF_FRAME_DATA); 1706 1707 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1708 for (n = 0; n < 100; n++) { 1709 DELAY(1); 1710 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1711 if (v & CAS_MIF_FRAME_TA0) 1712 return 0; 1713 } 1714 1715 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1716 return ETIMEDOUT; 1717} 1718 1719void 1720cas_mii_statchg(struct ifnet *ifp) 1721{ 1722 struct cas_softc *sc = ifp->if_softc; 1723#ifdef CAS_DEBUG 1724 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1725#endif 1726 bus_space_tag_t t = sc->sc_memt; 1727 bus_space_handle_t mac = sc->sc_memh; 1728 uint32_t v; 1729 1730#ifdef CAS_DEBUG 1731 if (sc->sc_debug) 1732 printf("cas_mii_statchg: status change: phy = %d\n", 1733 sc->sc_phys[instance]); 1734#endif 1735 1736 /* Set tx full duplex options */ 1737 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1738 delay(10000); /* reg must be cleared and delay before changing. */ 1739 v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT | 1740 CAS_MAC_TX_ENABLE; 1741 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1742 v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS; 1743 } 1744 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1745 1746 /* XIF Configuration */ 1747 v = CAS_MAC_XIF_TX_MII_ENA; 1748 v |= CAS_MAC_XIF_LINK_LED; 1749 1750 /* MII needs echo disable if half duplex. */ 1751 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1752 /* turn on full duplex LED */ 1753 v |= CAS_MAC_XIF_FDPLX_LED; 1754 else 1755 /* half duplex -- disable echo */ 1756 v |= CAS_MAC_XIF_ECHO_DISABL; 1757 1758 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1759 case IFM_1000_T: /* Gigabit using GMII interface */ 1760 case IFM_1000_SX: 1761 v |= CAS_MAC_XIF_GMII_MODE; 1762 break; 1763 default: 1764 v &= ~CAS_MAC_XIF_GMII_MODE; 1765 } 1766 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1767} 1768 1769int 1770cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val) 1771{ 1772 struct cas_softc *sc = device_private(self); 1773 bus_space_tag_t t = sc->sc_memt; 1774 bus_space_handle_t pcs = sc->sc_memh; 1775 1776#ifdef CAS_DEBUG 1777 if (sc->sc_debug) 1778 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1779#endif 1780 1781 if (phy != CAS_PHYAD_EXTERNAL) 1782 return -1; 1783 1784 switch (reg) { 1785 case MII_BMCR: 1786 reg = CAS_MII_CONTROL; 1787 break; 1788 case MII_BMSR: 1789 reg = CAS_MII_STATUS; 1790 break; 1791 case MII_ANAR: 1792 reg = CAS_MII_ANAR; 1793 break; 1794 case MII_ANLPAR: 1795 reg = CAS_MII_ANLPAR; 1796 break; 1797 case MII_EXTSR: 1798 *val = EXTSR_1000XFDX | EXTSR_1000XHDX; 1799 return 0; 1800 default: 1801 return (0); 1802 } 1803 1804 *val = bus_space_read_4(t, pcs, reg) & 0xffff; 1805 return 0; 1806} 1807 1808int 1809cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val) 1810{ 1811 struct cas_softc *sc = device_private(self); 1812 bus_space_tag_t t = sc->sc_memt; 1813 bus_space_handle_t pcs = sc->sc_memh; 1814 int reset = 0; 1815 1816#ifdef CAS_DEBUG 1817 if (sc->sc_debug) 1818 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1819 phy, reg, val); 1820#endif 1821 1822 if (phy != CAS_PHYAD_EXTERNAL) 1823 return -1; 1824 1825 if (reg == MII_ANAR) 1826 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1827 1828 switch (reg) { 1829 case MII_BMCR: 1830 reset = (val & CAS_MII_CONTROL_RESET); 1831 reg = CAS_MII_CONTROL; 1832 break; 1833 case MII_BMSR: 1834 reg = CAS_MII_STATUS; 1835 break; 1836 case MII_ANAR: 1837 reg = CAS_MII_ANAR; 1838 break; 1839 case MII_ANLPAR: 1840 reg = CAS_MII_ANLPAR; 1841 break; 1842 default: 1843 return 0; 1844 } 1845 1846 bus_space_write_4(t, pcs, reg, val); 1847 1848 if (reset) 1849 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1850 1851 if (reg == CAS_MII_ANAR || reset) 1852 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1853 CAS_MII_CONFIG_ENABLE); 1854 1855 return 0; 1856} 1857 1858int 1859cas_mediachange(struct ifnet *ifp) 1860{ 1861 struct cas_softc *sc = ifp->if_softc; 1862 struct mii_data *mii = &sc->sc_mii; 1863 1864 if (mii->mii_instance) { 1865 struct mii_softc *miisc; 1866 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1867 mii_phy_reset(miisc); 1868 } 1869 1870 return (mii_mediachg(&sc->sc_mii)); 1871} 1872 1873void 1874cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1875{ 1876 struct cas_softc *sc = ifp->if_softc; 1877 1878 mii_pollstat(&sc->sc_mii); 1879 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1880 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1881} 1882 1883/* 1884 * Process an ioctl request. 1885 */ 1886int 1887cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1888{ 1889 struct cas_softc *sc = ifp->if_softc; 1890 int s, error = 0; 1891 1892 s = splnet(); 1893 1894 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1895 error = 0; 1896 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1897 ; 1898 else if (ifp->if_flags & IFF_RUNNING) { 1899 /* 1900 * Multicast list has changed; set the hardware filter 1901 * accordingly. 1902 */ 1903 cas_iff(sc); 1904 } 1905 } 1906 1907 splx(s); 1908 return (error); 1909} 1910 1911static bool 1912cas_suspend(device_t self, const pmf_qual_t *qual) 1913{ 1914 struct cas_softc *sc = device_private(self); 1915 bus_space_tag_t t = sc->sc_memt; 1916 bus_space_handle_t h = sc->sc_memh; 1917 1918 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1919 if (sc->sc_ih != NULL) { 1920 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1921 sc->sc_ih = NULL; 1922 } 1923 1924 return true; 1925} 1926 1927static bool 1928cas_resume(device_t self, const pmf_qual_t *qual) 1929{ 1930 struct cas_softc *sc = device_private(self); 1931 1932 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1933} 1934 1935static bool 1936cas_estintr(struct cas_softc *sc, int what) 1937{ 1938 bus_space_tag_t t = sc->sc_memt; 1939 bus_space_handle_t h = sc->sc_memh; 1940 const char *intrstr = NULL; 1941 char intrbuf[PCI_INTRSTR_LEN]; 1942 1943 /* PCI interrupts */ 1944 if (what & CAS_INTR_PCI) { 1945 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle, intrbuf, 1946 sizeof(intrbuf)); 1947 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_handle, 1948 IPL_NET, cas_intr, sc, device_xname(sc->sc_dev)); 1949 if (sc->sc_ih == NULL) { 1950 aprint_error_dev(sc->sc_dev, 1951 "unable to establish interrupt"); 1952 if (intrstr != NULL) 1953 aprint_error(" at %s", intrstr); 1954 aprint_error("\n"); 1955 return false; 1956 } 1957 1958 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1959 } 1960 1961 /* Interrupt register */ 1962 if (what & CAS_INTR_REG) { 1963 bus_space_write_4(t, h, CAS_INTMASK, 1964 ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY | 1965 CAS_INTR_TX_TAG_ERR | 1966 CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF | 1967 CAS_INTR_RX_TAG_ERR | 1968 CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS | 1969 CAS_INTR_MAC_CONTROL | CAS_INTR_MIF | 1970 CAS_INTR_BERR)); 1971 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1972 CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT); 1973 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1974 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1975 } 1976 return true; 1977} 1978 1979bool 1980cas_shutdown(device_t self, int howto) 1981{ 1982 struct cas_softc *sc = device_private(self); 1983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1984 1985 cas_stop(ifp, 1); 1986 1987 return true; 1988} 1989 1990void 1991cas_iff(struct cas_softc *sc) 1992{ 1993 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1994 struct ethercom *ec = &sc->sc_ethercom; 1995 struct ether_multi *enm; 1996 struct ether_multistep step; 1997 bus_space_tag_t t = sc->sc_memt; 1998 bus_space_handle_t h = sc->sc_memh; 1999 uint32_t crc, hash[16], rxcfg; 2000 int i; 2001 2002 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 2003 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 2004 CAS_MAC_RX_PROMISC_GRP); 2005 ifp->if_flags &= ~IFF_ALLMULTI; 2006 2007 if ((ifp->if_flags & IFF_PROMISC) != 0) 2008 goto update; 2009 2010 /* 2011 * Set up multicast address filter by passing all multicast 2012 * addresses through a crc generator, and then using the 2013 * high order 8 bits as an index into the 256 bit logical 2014 * address filter. The high order 4 bits selects the word, 2015 * while the other 4 bits select the bit within the word 2016 * (where bit 0 is the MSB). 2017 */ 2018 2019 /* Clear hash table */ 2020 for (i = 0; i < 16; i++) 2021 hash[i] = 0; 2022 2023 ETHER_LOCK(ec); 2024 ETHER_FIRST_MULTI(step, ec, enm); 2025 while (enm != NULL) { 2026 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2027 /* XXX Use ETHER_F_ALLMULTI in future. */ 2028 ifp->if_flags |= IFF_ALLMULTI; 2029 ETHER_UNLOCK(ec); 2030 goto update; 2031 } 2032 2033 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 2034 2035 /* Just want the 8 most significant bits. */ 2036 crc >>= 24; 2037 2038 /* Set the corresponding bit in the filter. */ 2039 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2040 2041 ETHER_NEXT_MULTI(step, enm); 2042 } 2043 ETHER_UNLOCK(ec); 2044 2045 rxcfg |= CAS_MAC_RX_HASH_FILTER; 2046 2047 /* Now load the hash table into the chip (if we are using it) */ 2048 for (i = 0; i < 16; i++) { 2049 bus_space_write_4(t, h, 2050 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2051 hash[i]); 2052 } 2053 2054update: 2055 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2056 if (ifp->if_flags & IFF_PROMISC) { 2057 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 2058 /* XXX Use ETHER_F_ALLMULTI in future. */ 2059 ifp->if_flags |= IFF_ALLMULTI; 2060 } else 2061 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 2062 } 2063 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 2064} 2065 2066int 2067cas_encap(struct cas_softc *sc, struct mbuf *mhead, uint32_t *bixp) 2068{ 2069 uint64_t flags; 2070 uint32_t cur, frag, i; 2071 bus_dmamap_t map; 2072 2073 cur = frag = *bixp; 2074 map = sc->sc_txd[cur].sd_map; 2075 2076 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 2077 BUS_DMA_NOWAIT) != 0) { 2078 return (ENOBUFS); 2079 } 2080 2081 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 2082 bus_dmamap_unload(sc->sc_dmatag, map); 2083 return (ENOBUFS); 2084 } 2085 2086 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 2087 BUS_DMASYNC_PREWRITE); 2088 2089 for (i = 0; i < map->dm_nsegs; i++) { 2090 sc->sc_txdescs[frag].cd_addr = 2091 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 2092 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 2093 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 2094 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 2095 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 2096 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 2097 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 2098 BUS_DMASYNC_PREWRITE); 2099 cur = frag; 2100 if (++frag == CAS_NTXDESC) 2101 frag = 0; 2102 } 2103 2104 sc->sc_tx_cnt += map->dm_nsegs; 2105 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 2106 sc->sc_txd[cur].sd_map = map; 2107 sc->sc_txd[cur].sd_mbuf = mhead; 2108 2109 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 2110 2111 *bixp = frag; 2112 2113 /* sync descriptors */ 2114 2115 return (0); 2116} 2117 2118/* 2119 * Transmit interrupt. 2120 */ 2121int 2122cas_tint(struct cas_softc *sc, uint32_t status) 2123{ 2124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2125 struct cas_sxd *sd; 2126 uint32_t cons, comp; 2127 2128 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 2129 cons = sc->sc_tx_cons; 2130 while (cons != comp) { 2131 sd = &sc->sc_txd[cons]; 2132 if (sd->sd_mbuf != NULL) { 2133 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2134 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2135 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2136 m_freem(sd->sd_mbuf); 2137 sd->sd_mbuf = NULL; 2138 if_statinc(ifp, if_opackets); 2139 } 2140 sc->sc_tx_cnt--; 2141 if (++cons == CAS_NTXDESC) 2142 cons = 0; 2143 } 2144 sc->sc_tx_cons = cons; 2145 2146 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2147 ifp->if_flags &= ~IFF_OACTIVE; 2148 if (sc->sc_tx_cnt == 0) 2149 ifp->if_timer = 0; 2150 2151 if_schedule_deferred_start(ifp); 2152 2153 return (1); 2154} 2155 2156void 2157cas_start(struct ifnet *ifp) 2158{ 2159 struct cas_softc *sc = ifp->if_softc; 2160 struct mbuf *m; 2161 uint32_t bix; 2162 2163 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2164 return; 2165 2166 bix = sc->sc_tx_prod; 2167 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2168 IFQ_POLL(&ifp->if_snd, m); 2169 if (m == NULL) 2170 break; 2171 2172 /* 2173 * If BPF is listening on this interface, let it see the 2174 * packet before we commit it to the wire. 2175 */ 2176 bpf_mtap(ifp, m, BPF_D_OUT); 2177 2178 /* 2179 * Encapsulate this packet and start it going... 2180 * or fail... 2181 */ 2182 if (cas_encap(sc, m, &bix)) { 2183 ifp->if_flags |= IFF_OACTIVE; 2184 break; 2185 } 2186 2187 IFQ_DEQUEUE(&ifp->if_snd, m); 2188 ifp->if_timer = 5; 2189 } 2190 2191 sc->sc_tx_prod = bix; 2192} 2193 2194MODULE(MODULE_CLASS_DRIVER, if_cas, "pci"); 2195 2196#ifdef _MODULE 2197#include "ioconf.c" 2198#endif 2199 2200static int 2201if_cas_modcmd(modcmd_t cmd, void *opaque) 2202{ 2203 int error = 0; 2204 2205 switch (cmd) { 2206 case MODULE_CMD_INIT: 2207#ifdef _MODULE 2208 error = config_init_component(cfdriver_ioconf_cas, 2209 cfattach_ioconf_cas, cfdata_ioconf_cas); 2210#endif 2211 return error; 2212 case MODULE_CMD_FINI: 2213#ifdef _MODULE 2214 error = config_fini_component(cfdriver_ioconf_cas, 2215 cfattach_ioconf_cas, cfdata_ioconf_cas); 2216#endif 2217 return error; 2218 default: 2219 return ENOTTY; 2220 } 2221} 2222