if_cas.c revision 1.10
1/* $NetBSD: if_cas.c,v 1.10 2010/07/14 04:50:28 jnemeth Exp $ */ 2/* $OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $ */ 3 4/* 5 * 6 * Copyright (C) 2007 Mark Kettenis. 7 * Copyright (C) 2001 Eduardo Horvath. 8 * All rights reserved. 9 * 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34/* 35 * Driver for Sun Cassini ethernet controllers. 36 * 37 * There are basically two variants of this chip: Cassini and 38 * Cassini+. We can distinguish between the two by revision: 0x10 and 39 * up are Cassini+. The most important difference is that Cassini+ 40 * has a second RX descriptor ring. Cassini+ will not work without 41 * configuring that second ring. However, since we don't use it we 42 * don't actually fill the descriptors, and only hand off the first 43 * four to the chip. 44 */ 45 46#include <sys/cdefs.h> 47__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.10 2010/07/14 04:50:28 jnemeth Exp $"); 48 49#include "opt_inet.h" 50 51#include <sys/param.h> 52#include <sys/systm.h> 53#include <sys/callout.h> 54#include <sys/mbuf.h> 55#include <sys/syslog.h> 56#include <sys/malloc.h> 57#include <sys/kernel.h> 58#include <sys/socket.h> 59#include <sys/ioctl.h> 60#include <sys/errno.h> 61#include <sys/device.h> 62 63#include <machine/endian.h> 64 65#include <uvm/uvm_extern.h> 66 67#include <net/if.h> 68#include <net/if_dl.h> 69#include <net/if_media.h> 70#include <net/if_ether.h> 71 72#ifdef INET 73#include <netinet/in.h> 74#include <netinet/in_systm.h> 75#include <netinet/in_var.h> 76#include <netinet/ip.h> 77#include <netinet/tcp.h> 78#include <netinet/udp.h> 79#endif 80 81#include <net/bpf.h> 82 83#include <sys/bus.h> 84#include <sys/intr.h> 85 86#include <dev/mii/mii.h> 87#include <dev/mii/miivar.h> 88#include <dev/mii/mii_bitbang.h> 89 90#include <dev/pci/pcivar.h> 91#include <dev/pci/pcireg.h> 92#include <dev/pci/pcidevs.h> 93#include <prop/proplib.h> 94 95#include <dev/pci/if_casreg.h> 96#include <dev/pci/if_casvar.h> 97 98#define TRIES 10000 99 100static bool cas_estintr(struct cas_softc *sc, int); 101bool cas_shutdown(device_t, int); 102static bool cas_suspend(device_t, const pmf_qual_t *); 103static bool cas_resume(device_t, const pmf_qual_t *); 104static int cas_detach(device_t, int); 105static void cas_partial_detach(struct cas_softc *, enum cas_attach_stage); 106 107int cas_match(device_t, cfdata_t, void *); 108void cas_attach(device_t, device_t, void *); 109 110 111CFATTACH_DECL3_NEW(cas, sizeof(struct cas_softc), 112 cas_match, cas_attach, cas_detach, NULL, NULL, NULL, 113 DVF_DETACH_SHUTDOWN); 114 115int cas_pci_enaddr(struct cas_softc *, struct pci_attach_args *, uint8_t *); 116 117void cas_config(struct cas_softc *, const uint8_t *); 118void cas_start(struct ifnet *); 119void cas_stop(struct ifnet *, int); 120int cas_ioctl(struct ifnet *, u_long, void *); 121void cas_tick(void *); 122void cas_watchdog(struct ifnet *); 123int cas_init(struct ifnet *); 124void cas_init_regs(struct cas_softc *); 125int cas_ringsize(int); 126int cas_cringsize(int); 127int cas_meminit(struct cas_softc *); 128void cas_mifinit(struct cas_softc *); 129int cas_bitwait(struct cas_softc *, bus_space_handle_t, int, 130 u_int32_t, u_int32_t); 131void cas_reset(struct cas_softc *); 132int cas_reset_rx(struct cas_softc *); 133int cas_reset_tx(struct cas_softc *); 134int cas_disable_rx(struct cas_softc *); 135int cas_disable_tx(struct cas_softc *); 136void cas_rxdrain(struct cas_softc *); 137int cas_add_rxbuf(struct cas_softc *, int idx); 138void cas_iff(struct cas_softc *); 139int cas_encap(struct cas_softc *, struct mbuf *, u_int32_t *); 140 141/* MII methods & callbacks */ 142int cas_mii_readreg(device_t, int, int); 143void cas_mii_writereg(device_t, int, int, int); 144void cas_mii_statchg(device_t); 145int cas_pcs_readreg(device_t, int, int); 146void cas_pcs_writereg(device_t, int, int, int); 147 148int cas_mediachange(struct ifnet *); 149void cas_mediastatus(struct ifnet *, struct ifmediareq *); 150 151int cas_eint(struct cas_softc *, u_int); 152int cas_rint(struct cas_softc *); 153int cas_tint(struct cas_softc *, u_int32_t); 154int cas_pint(struct cas_softc *); 155int cas_intr(void *); 156 157#ifdef CAS_DEBUG 158#define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 159 printf x 160#else 161#define DPRINTF(sc, x) /* nothing */ 162#endif 163 164int 165cas_match(device_t parent, cfdata_t cf, void *aux) 166{ 167 struct pci_attach_args *pa = aux; 168 169 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 170 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_CASSINI)) 171 return 1; 172 173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 174 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SATURN)) 175 return 1; 176 177 return 0; 178} 179 180#define PROMHDR_PTR_DATA 0x18 181#define PROMDATA_PTR_VPD 0x08 182#define PROMDATA_DATA2 0x0a 183 184static const u_int8_t cas_promhdr[] = { 0x55, 0xaa }; 185static const u_int8_t cas_promdat[] = { 186 'P', 'C', 'I', 'R', 187 PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8, 188 PCI_PRODUCT_SUN_CASSINI & 0xff, PCI_PRODUCT_SUN_CASSINI >> 8 189}; 190 191static const u_int8_t cas_promdat2[] = { 192 0x18, 0x00, /* structure length */ 193 0x00, /* structure revision */ 194 0x00, /* interface revision */ 195 PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */ 196 PCI_CLASS_NETWORK /* class code */ 197}; 198 199int 200cas_pci_enaddr(struct cas_softc *sc, struct pci_attach_args *pa, 201 uint8_t *enaddr) 202{ 203 struct pci_vpd_largeres *res; 204 struct pci_vpd *vpd; 205 bus_space_handle_t romh; 206 bus_space_tag_t romt; 207 bus_size_t romsize = 0; 208 u_int8_t buf[32], *desc; 209 pcireg_t address; 210 int dataoff, vpdoff, len; 211 int rv = -1; 212 213 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_MEM, 0, 214 &romt, &romh, NULL, &romsize)) 215 return (-1); 216 217 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 218 address |= PCI_MAPREG_ROM_ENABLE; 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START, address); 220 221 bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf)); 222 if (bcmp(buf, cas_promhdr, sizeof(cas_promhdr))) 223 goto fail; 224 225 dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8); 226 if (dataoff < 0x1c) 227 goto fail; 228 229 bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf)); 230 if (bcmp(buf, cas_promdat, sizeof(cas_promdat)) || 231 bcmp(buf + PROMDATA_DATA2, cas_promdat2, sizeof(cas_promdat2))) 232 goto fail; 233 234 vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8); 235 if (vpdoff < 0x1c) 236 goto fail; 237 238next: 239 bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf)); 240 if (!PCI_VPDRES_ISLARGE(buf[0])) 241 goto fail; 242 243 res = (struct pci_vpd_largeres *)buf; 244 vpdoff += sizeof(*res); 245 246 len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb); 247 switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) { 248 case PCI_VPDRES_TYPE_IDENTIFIER_STRING: 249 /* Skip identifier string. */ 250 vpdoff += len; 251 goto next; 252 253 case PCI_VPDRES_TYPE_VPD: 254 while (len > 0) { 255 bus_space_read_region_1(romt, romh, vpdoff, 256 buf, sizeof(buf)); 257 258 vpd = (struct pci_vpd *)buf; 259 vpdoff += sizeof(*vpd) + vpd->vpd_len; 260 len -= sizeof(*vpd) + vpd->vpd_len; 261 262 /* 263 * We're looking for an "Enhanced" VPD... 264 */ 265 if (vpd->vpd_key0 != 'Z') 266 continue; 267 268 desc = buf + sizeof(*vpd); 269 270 /* 271 * ...which is an instance property... 272 */ 273 if (desc[0] != 'I') 274 continue; 275 desc += 3; 276 277 /* 278 * ...that's a byte array with the proper 279 * length for a MAC address... 280 */ 281 if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN) 282 continue; 283 desc += 2; 284 285 /* 286 * ...named "local-mac-address". 287 */ 288 if (strcmp(desc, "local-mac-address") != 0) 289 continue; 290 desc += strlen("local-mac-address") + 1; 291 292 memcpy(enaddr, desc, ETHER_ADDR_LEN); 293 rv = 0; 294 } 295 break; 296 297 default: 298 goto fail; 299 } 300 301 fail: 302 if (romsize != 0) 303 bus_space_unmap(romt, romh, romsize); 304 305 address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM); 306 address &= ~PCI_MAPREG_ROM_ENABLE; 307 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address); 308 309 return (rv); 310} 311 312void 313cas_attach(device_t parent, device_t self, void *aux) 314{ 315 struct pci_attach_args *pa = aux; 316 struct cas_softc *sc = device_private(self); 317 char devinfo[256]; 318 prop_data_t data; 319 uint8_t enaddr[ETHER_ADDR_LEN]; 320 321 sc->sc_dev = self; 322 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 323 sc->sc_rev = PCI_REVISION(pa->pa_class); 324 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, sc->sc_rev); 325 sc->sc_dmatag = pa->pa_dmat; 326 327#define PCI_CAS_BASEADDR 0x10 328 if (pci_mapreg_map(pa, PCI_CAS_BASEADDR, PCI_MAPREG_TYPE_MEM, 0, 329 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_size) != 0) { 330 aprint_error_dev(sc->sc_dev, 331 "unable to map device registers\n"); 332 return; 333 } 334 335 if ((data = prop_dictionary_get(device_properties(sc->sc_dev), 336 "mac-address")) != NULL) 337 memcpy(enaddr, prop_data_data_nocopy(data), ETHER_ADDR_LEN); 338 else if (cas_pci_enaddr(sc, pa, enaddr) != 0) { 339 aprint_error_dev(sc->sc_dev, "no Ethernet address found\n"); 340 memset(enaddr, 0, sizeof(enaddr)); 341 } 342 343 sc->sc_burst = 16; /* XXX */ 344 345 sc->sc_att_stage = CAS_ATT_BACKEND_0; 346 347 if (pci_intr_map(pa, &sc->sc_handle) != 0) { 348 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 349 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 350 return; 351 } 352 sc->sc_pc = pa->pa_pc; 353 if (!cas_estintr(sc, CAS_INTR_PCI)) { 354 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 355 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 356 return; 357 } 358 359 sc->sc_att_stage = CAS_ATT_BACKEND_1; 360 361 /* 362 * call the main configure 363 */ 364 cas_config(sc, enaddr); 365 366 if (pmf_device_register1(sc->sc_dev, 367 cas_suspend, cas_resume, cas_shutdown)) 368 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 369 else 370 aprint_error_dev(sc->sc_dev, 371 "could not establish power handlers\n"); 372 373 sc->sc_att_stage = CAS_ATT_FINISHED; 374 /*FALLTHROUGH*/ 375} 376 377/* 378 * cas_config: 379 * 380 * Attach a Cassini interface to the system. 381 */ 382void 383cas_config(struct cas_softc *sc, const uint8_t *enaddr) 384{ 385 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 386 struct mii_data *mii = &sc->sc_mii; 387 struct mii_softc *child; 388 int i, error; 389 390 /* Make sure the chip is stopped. */ 391 ifp->if_softc = sc; 392 cas_reset(sc); 393 394 /* 395 * Allocate the control data structures, and create and load the 396 * DMA map for it. 397 */ 398 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 399 sizeof(struct cas_control_data), CAS_PAGE_SIZE, 0, &sc->sc_cdseg, 400 1, &sc->sc_cdnseg, 0)) != 0) { 401 aprint_error_dev(sc->sc_dev, 402 "unable to allocate control data, error = %d\n", 403 error); 404 cas_partial_detach(sc, CAS_ATT_0); 405 } 406 407 /* XXX should map this in with correct endianness */ 408 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 409 sizeof(struct cas_control_data), (void **)&sc->sc_control_data, 410 BUS_DMA_COHERENT)) != 0) { 411 aprint_error_dev(sc->sc_dev, 412 "unable to map control data, error = %d\n", error); 413 cas_partial_detach(sc, CAS_ATT_1); 414 } 415 416 if ((error = bus_dmamap_create(sc->sc_dmatag, 417 sizeof(struct cas_control_data), 1, 418 sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 419 aprint_error_dev(sc->sc_dev, 420 "unable to create control data DMA map, error = %d\n", error); 421 cas_partial_detach(sc, CAS_ATT_2); 422 } 423 424 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 425 sc->sc_control_data, sizeof(struct cas_control_data), NULL, 426 0)) != 0) { 427 aprint_error_dev(sc->sc_dev, 428 "unable to load control data DMA map, error = %d\n", 429 error); 430 cas_partial_detach(sc, CAS_ATT_3); 431 } 432 433 memset(sc->sc_control_data, 0, sizeof(struct cas_control_data)); 434 435 /* 436 * Create the receive buffer DMA maps. 437 */ 438 for (i = 0; i < CAS_NRXDESC; i++) { 439 bus_dma_segment_t seg; 440 char *kva; 441 int rseg; 442 443 if ((error = bus_dmamem_alloc(sc->sc_dmatag, CAS_PAGE_SIZE, 444 CAS_PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 445 aprint_error_dev(sc->sc_dev, 446 "unable to alloc rx DMA mem %d, error = %d\n", 447 i, error); 448 cas_partial_detach(sc, CAS_ATT_5); 449 } 450 sc->sc_rxsoft[i].rxs_dmaseg = seg; 451 452 if ((error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, 453 CAS_PAGE_SIZE, (void **)&kva, BUS_DMA_NOWAIT)) != 0) { 454 aprint_error_dev(sc->sc_dev, 455 "unable to alloc rx DMA mem %d, error = %d\n", 456 i, error); 457 cas_partial_detach(sc, CAS_ATT_5); 458 } 459 sc->sc_rxsoft[i].rxs_kva = kva; 460 461 if ((error = bus_dmamap_create(sc->sc_dmatag, CAS_PAGE_SIZE, 1, 462 CAS_PAGE_SIZE, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 463 aprint_error_dev(sc->sc_dev, 464 "unable to create rx DMA map %d, error = %d\n", 465 i, error); 466 cas_partial_detach(sc, CAS_ATT_5); 467 } 468 469 if ((error = bus_dmamap_load(sc->sc_dmatag, 470 sc->sc_rxsoft[i].rxs_dmamap, kva, CAS_PAGE_SIZE, NULL, 471 BUS_DMA_NOWAIT)) != 0) { 472 aprint_error_dev(sc->sc_dev, 473 "unable to load rx DMA map %d, error = %d\n", 474 i, error); 475 cas_partial_detach(sc, CAS_ATT_5); 476 } 477 } 478 479 /* 480 * Create the transmit buffer DMA maps. 481 */ 482 for (i = 0; i < CAS_NTXDESC; i++) { 483 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 484 CAS_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 485 &sc->sc_txd[i].sd_map)) != 0) { 486 aprint_error_dev(sc->sc_dev, 487 "unable to create tx DMA map %d, error = %d\n", 488 i, error); 489 cas_partial_detach(sc, CAS_ATT_6); 490 } 491 sc->sc_txd[i].sd_mbuf = NULL; 492 } 493 494 /* 495 * From this point forward, the attachment cannot fail. A failure 496 * before this point releases all resources that may have been 497 * allocated. 498 */ 499 500 /* Announce ourselves. */ 501 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 502 ether_sprintf(enaddr)); 503 aprint_naive(": Ethernet controller\n"); 504 505 /* Get RX FIFO size */ 506 sc->sc_rxfifosize = 16 * 1024; 507 508 /* Initialize ifnet structure. */ 509 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 510 ifp->if_softc = sc; 511 ifp->if_flags = 512 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 513 ifp->if_start = cas_start; 514 ifp->if_ioctl = cas_ioctl; 515 ifp->if_watchdog = cas_watchdog; 516 ifp->if_stop = cas_stop; 517 ifp->if_init = cas_init; 518 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_NTXDESC - 1); 519 IFQ_SET_READY(&ifp->if_snd); 520 521 /* Initialize ifmedia structures and MII info */ 522 mii->mii_ifp = ifp; 523 mii->mii_readreg = cas_mii_readreg; 524 mii->mii_writereg = cas_mii_writereg; 525 mii->mii_statchg = cas_mii_statchg; 526 527 ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus); 528 sc->sc_ethercom.ec_mii = mii; 529 530 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0); 531 532 cas_mifinit(sc); 533 534 if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) { 535 sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL; 536 bus_space_write_4(sc->sc_memt, sc->sc_memh, 537 CAS_MIF_CONFIG, sc->sc_mif_config); 538 } 539 540 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 541 MII_OFFSET_ANY, 0); 542 543 child = LIST_FIRST(&mii->mii_phys); 544 if (child == NULL && 545 sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { 546 /* 547 * Try the external PCS SERDES if we didn't find any 548 * MII devices. 549 */ 550 bus_space_write_4(sc->sc_memt, sc->sc_memh, 551 CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES); 552 553 bus_space_write_4(sc->sc_memt, sc->sc_memh, 554 CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE); 555 556 mii->mii_readreg = cas_pcs_readreg; 557 mii->mii_writereg = cas_pcs_writereg; 558 559 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 560 MII_OFFSET_ANY, MIIF_NOISOLATE); 561 } 562 563 child = LIST_FIRST(&mii->mii_phys); 564 if (child == NULL) { 565 /* No PHY attached */ 566 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 567 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 568 } else { 569 /* 570 * Walk along the list of attached MII devices and 571 * establish an `MII instance' to `phy number' 572 * mapping. We'll use this mapping in media change 573 * requests to determine which phy to use to program 574 * the MIF configuration register. 575 */ 576 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 577 /* 578 * Note: we support just two PHYs: the built-in 579 * internal device and an external on the MII 580 * connector. 581 */ 582 if (child->mii_phy > 1 || child->mii_inst > 1) { 583 aprint_error_dev(sc->sc_dev, 584 "cannot accommodate MII device %s" 585 " at phy %d, instance %d\n", 586 device_xname(child->mii_dev), 587 child->mii_phy, child->mii_inst); 588 continue; 589 } 590 591 sc->sc_phys[child->mii_inst] = child->mii_phy; 592 } 593 594 /* 595 * XXX - we can really do the following ONLY if the 596 * phy indeed has the auto negotiation capability!! 597 */ 598 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 599 } 600 601 /* claim 802.1q capability */ 602 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 603 604 /* Attach the interface. */ 605 if_attach(ifp); 606 ether_ifattach(ifp, enaddr); 607 608#if NRND > 0 609 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 610 RND_TYPE_NET, 0); 611#endif 612 613 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 614 NULL, device_xname(sc->sc_dev), "interrupts"); 615 616 callout_init(&sc->sc_tick_ch, 0); 617 618 return; 619} 620 621int 622cas_detach(device_t self, int flags) 623{ 624 int i; 625 struct cas_softc *sc = device_private(self); 626 bus_space_tag_t t = sc->sc_memt; 627 bus_space_handle_t h = sc->sc_memh; 628 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 629 630 /* 631 * Free any resources we've allocated during the failed attach 632 * attempt. Do this in reverse order and fall through. 633 */ 634 switch (sc->sc_att_stage) { 635 case CAS_ATT_FINISHED: 636 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 637 pmf_device_deregister(self); 638 cas_stop(&sc->sc_ethercom.ec_if, 1); 639 evcnt_detach(&sc->sc_ev_intr); 640 641#if NRND > 0 642 rnd_detach_source(&sc->rnd_source); 643#endif 644 645 ether_ifdetach(ifp); 646 if_detach(ifp); 647 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 648 649 callout_destroy(&sc->sc_tick_ch); 650 651 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 652 653 /*FALLTHROUGH*/ 654 case CAS_ATT_MII: 655 case CAS_ATT_7: 656 case CAS_ATT_6: 657 for (i = 0; i < CAS_NTXDESC; i++) { 658 if (sc->sc_txd[i].sd_map != NULL) 659 bus_dmamap_destroy(sc->sc_dmatag, 660 sc->sc_txd[i].sd_map); 661 } 662 /*FALLTHROUGH*/ 663 case CAS_ATT_5: 664 for (i = 0; i < CAS_NRXDESC; i++) { 665 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 666 bus_dmamap_unload(sc->sc_dmatag, 667 sc->sc_rxsoft[i].rxs_dmamap); 668 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 669 bus_dmamap_destroy(sc->sc_dmatag, 670 sc->sc_rxsoft[i].rxs_dmamap); 671 if (sc->sc_rxsoft[i].rxs_kva != NULL) 672 bus_dmamem_unmap(sc->sc_dmatag, 673 sc->sc_rxsoft[i].rxs_kva, CAS_PAGE_SIZE); 674 /* XXX need to check that bus_dmamem_alloc suceeded 675 if (sc->sc_rxsoft[i].rxs_dmaseg != NULL) 676 */ 677 bus_dmamem_free(sc->sc_dmatag, 678 &(sc->sc_rxsoft[i].rxs_dmaseg), 1); 679 } 680 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 681 /*FALLTHROUGH*/ 682 case CAS_ATT_4: 683 case CAS_ATT_3: 684 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 685 /*FALLTHROUGH*/ 686 case CAS_ATT_2: 687 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 688 sizeof(struct cas_control_data)); 689 /*FALLTHROUGH*/ 690 case CAS_ATT_1: 691 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 692 /*FALLTHROUGH*/ 693 case CAS_ATT_0: 694 sc->sc_att_stage = CAS_ATT_0; 695 /*FALLTHROUGH*/ 696 case CAS_ATT_BACKEND_2: 697 case CAS_ATT_BACKEND_1: 698 if (sc->sc_ih != NULL) { 699 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 700 sc->sc_ih = NULL; 701 } 702 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_size); 703 /*FALLTHROUGH*/ 704 case CAS_ATT_BACKEND_0: 705 break; 706 } 707 return 0; 708} 709 710static void 711cas_partial_detach(struct cas_softc *sc, enum cas_attach_stage stage) 712{ 713 cfattach_t ca = device_cfattach(sc->sc_dev); 714 715 sc->sc_att_stage = stage; 716 (*ca->ca_detach)(sc->sc_dev, 0); 717} 718 719void 720cas_tick(void *arg) 721{ 722 struct cas_softc *sc = arg; 723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 724 bus_space_tag_t t = sc->sc_memt; 725 bus_space_handle_t mac = sc->sc_memh; 726 int s; 727 u_int32_t v; 728 729 /* unload collisions counters */ 730 v = bus_space_read_4(t, mac, CAS_MAC_EXCESS_COLL_CNT) + 731 bus_space_read_4(t, mac, CAS_MAC_LATE_COLL_CNT); 732 ifp->if_collisions += v + 733 bus_space_read_4(t, mac, CAS_MAC_NORM_COLL_CNT) + 734 bus_space_read_4(t, mac, CAS_MAC_FIRST_COLL_CNT); 735 ifp->if_oerrors += v; 736 737 /* read error counters */ 738 ifp->if_ierrors += 739 bus_space_read_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT) + 740 bus_space_read_4(t, mac, CAS_MAC_RX_ALIGN_ERR) + 741 bus_space_read_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT) + 742 bus_space_read_4(t, mac, CAS_MAC_RX_CODE_VIOL); 743 744 /* clear the hardware counters */ 745 bus_space_write_4(t, mac, CAS_MAC_NORM_COLL_CNT, 0); 746 bus_space_write_4(t, mac, CAS_MAC_FIRST_COLL_CNT, 0); 747 bus_space_write_4(t, mac, CAS_MAC_EXCESS_COLL_CNT, 0); 748 bus_space_write_4(t, mac, CAS_MAC_LATE_COLL_CNT, 0); 749 bus_space_write_4(t, mac, CAS_MAC_RX_LEN_ERR_CNT, 0); 750 bus_space_write_4(t, mac, CAS_MAC_RX_ALIGN_ERR, 0); 751 bus_space_write_4(t, mac, CAS_MAC_RX_CRC_ERR_CNT, 0); 752 bus_space_write_4(t, mac, CAS_MAC_RX_CODE_VIOL, 0); 753 754 s = splnet(); 755 mii_tick(&sc->sc_mii); 756 splx(s); 757 758 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 759} 760 761int 762cas_bitwait(struct cas_softc *sc, bus_space_handle_t h, int r, 763 u_int32_t clr, u_int32_t set) 764{ 765 int i; 766 u_int32_t reg; 767 768 for (i = TRIES; i--; DELAY(100)) { 769 reg = bus_space_read_4(sc->sc_memt, h, r); 770 if ((reg & clr) == 0 && (reg & set) == set) 771 return (1); 772 } 773 774 return (0); 775} 776 777void 778cas_reset(struct cas_softc *sc) 779{ 780 bus_space_tag_t t = sc->sc_memt; 781 bus_space_handle_t h = sc->sc_memh; 782 int s; 783 784 s = splnet(); 785 DPRINTF(sc, ("%s: cas_reset\n", device_xname(sc->sc_dev))); 786 cas_reset_rx(sc); 787 cas_reset_tx(sc); 788 789 /* Disable interrupts */ 790 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_INTMASK, ~(uint32_t)0); 791 792 /* Do a full reset */ 793 bus_space_write_4(t, h, CAS_RESET, 794 CAS_RESET_RX | CAS_RESET_TX | CAS_RESET_BLOCK_PCS); 795 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 796 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 797 splx(s); 798} 799 800 801/* 802 * cas_rxdrain: 803 * 804 * Drain the receive queue. 805 */ 806void 807cas_rxdrain(struct cas_softc *sc) 808{ 809 /* Nothing to do yet. */ 810} 811 812/* 813 * Reset the whole thing. 814 */ 815void 816cas_stop(struct ifnet *ifp, int disable) 817{ 818 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 819 struct cas_sxd *sd; 820 u_int32_t i; 821 822 DPRINTF(sc, ("%s: cas_stop\n", device_xname(sc->sc_dev))); 823 824 callout_stop(&sc->sc_tick_ch); 825 826 /* 827 * Mark the interface down and cancel the watchdog timer. 828 */ 829 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 830 ifp->if_timer = 0; 831 832 mii_down(&sc->sc_mii); 833 834 cas_reset_rx(sc); 835 cas_reset_tx(sc); 836 837 /* 838 * Release any queued transmit buffers. 839 */ 840 for (i = 0; i < CAS_NTXDESC; i++) { 841 sd = &sc->sc_txd[i]; 842 if (sd->sd_mbuf != NULL) { 843 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 844 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 845 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 846 m_freem(sd->sd_mbuf); 847 sd->sd_mbuf = NULL; 848 } 849 } 850 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 851 852 if (disable) 853 cas_rxdrain(sc); 854} 855 856 857/* 858 * Reset the receiver 859 */ 860int 861cas_reset_rx(struct cas_softc *sc) 862{ 863 bus_space_tag_t t = sc->sc_memt; 864 bus_space_handle_t h = sc->sc_memh; 865 866 /* 867 * Resetting while DMA is in progress can cause a bus hang, so we 868 * disable DMA first. 869 */ 870 cas_disable_rx(sc); 871 bus_space_write_4(t, h, CAS_RX_CONFIG, 0); 872 /* Wait till it finishes */ 873 if (!cas_bitwait(sc, h, CAS_RX_CONFIG, 1, 0)) 874 aprint_error_dev(sc->sc_dev, "cannot disable rx dma\n"); 875 /* Wait 5ms extra. */ 876 delay(5000); 877 878 /* Finally, reset the ERX */ 879 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_RX); 880 /* Wait till it finishes */ 881 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_RX, 0)) { 882 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 883 return (1); 884 } 885 return (0); 886} 887 888 889/* 890 * Reset the transmitter 891 */ 892int 893cas_reset_tx(struct cas_softc *sc) 894{ 895 bus_space_tag_t t = sc->sc_memt; 896 bus_space_handle_t h = sc->sc_memh; 897 898 /* 899 * Resetting while DMA is in progress can cause a bus hang, so we 900 * disable DMA first. 901 */ 902 cas_disable_tx(sc); 903 bus_space_write_4(t, h, CAS_TX_CONFIG, 0); 904 /* Wait till it finishes */ 905 if (!cas_bitwait(sc, h, CAS_TX_CONFIG, 1, 0)) 906 aprint_error_dev(sc->sc_dev, "cannot disable tx dma\n"); 907 /* Wait 5ms extra. */ 908 delay(5000); 909 910 /* Finally, reset the ETX */ 911 bus_space_write_4(t, h, CAS_RESET, CAS_RESET_TX); 912 /* Wait till it finishes */ 913 if (!cas_bitwait(sc, h, CAS_RESET, CAS_RESET_TX, 0)) { 914 aprint_error_dev(sc->sc_dev, "cannot reset transmitter\n"); 915 return (1); 916 } 917 return (0); 918} 919 920/* 921 * Disable receiver. 922 */ 923int 924cas_disable_rx(struct cas_softc *sc) 925{ 926 bus_space_tag_t t = sc->sc_memt; 927 bus_space_handle_t h = sc->sc_memh; 928 u_int32_t cfg; 929 930 /* Flip the enable bit */ 931 cfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 932 cfg &= ~CAS_MAC_RX_ENABLE; 933 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, cfg); 934 935 /* Wait for it to finish */ 936 return (cas_bitwait(sc, h, CAS_MAC_RX_CONFIG, CAS_MAC_RX_ENABLE, 0)); 937} 938 939/* 940 * Disable transmitter. 941 */ 942int 943cas_disable_tx(struct cas_softc *sc) 944{ 945 bus_space_tag_t t = sc->sc_memt; 946 bus_space_handle_t h = sc->sc_memh; 947 u_int32_t cfg; 948 949 /* Flip the enable bit */ 950 cfg = bus_space_read_4(t, h, CAS_MAC_TX_CONFIG); 951 cfg &= ~CAS_MAC_TX_ENABLE; 952 bus_space_write_4(t, h, CAS_MAC_TX_CONFIG, cfg); 953 954 /* Wait for it to finish */ 955 return (cas_bitwait(sc, h, CAS_MAC_TX_CONFIG, CAS_MAC_TX_ENABLE, 0)); 956} 957 958/* 959 * Initialize interface. 960 */ 961int 962cas_meminit(struct cas_softc *sc) 963{ 964 struct cas_rxsoft *rxs; 965 int i, error; 966 967 rxs = (void *)&error; 968 969 /* 970 * Initialize the transmit descriptor ring. 971 */ 972 for (i = 0; i < CAS_NTXDESC; i++) { 973 sc->sc_txdescs[i].cd_flags = 0; 974 sc->sc_txdescs[i].cd_addr = 0; 975 } 976 CAS_CDTXSYNC(sc, 0, CAS_NTXDESC, 977 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 978 979 /* 980 * Initialize the receive descriptor and receive job 981 * descriptor rings. 982 */ 983 for (i = 0; i < CAS_NRXDESC; i++) 984 CAS_INIT_RXDESC(sc, i, i); 985 sc->sc_rxdptr = 0; 986 sc->sc_rxptr = 0; 987 988 /* 989 * Initialize the receive completion ring. 990 */ 991 for (i = 0; i < CAS_NRXCOMP; i++) { 992 sc->sc_rxcomps[i].cc_word[0] = 0; 993 sc->sc_rxcomps[i].cc_word[1] = 0; 994 sc->sc_rxcomps[i].cc_word[2] = 0; 995 sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN); 996 CAS_CDRXCSYNC(sc, i, 997 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 998 } 999 1000 return (0); 1001} 1002 1003int 1004cas_ringsize(int sz) 1005{ 1006 switch (sz) { 1007 case 32: 1008 return CAS_RING_SZ_32; 1009 case 64: 1010 return CAS_RING_SZ_64; 1011 case 128: 1012 return CAS_RING_SZ_128; 1013 case 256: 1014 return CAS_RING_SZ_256; 1015 case 512: 1016 return CAS_RING_SZ_512; 1017 case 1024: 1018 return CAS_RING_SZ_1024; 1019 case 2048: 1020 return CAS_RING_SZ_2048; 1021 case 4096: 1022 return CAS_RING_SZ_4096; 1023 case 8192: 1024 return CAS_RING_SZ_8192; 1025 default: 1026 aprint_error("cas: invalid Receive Descriptor ring size %d\n", 1027 sz); 1028 return CAS_RING_SZ_32; 1029 } 1030} 1031 1032int 1033cas_cringsize(int sz) 1034{ 1035 int i; 1036 1037 for (i = 0; i < 9; i++) 1038 if (sz == (128 << i)) 1039 return i; 1040 1041 aprint_error("cas: invalid completion ring size %d\n", sz); 1042 return 128; 1043} 1044 1045/* 1046 * Initialization of interface; set up initialization block 1047 * and transmit/receive descriptor rings. 1048 */ 1049int 1050cas_init(struct ifnet *ifp) 1051{ 1052 struct cas_softc *sc = (struct cas_softc *)ifp->if_softc; 1053 bus_space_tag_t t = sc->sc_memt; 1054 bus_space_handle_t h = sc->sc_memh; 1055 int s; 1056 u_int max_frame_size; 1057 u_int32_t v; 1058 1059 s = splnet(); 1060 1061 DPRINTF(sc, ("%s: cas_init: calling stop\n", device_xname(sc->sc_dev))); 1062 /* 1063 * Initialization sequence. The numbered steps below correspond 1064 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1065 * Channel Engine manual (part of the PCIO manual). 1066 * See also the STP2002-STQ document from Sun Microsystems. 1067 */ 1068 1069 /* step 1 & 2. Reset the Ethernet Channel */ 1070 cas_stop(ifp, 0); 1071 cas_reset(sc); 1072 DPRINTF(sc, ("%s: cas_init: restarting\n", device_xname(sc->sc_dev))); 1073 1074 /* Re-initialize the MIF */ 1075 cas_mifinit(sc); 1076 1077 /* step 3. Setup data structures in host memory */ 1078 cas_meminit(sc); 1079 1080 /* step 4. TX MAC registers & counters */ 1081 cas_init_regs(sc); 1082 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 1083 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 1084 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1085 1086 /* step 5. RX MAC registers & counters */ 1087 cas_iff(sc); 1088 1089 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1090 KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0); 1091 bus_space_write_4(t, h, CAS_TX_RING_PTR_HI, 1092 (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32)); 1093 bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0)); 1094 1095 KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0); 1096 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI, 1097 (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32)); 1098 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0)); 1099 1100 KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0); 1101 bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI, 1102 (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32)); 1103 bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0)); 1104 1105 if (CAS_PLUS(sc)) { 1106 KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0); 1107 bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2, 1108 (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32)); 1109 bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2, 1110 CAS_CDRXADDR2(sc, 0)); 1111 } 1112 1113 /* step 8. Global Configuration & Interrupt Mask */ 1114 cas_estintr(sc, CAS_INTR_REG); 1115 1116 /* step 9. ETX Configuration: use mostly default values */ 1117 1118 /* Enable DMA */ 1119 v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10; 1120 bus_space_write_4(t, h, CAS_TX_CONFIG, 1121 v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29)); 1122 bus_space_write_4(t, h, CAS_TX_KICK, 0); 1123 1124 /* step 10. ERX Configuration */ 1125 1126 /* Encode Receive Descriptor ring size */ 1127 v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT; 1128 if (CAS_PLUS(sc)) 1129 v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT; 1130 1131 /* Encode Receive Completion ring size */ 1132 v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT; 1133 1134 /* Enable DMA */ 1135 bus_space_write_4(t, h, CAS_RX_CONFIG, 1136 v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN); 1137 1138 /* 1139 * The following value is for an OFF Threshold of about 3/4 full 1140 * and an ON Threshold of 1/4 full. 1141 */ 1142 bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH, 1143 (3 * sc->sc_rxfifosize / 256) | 1144 ((sc->sc_rxfifosize / 256) << 12)); 1145 bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6); 1146 1147 /* step 11. Configure Media */ 1148 mii_ifmedia_change(&sc->sc_mii); 1149 1150 /* step 12. RX_MAC Configuration Register */ 1151 v = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1152 v |= CAS_MAC_RX_ENABLE | CAS_MAC_RX_STRIP_CRC; 1153 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, v); 1154 1155 /* step 14. Issue Transmit Pending command */ 1156 1157 /* step 15. Give the receiver a swift kick */ 1158 bus_space_write_4(t, h, CAS_RX_KICK, CAS_NRXDESC-4); 1159 if (CAS_PLUS(sc)) 1160 bus_space_write_4(t, h, CAS_RX_KICK2, 4); 1161 1162 /* Start the one second timer. */ 1163 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1164 1165 ifp->if_flags |= IFF_RUNNING; 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 ifp->if_timer = 0; 1168 splx(s); 1169 1170 return (0); 1171} 1172 1173void 1174cas_init_regs(struct cas_softc *sc) 1175{ 1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1177 bus_space_tag_t t = sc->sc_memt; 1178 bus_space_handle_t h = sc->sc_memh; 1179 const u_char *laddr = CLLADDR(ifp->if_sadl); 1180 u_int32_t v, r; 1181 1182 /* These regs are not cleared on reset */ 1183 sc->sc_inited = 0; 1184 if (!sc->sc_inited) { 1185 /* Load recommended values */ 1186 bus_space_write_4(t, h, CAS_MAC_IPG0, 0x00); 1187 bus_space_write_4(t, h, CAS_MAC_IPG1, 0x08); 1188 bus_space_write_4(t, h, CAS_MAC_IPG2, 0x04); 1189 1190 bus_space_write_4(t, h, CAS_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1191 /* Max frame and max burst size */ 1192 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 1193 bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v); 1194 1195 bus_space_write_4(t, h, CAS_MAC_PREAMBLE_LEN, 0x07); 1196 bus_space_write_4(t, h, CAS_MAC_JAM_SIZE, 0x04); 1197 bus_space_write_4(t, h, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1198 bus_space_write_4(t, h, CAS_MAC_CONTROL_TYPE, 0x8088); 1199 bus_space_write_4(t, h, CAS_MAC_RANDOM_SEED, 1200 ((laddr[5]<<8)|laddr[4])&0x3ff); 1201 1202 /* Secondary MAC addresses set to 0:0:0:0:0:0 */ 1203 for (r = CAS_MAC_ADDR3; r < CAS_MAC_ADDR42; r += 4) 1204 bus_space_write_4(t, h, r, 0); 1205 1206 /* MAC control addr set to 0:1:c2:0:1:80 */ 1207 bus_space_write_4(t, h, CAS_MAC_ADDR42, 0x0001); 1208 bus_space_write_4(t, h, CAS_MAC_ADDR43, 0xc200); 1209 bus_space_write_4(t, h, CAS_MAC_ADDR44, 0x0180); 1210 1211 /* MAC filter addr set to 0:0:0:0:0:0 */ 1212 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER0, 0); 1213 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER1, 0); 1214 bus_space_write_4(t, h, CAS_MAC_ADDR_FILTER2, 0); 1215 1216 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK1_2, 0); 1217 bus_space_write_4(t, h, CAS_MAC_ADR_FLT_MASK0, 0); 1218 1219 /* Hash table initialized to 0 */ 1220 for (r = CAS_MAC_HASH0; r <= CAS_MAC_HASH15; r += 4) 1221 bus_space_write_4(t, h, r, 0); 1222 1223 sc->sc_inited = 1; 1224 } 1225 1226 /* Counters need to be zeroed */ 1227 bus_space_write_4(t, h, CAS_MAC_NORM_COLL_CNT, 0); 1228 bus_space_write_4(t, h, CAS_MAC_FIRST_COLL_CNT, 0); 1229 bus_space_write_4(t, h, CAS_MAC_EXCESS_COLL_CNT, 0); 1230 bus_space_write_4(t, h, CAS_MAC_LATE_COLL_CNT, 0); 1231 bus_space_write_4(t, h, CAS_MAC_DEFER_TMR_CNT, 0); 1232 bus_space_write_4(t, h, CAS_MAC_PEAK_ATTEMPTS, 0); 1233 bus_space_write_4(t, h, CAS_MAC_RX_FRAME_COUNT, 0); 1234 bus_space_write_4(t, h, CAS_MAC_RX_LEN_ERR_CNT, 0); 1235 bus_space_write_4(t, h, CAS_MAC_RX_ALIGN_ERR, 0); 1236 bus_space_write_4(t, h, CAS_MAC_RX_CRC_ERR_CNT, 0); 1237 bus_space_write_4(t, h, CAS_MAC_RX_CODE_VIOL, 0); 1238 1239 /* Un-pause stuff */ 1240 bus_space_write_4(t, h, CAS_MAC_SEND_PAUSE_CMD, 0); 1241 1242 /* 1243 * Set the station address. 1244 */ 1245 bus_space_write_4(t, h, CAS_MAC_ADDR0, (laddr[4]<<8) | laddr[5]); 1246 bus_space_write_4(t, h, CAS_MAC_ADDR1, (laddr[2]<<8) | laddr[3]); 1247 bus_space_write_4(t, h, CAS_MAC_ADDR2, (laddr[0]<<8) | laddr[1]); 1248} 1249 1250/* 1251 * Receive interrupt. 1252 */ 1253int 1254cas_rint(struct cas_softc *sc) 1255{ 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 bus_space_tag_t t = sc->sc_memt; 1258 bus_space_handle_t h = sc->sc_memh; 1259 struct cas_rxsoft *rxs; 1260 struct mbuf *m; 1261 u_int64_t word[4]; 1262 int len, off, idx; 1263 int i, skip; 1264 void *cp; 1265 1266 for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) { 1267 CAS_CDRXCSYNC(sc, i, 1268 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1269 1270 word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]); 1271 word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]); 1272 word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]); 1273 word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]); 1274 1275 /* Stop if the hardware still owns the descriptor. */ 1276 if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN) 1277 break; 1278 1279 len = CAS_RC1_HDR_LEN(word[1]); 1280 if (len > 0) { 1281 off = CAS_RC1_HDR_OFF(word[1]); 1282 idx = CAS_RC1_HDR_IDX(word[1]); 1283 rxs = &sc->sc_rxsoft[idx]; 1284 1285 DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n", 1286 idx, off, len)); 1287 1288 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1289 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1290 1291 cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN; 1292 m = m_devget(cp, len, 0, ifp, NULL); 1293 1294 if (word[0] & CAS_RC0_RELEASE_HDR) 1295 cas_add_rxbuf(sc, idx); 1296 1297 if (m != NULL) { 1298 1299 /* 1300 * Pass this up to any BPF listeners, but only 1301 * pass it up the stack if its for us. 1302 */ 1303 bpf_mtap(ifp, m); 1304 1305 ifp->if_ipackets++; 1306 m->m_pkthdr.csum_flags = 0; 1307 (*ifp->if_input)(ifp, m); 1308 } else 1309 ifp->if_ierrors++; 1310 } 1311 1312 len = CAS_RC0_DATA_LEN(word[0]); 1313 if (len > 0) { 1314 off = CAS_RC0_DATA_OFF(word[0]); 1315 idx = CAS_RC0_DATA_IDX(word[0]); 1316 rxs = &sc->sc_rxsoft[idx]; 1317 1318 DPRINTF(sc, ("data at idx %d, off %d, len %d\n", 1319 idx, off, len)); 1320 1321 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1322 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1323 1324 /* XXX We should not be copying the packet here. */ 1325 cp = rxs->rxs_kva + off + ETHER_ALIGN; 1326 m = m_devget(cp, len, 0, ifp, NULL); 1327 1328 if (word[0] & CAS_RC0_RELEASE_DATA) 1329 cas_add_rxbuf(sc, idx); 1330 1331 if (m != NULL) { 1332 /* 1333 * Pass this up to any BPF listeners, but only 1334 * pass it up the stack if its for us. 1335 */ 1336 bpf_mtap(ifp, m); 1337 1338 ifp->if_ipackets++; 1339 m->m_pkthdr.csum_flags = 0; 1340 (*ifp->if_input)(ifp, m); 1341 } else 1342 ifp->if_ierrors++; 1343 } 1344 1345 if (word[0] & CAS_RC0_SPLIT) 1346 aprint_error_dev(sc->sc_dev, "split packet\n"); 1347 1348 skip = CAS_RC0_SKIP(word[0]); 1349 } 1350 1351 while (sc->sc_rxptr != i) { 1352 sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0; 1353 sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0; 1354 sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0; 1355 sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] = 1356 CAS_DMA_WRITE(CAS_RC3_OWN); 1357 CAS_CDRXCSYNC(sc, sc->sc_rxptr, 1358 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1359 1360 sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr); 1361 } 1362 1363 bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr); 1364 1365 DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n", 1366 sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION))); 1367 1368 return (1); 1369} 1370 1371/* 1372 * cas_add_rxbuf: 1373 * 1374 * Add a receive buffer to the indicated descriptor. 1375 */ 1376int 1377cas_add_rxbuf(struct cas_softc *sc, int idx) 1378{ 1379 bus_space_tag_t t = sc->sc_memt; 1380 bus_space_handle_t h = sc->sc_memh; 1381 1382 CAS_INIT_RXDESC(sc, sc->sc_rxdptr, idx); 1383 1384 if ((sc->sc_rxdptr % 4) == 0) 1385 bus_space_write_4(t, h, CAS_RX_KICK, sc->sc_rxdptr); 1386 1387 if (++sc->sc_rxdptr == CAS_NRXDESC) 1388 sc->sc_rxdptr = 0; 1389 1390 return (0); 1391} 1392 1393int 1394cas_eint(struct cas_softc *sc, u_int status) 1395{ 1396 char bits[128]; 1397 if ((status & CAS_INTR_MIF) != 0) { 1398 DPRINTF(sc, ("%s: link status changed\n", 1399 device_xname(sc->sc_dev))); 1400 return (1); 1401 } 1402 1403 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1404 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1405 return (1); 1406} 1407 1408int 1409cas_pint(struct cas_softc *sc) 1410{ 1411 bus_space_tag_t t = sc->sc_memt; 1412 bus_space_handle_t seb = sc->sc_memh; 1413 u_int32_t status; 1414 1415 status = bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1416 status |= bus_space_read_4(t, seb, CAS_MII_INTERRUP_STATUS); 1417#ifdef CAS_DEBUG 1418 if (status) 1419 printf("%s: link status changed\n", device_xname(sc->sc_dev)); 1420#endif 1421 return (1); 1422} 1423 1424int 1425cas_intr(void *v) 1426{ 1427 struct cas_softc *sc = (struct cas_softc *)v; 1428 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1429 bus_space_tag_t t = sc->sc_memt; 1430 bus_space_handle_t seb = sc->sc_memh; 1431 u_int32_t status; 1432 int r = 0; 1433#ifdef CAS_DEBUG 1434 char bits[128]; 1435#endif 1436 1437 sc->sc_ev_intr.ev_count++; 1438 1439 status = bus_space_read_4(t, seb, CAS_STATUS); 1440#ifdef CAS_DEBUG 1441 snprintb(bits, sizeof(bits), CAS_INTR_BITS, status); 1442#endif 1443 DPRINTF(sc, ("%s: cas_intr: cplt %x status %s\n", 1444 device_xname(sc->sc_dev), (status>>19), bits)); 1445 1446 if ((status & CAS_INTR_PCS) != 0) 1447 r |= cas_pint(sc); 1448 1449 if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 1450 CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0) 1451 r |= cas_eint(sc, status); 1452 1453 if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0) 1454 r |= cas_tint(sc, status); 1455 1456 if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0) 1457 r |= cas_rint(sc); 1458 1459 /* We should eventually do more than just print out error stats. */ 1460 if (status & CAS_INTR_TX_MAC) { 1461 int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS); 1462#ifdef CAS_DEBUG 1463 if (txstat & ~CAS_MAC_TX_XMIT_DONE) 1464 printf("%s: MAC tx fault, status %x\n", 1465 device_xname(sc->sc_dev), txstat); 1466#endif 1467 if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG)) 1468 cas_init(ifp); 1469 } 1470 if (status & CAS_INTR_RX_MAC) { 1471 int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS); 1472#ifdef CAS_DEBUG 1473 if (rxstat & ~CAS_MAC_RX_DONE) 1474 printf("%s: MAC rx fault, status %x\n", 1475 device_xname(sc->sc_dev), rxstat); 1476#endif 1477 /* 1478 * On some chip revisions CAS_MAC_RX_OVERFLOW happen often 1479 * due to a silicon bug so handle them silently. 1480 */ 1481 if (rxstat & CAS_MAC_RX_OVERFLOW) { 1482 ifp->if_ierrors++; 1483 cas_init(ifp); 1484 } 1485#ifdef CAS_DEBUG 1486 else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT)) 1487 printf("%s: MAC rx fault, status %x\n", 1488 device_xname(sc->sc_dev), rxstat); 1489#endif 1490 } 1491#if NRND > 0 1492 rnd_add_uint32(&sc->rnd_source, status); 1493#endif 1494 return (r); 1495} 1496 1497 1498void 1499cas_watchdog(struct ifnet *ifp) 1500{ 1501 struct cas_softc *sc = ifp->if_softc; 1502 1503 DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x " 1504 "CAS_MAC_RX_CONFIG %x\n", 1505 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG), 1506 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS), 1507 bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG))); 1508 1509 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1510 ++ifp->if_oerrors; 1511 1512 /* Try to get more packets going. */ 1513 cas_init(ifp); 1514} 1515 1516/* 1517 * Initialize the MII Management Interface 1518 */ 1519void 1520cas_mifinit(struct cas_softc *sc) 1521{ 1522 bus_space_tag_t t = sc->sc_memt; 1523 bus_space_handle_t mif = sc->sc_memh; 1524 1525 /* Configure the MIF in frame mode */ 1526 sc->sc_mif_config = bus_space_read_4(t, mif, CAS_MIF_CONFIG); 1527 sc->sc_mif_config &= ~CAS_MIF_CONFIG_BB_ENA; 1528 bus_space_write_4(t, mif, CAS_MIF_CONFIG, sc->sc_mif_config); 1529} 1530 1531/* 1532 * MII interface 1533 * 1534 * The Cassini MII interface supports at least three different operating modes: 1535 * 1536 * Bitbang mode is implemented using data, clock and output enable registers. 1537 * 1538 * Frame mode is implemented by loading a complete frame into the frame 1539 * register and polling the valid bit for completion. 1540 * 1541 * Polling mode uses the frame register but completion is indicated by 1542 * an interrupt. 1543 * 1544 */ 1545int 1546cas_mii_readreg(device_t self, int phy, int reg) 1547{ 1548 struct cas_softc *sc = device_private(self); 1549 bus_space_tag_t t = sc->sc_memt; 1550 bus_space_handle_t mif = sc->sc_memh; 1551 int n; 1552 u_int32_t v; 1553 1554#ifdef CAS_DEBUG 1555 if (sc->sc_debug) 1556 printf("cas_mii_readreg: phy %d reg %d\n", phy, reg); 1557#endif 1558 1559 /* Construct the frame command */ 1560 v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) | 1561 CAS_MIF_FRAME_READ; 1562 1563 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1564 for (n = 0; n < 100; n++) { 1565 DELAY(1); 1566 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1567 if (v & CAS_MIF_FRAME_TA0) 1568 return (v & CAS_MIF_FRAME_DATA); 1569 } 1570 1571 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1572 return (0); 1573} 1574 1575void 1576cas_mii_writereg(device_t self, int phy, int reg, int val) 1577{ 1578 struct cas_softc *sc = device_private(self); 1579 bus_space_tag_t t = sc->sc_memt; 1580 bus_space_handle_t mif = sc->sc_memh; 1581 int n; 1582 u_int32_t v; 1583 1584#ifdef CAS_DEBUG 1585 if (sc->sc_debug) 1586 printf("cas_mii_writereg: phy %d reg %d val %x\n", 1587 phy, reg, val); 1588#endif 1589 1590 /* Construct the frame command */ 1591 v = CAS_MIF_FRAME_WRITE | 1592 (phy << CAS_MIF_PHY_SHIFT) | 1593 (reg << CAS_MIF_REG_SHIFT) | 1594 (val & CAS_MIF_FRAME_DATA); 1595 1596 bus_space_write_4(t, mif, CAS_MIF_FRAME, v); 1597 for (n = 0; n < 100; n++) { 1598 DELAY(1); 1599 v = bus_space_read_4(t, mif, CAS_MIF_FRAME); 1600 if (v & CAS_MIF_FRAME_TA0) 1601 return; 1602 } 1603 1604 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1605} 1606 1607void 1608cas_mii_statchg(device_t self) 1609{ 1610 struct cas_softc *sc = device_private(self); 1611#ifdef CAS_DEBUG 1612 int instance = IFM_INST(sc->sc_media.ifm_cur->ifm_media); 1613#endif 1614 bus_space_tag_t t = sc->sc_memt; 1615 bus_space_handle_t mac = sc->sc_memh; 1616 u_int32_t v; 1617 1618#ifdef CAS_DEBUG 1619 if (sc->sc_debug) 1620 printf("cas_mii_statchg: status change: phy = %d\n", 1621 sc->sc_phys[instance]); 1622#endif 1623 1624 /* Set tx full duplex options */ 1625 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0); 1626 delay(10000); /* reg must be cleared and delay before changing. */ 1627 v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT| 1628 CAS_MAC_TX_ENABLE; 1629 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1630 v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS; 1631 } 1632 bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v); 1633 1634 /* XIF Configuration */ 1635 v = CAS_MAC_XIF_TX_MII_ENA; 1636 v |= CAS_MAC_XIF_LINK_LED; 1637 1638 /* MII needs echo disable if half duplex. */ 1639 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1640 /* turn on full duplex LED */ 1641 v |= CAS_MAC_XIF_FDPLX_LED; 1642 else 1643 /* half duplex -- disable echo */ 1644 v |= CAS_MAC_XIF_ECHO_DISABL; 1645 1646 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1647 case IFM_1000_T: /* Gigabit using GMII interface */ 1648 case IFM_1000_SX: 1649 v |= CAS_MAC_XIF_GMII_MODE; 1650 break; 1651 default: 1652 v &= ~CAS_MAC_XIF_GMII_MODE; 1653 } 1654 bus_space_write_4(t, mac, CAS_MAC_XIF_CONFIG, v); 1655} 1656 1657int 1658cas_pcs_readreg(device_t self, int phy, int reg) 1659{ 1660 struct cas_softc *sc = device_private(self); 1661 bus_space_tag_t t = sc->sc_memt; 1662 bus_space_handle_t pcs = sc->sc_memh; 1663 1664#ifdef CAS_DEBUG 1665 if (sc->sc_debug) 1666 printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg); 1667#endif 1668 1669 if (phy != CAS_PHYAD_EXTERNAL) 1670 return (0); 1671 1672 switch (reg) { 1673 case MII_BMCR: 1674 reg = CAS_MII_CONTROL; 1675 break; 1676 case MII_BMSR: 1677 reg = CAS_MII_STATUS; 1678 break; 1679 case MII_ANAR: 1680 reg = CAS_MII_ANAR; 1681 break; 1682 case MII_ANLPAR: 1683 reg = CAS_MII_ANLPAR; 1684 break; 1685 case MII_EXTSR: 1686 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 1687 default: 1688 return (0); 1689 } 1690 1691 return bus_space_read_4(t, pcs, reg); 1692} 1693 1694void 1695cas_pcs_writereg(device_t self, int phy, int reg, int val) 1696{ 1697 struct cas_softc *sc = device_private(self); 1698 bus_space_tag_t t = sc->sc_memt; 1699 bus_space_handle_t pcs = sc->sc_memh; 1700 int reset = 0; 1701 1702#ifdef CAS_DEBUG 1703 if (sc->sc_debug) 1704 printf("cas_pcs_writereg: phy %d reg %d val %x\n", 1705 phy, reg, val); 1706#endif 1707 1708 if (phy != CAS_PHYAD_EXTERNAL) 1709 return; 1710 1711 if (reg == MII_ANAR) 1712 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 0); 1713 1714 switch (reg) { 1715 case MII_BMCR: 1716 reset = (val & CAS_MII_CONTROL_RESET); 1717 reg = CAS_MII_CONTROL; 1718 break; 1719 case MII_BMSR: 1720 reg = CAS_MII_STATUS; 1721 break; 1722 case MII_ANAR: 1723 reg = CAS_MII_ANAR; 1724 break; 1725 case MII_ANLPAR: 1726 reg = CAS_MII_ANLPAR; 1727 break; 1728 default: 1729 return; 1730 } 1731 1732 bus_space_write_4(t, pcs, reg, val); 1733 1734 if (reset) 1735 cas_bitwait(sc, pcs, CAS_MII_CONTROL, CAS_MII_CONTROL_RESET, 0); 1736 1737 if (reg == CAS_MII_ANAR || reset) 1738 bus_space_write_4(t, pcs, CAS_MII_CONFIG, 1739 CAS_MII_CONFIG_ENABLE); 1740} 1741 1742int 1743cas_mediachange(struct ifnet *ifp) 1744{ 1745 struct cas_softc *sc = ifp->if_softc; 1746 struct mii_data *mii = &sc->sc_mii; 1747 1748 if (mii->mii_instance) { 1749 struct mii_softc *miisc; 1750 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1751 mii_phy_reset(miisc); 1752 } 1753 1754 return (mii_mediachg(&sc->sc_mii)); 1755} 1756 1757void 1758cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1759{ 1760 struct cas_softc *sc = ifp->if_softc; 1761 1762 mii_pollstat(&sc->sc_mii); 1763 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1764 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1765} 1766 1767/* 1768 * Process an ioctl request. 1769 */ 1770int 1771cas_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1772{ 1773 struct cas_softc *sc = ifp->if_softc; 1774 int s, error = 0; 1775 1776 s = splnet(); 1777 1778 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1779 error = 0; 1780 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1781 ; 1782 else if (ifp->if_flags & IFF_RUNNING) { 1783 /* 1784 * Multicast list has changed; set the hardware filter 1785 * accordingly. 1786 */ 1787 cas_iff(sc); 1788 } 1789 } 1790 1791 splx(s); 1792 return (error); 1793} 1794 1795static bool 1796cas_suspend(device_t self, const pmf_qual_t *qual) 1797{ 1798 struct cas_softc *sc = device_private(self); 1799 bus_space_tag_t t = sc->sc_memt; 1800 bus_space_handle_t h = sc->sc_memh; 1801 1802 bus_space_write_4(t, h, CAS_INTMASK, ~(uint32_t)0); 1803 if (sc->sc_ih != NULL) { 1804 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1805 sc->sc_ih = NULL; 1806 } 1807 1808 return true; 1809} 1810 1811static bool 1812cas_resume(device_t self, const pmf_qual_t *qual) 1813{ 1814 struct cas_softc *sc = device_private(self); 1815 1816 return cas_estintr(sc, CAS_INTR_PCI | CAS_INTR_REG); 1817} 1818 1819static bool 1820cas_estintr(struct cas_softc *sc, int what) 1821{ 1822 bus_space_tag_t t = sc->sc_memt; 1823 bus_space_handle_t h = sc->sc_memh; 1824 const char *intrstr = NULL; 1825 1826 /* PCI interrupts */ 1827 if (what & CAS_INTR_PCI) { 1828 intrstr = pci_intr_string(sc->sc_pc, sc->sc_handle); 1829 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_handle, 1830 IPL_NET, cas_intr, sc); 1831 if (sc->sc_ih == NULL) { 1832 aprint_error_dev(sc->sc_dev, 1833 "unable to establish interrupt"); 1834 if (intrstr != NULL) 1835 aprint_error(" at %s", intrstr); 1836 aprint_error("\n"); 1837 return false; 1838 } 1839 1840 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1841 } 1842 1843 /* Interrupt register */ 1844 if (what & CAS_INTR_REG) { 1845 bus_space_write_4(t, h, CAS_INTMASK, 1846 ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY| 1847 CAS_INTR_TX_TAG_ERR| 1848 CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF| 1849 CAS_INTR_RX_TAG_ERR| 1850 CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS| 1851 CAS_INTR_MAC_CONTROL|CAS_INTR_MIF| 1852 CAS_INTR_BERR)); 1853 bus_space_write_4(t, h, CAS_MAC_RX_MASK, 1854 CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT); 1855 bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE); 1856 bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */ 1857 } 1858 return true; 1859} 1860 1861bool 1862cas_shutdown(device_t self, int howto) 1863{ 1864 struct cas_softc *sc = device_private(self); 1865 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1866 1867 cas_stop(ifp, 1); 1868 1869 return true; 1870} 1871 1872void 1873cas_iff(struct cas_softc *sc) 1874{ 1875 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1876 struct ethercom *ec = &sc->sc_ethercom; 1877 struct ether_multi *enm; 1878 struct ether_multistep step; 1879 bus_space_tag_t t = sc->sc_memt; 1880 bus_space_handle_t h = sc->sc_memh; 1881 u_int32_t crc, hash[16], rxcfg; 1882 int i; 1883 1884 rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG); 1885 rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS | 1886 CAS_MAC_RX_PROMISC_GRP); 1887 ifp->if_flags &= ~IFF_ALLMULTI; 1888 1889 if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) { 1890 ifp->if_flags |= IFF_ALLMULTI; 1891 if (ifp->if_flags & IFF_PROMISC) 1892 rxcfg |= CAS_MAC_RX_PROMISCUOUS; 1893 else 1894 rxcfg |= CAS_MAC_RX_PROMISC_GRP; 1895 } else { 1896 /* 1897 * Set up multicast address filter by passing all multicast 1898 * addresses through a crc generator, and then using the 1899 * high order 8 bits as an index into the 256 bit logical 1900 * address filter. The high order 4 bits selects the word, 1901 * while the other 4 bits select the bit within the word 1902 * (where bit 0 is the MSB). 1903 */ 1904 1905 rxcfg |= CAS_MAC_RX_HASH_FILTER; 1906 1907 /* Clear hash table */ 1908 for (i = 0; i < 16; i++) 1909 hash[i] = 0; 1910 1911 ETHER_FIRST_MULTI(step, ec, enm); 1912 while (enm != NULL) { 1913 crc = ether_crc32_le(enm->enm_addrlo, 1914 ETHER_ADDR_LEN); 1915 1916 /* Just want the 8 most significant bits. */ 1917 crc >>= 24; 1918 1919 /* Set the corresponding bit in the filter. */ 1920 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1921 1922 ETHER_NEXT_MULTI(step, enm); 1923 } 1924 1925 /* Now load the hash table into the chip (if we are using it) */ 1926 for (i = 0; i < 16; i++) { 1927 bus_space_write_4(t, h, 1928 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 1929 hash[i]); 1930 } 1931 } 1932 1933 bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg); 1934} 1935 1936int 1937cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp) 1938{ 1939 u_int64_t flags; 1940 u_int32_t cur, frag, i; 1941 bus_dmamap_t map; 1942 1943 cur = frag = *bixp; 1944 map = sc->sc_txd[cur].sd_map; 1945 1946 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1947 BUS_DMA_NOWAIT) != 0) { 1948 return (ENOBUFS); 1949 } 1950 1951 if ((sc->sc_tx_cnt + map->dm_nsegs) > (CAS_NTXDESC - 2)) { 1952 bus_dmamap_unload(sc->sc_dmatag, map); 1953 return (ENOBUFS); 1954 } 1955 1956 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1957 BUS_DMASYNC_PREWRITE); 1958 1959 for (i = 0; i < map->dm_nsegs; i++) { 1960 sc->sc_txdescs[frag].cd_addr = 1961 CAS_DMA_WRITE(map->dm_segs[i].ds_addr); 1962 flags = (map->dm_segs[i].ds_len & CAS_TD_BUFSIZE) | 1963 (i == 0 ? CAS_TD_START_OF_PACKET : 0) | 1964 ((i == (map->dm_nsegs - 1)) ? CAS_TD_END_OF_PACKET : 0); 1965 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); 1966 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1967 CAS_CDTXOFF(frag), sizeof(struct cas_desc), 1968 BUS_DMASYNC_PREWRITE); 1969 cur = frag; 1970 if (++frag == CAS_NTXDESC) 1971 frag = 0; 1972 } 1973 1974 sc->sc_tx_cnt += map->dm_nsegs; 1975 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1976 sc->sc_txd[cur].sd_map = map; 1977 sc->sc_txd[cur].sd_mbuf = mhead; 1978 1979 bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_TX_KICK, frag); 1980 1981 *bixp = frag; 1982 1983 /* sync descriptors */ 1984 1985 return (0); 1986} 1987 1988/* 1989 * Transmit interrupt. 1990 */ 1991int 1992cas_tint(struct cas_softc *sc, u_int32_t status) 1993{ 1994 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1995 struct cas_sxd *sd; 1996 u_int32_t cons, comp; 1997 1998 comp = bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_TX_COMPLETION); 1999 cons = sc->sc_tx_cons; 2000 while (cons != comp) { 2001 sd = &sc->sc_txd[cons]; 2002 if (sd->sd_mbuf != NULL) { 2003 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 2004 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2005 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 2006 m_freem(sd->sd_mbuf); 2007 sd->sd_mbuf = NULL; 2008 ifp->if_opackets++; 2009 } 2010 sc->sc_tx_cnt--; 2011 if (++cons == CAS_NTXDESC) 2012 cons = 0; 2013 } 2014 sc->sc_tx_cons = cons; 2015 2016 if (sc->sc_tx_cnt < CAS_NTXDESC - 2) 2017 ifp->if_flags &= ~IFF_OACTIVE; 2018 if (sc->sc_tx_cnt == 0) 2019 ifp->if_timer = 0; 2020 2021 cas_start(ifp); 2022 2023 return (1); 2024} 2025 2026void 2027cas_start(struct ifnet *ifp) 2028{ 2029 struct cas_softc *sc = ifp->if_softc; 2030 struct mbuf *m; 2031 u_int32_t bix; 2032 2033 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2034 return; 2035 2036 bix = sc->sc_tx_prod; 2037 while (sc->sc_txd[bix].sd_mbuf == NULL) { 2038 IFQ_POLL(&ifp->if_snd, m); 2039 if (m == NULL) 2040 break; 2041 2042 /* 2043 * If BPF is listening on this interface, let it see the 2044 * packet before we commit it to the wire. 2045 */ 2046 bpf_mtap(ifp, m); 2047 2048 /* 2049 * Encapsulate this packet and start it going... 2050 * or fail... 2051 */ 2052 if (cas_encap(sc, m, &bix)) { 2053 ifp->if_flags |= IFF_OACTIVE; 2054 break; 2055 } 2056 2057 IFQ_DEQUEUE(&ifp->if_snd, m); 2058 ifp->if_timer = 5; 2059 } 2060 2061 sc->sc_tx_prod = bix; 2062} 2063