if_athn_pci.c revision 1.9 
1/*	$NetBSD: if_athn_pci.c,v 1.9 2013/12/08 11:32:51 martin Exp $	*/
2/*	$OpenBSD: if_athn_pci.c,v 1.11 2011/01/08 10:02:32 damien Exp $	*/
3
4/*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20/*
21 * PCI front-end for Atheros 802.11a/g/n chipsets.
22 */
23
24#include <sys/cdefs.h>
25__KERNEL_RCSID(0, "$NetBSD: if_athn_pci.c,v 1.9 2013/12/08 11:32:51 martin Exp $");
26
27#include "opt_inet.h"
28
29#include <sys/param.h>
30#include <sys/sockio.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/callout.h>
37#include <sys/device.h>
38
39#include <sys/bus.h>
40#include <sys/intr.h>
41
42#include <net/if.h>
43#include <net/if_ether.h>
44#include <net/if_media.h>
45
46#include <net80211/ieee80211_var.h>
47#include <net80211/ieee80211_amrr.h>
48#include <net80211/ieee80211_radiotap.h>
49
50#include <dev/ic/athnreg.h>
51#include <dev/ic/athnvar.h>
52
53#include <dev/pci/pcireg.h>
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pcidevs.h>
56
57#define PCI_SUBSYSID_ATHEROS_COEX2WIRE		0x309b
58#define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA	0x30aa
59#define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA	0x30ab
60
61#define ATHN_PCI_MMBA	PCI_BAR(0)	/* memory mapped base */
62
63struct athn_pci_softc {
64	struct athn_softc	psc_sc;
65
66	/* PCI specific goo. */
67	pci_chipset_tag_t	psc_pc;
68	pcitag_t		psc_tag;
69	pci_intr_handle_t	psc_pih;
70	void			*psc_ih;
71	bus_space_tag_t		psc_iot;
72	bus_space_handle_t	psc_ioh;
73	bus_size_t		psc_mapsz;
74	int			psc_cap_off;
75};
76
77#define Static static
78
79Static int	athn_pci_match(device_t, cfdata_t, void *);
80Static void	athn_pci_attach(device_t, device_t, void *);
81Static int	athn_pci_detach(device_t, int);
82Static int	athn_pci_activate(device_t, enum devact);
83
84CFATTACH_DECL_NEW(athn_pci, sizeof(struct athn_pci_softc), athn_pci_match,
85    athn_pci_attach, athn_pci_detach, athn_pci_activate);
86
87Static bool	athn_pci_resume(device_t, const pmf_qual_t *);
88Static bool	athn_pci_suspend(device_t, const pmf_qual_t *);
89Static uint32_t	athn_pci_read(struct athn_softc *, uint32_t);
90Static void	athn_pci_write(struct athn_softc *, uint32_t, uint32_t);
91Static void	athn_pci_write_barrier(struct athn_softc *);
92Static void	athn_pci_disable_aspm(struct athn_softc *);
93
94Static int
95athn_pci_match(device_t parent, cfdata_t match, void *aux)
96{
97	static const struct {
98		pci_vendor_id_t		apd_vendor;
99		pci_product_id_t	apd_product;
100	} athn_pci_devices[] = {
101		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 },
102		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 },
103		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 },
104		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 },
105		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 },
106		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 },
107		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 },
108		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 },
109		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 },
110		{ PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 }
111	};
112	struct pci_attach_args *pa = aux;
113	size_t i;
114
115	for (i = 0; i < __arraycount(athn_pci_devices); i++) {
116		if (PCI_VENDOR(pa->pa_id) == athn_pci_devices[i].apd_vendor &&
117		    PCI_PRODUCT(pa->pa_id) == athn_pci_devices[i].apd_product)
118			/*
119			 * Match better than 1, we prefer this driver
120			 * over ath(4)
121			 */
122			return 10;
123	}
124	return 0;
125}
126
127Static void
128athn_pci_attach(device_t parent, device_t self, void *aux)
129{
130	struct athn_pci_softc *psc = device_private(self);
131	struct athn_softc *sc = &psc->psc_sc;
132	struct ieee80211com *ic = &sc->sc_ic;
133	struct pci_attach_args *pa = aux;
134	const char *intrstr;
135	pcireg_t memtype, reg;
136	pci_product_id_t subsysid;
137	int error;
138
139	sc->sc_dev = self;
140	sc->sc_dmat = pa->pa_dmat;
141	psc->psc_pc = pa->pa_pc;
142	psc->psc_tag = pa->pa_tag;
143
144	sc->sc_ops.read = athn_pci_read;
145	sc->sc_ops.write = athn_pci_write;
146	sc->sc_ops.write_barrier = athn_pci_write_barrier;
147
148	/*
149	 * Get the offset of the PCI Express Capability Structure in PCI
150	 * Configuration Space (Linux hardcodes it as 0x60.)
151	 */
152	error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
153	    &psc->psc_cap_off, NULL);
154	if (error != 0) {	/* Found. */
155		sc->sc_disable_aspm = athn_pci_disable_aspm;
156		sc->sc_flags |= ATHN_FLAG_PCIE;
157	}
158	/*
159	 * Noone knows why this shit is necessary but there are claims that
160	 * not doing this may cause very frequent PCI FATAL interrupts from
161	 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483
162	 */
163	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
164	if (reg & 0xff00)
165		pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00);
166
167	/* Change latency timer; default value yields poor results. */
168	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
169	reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
170	reg |= 168 << PCI_LATTIMER_SHIFT;
171	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg);
172
173	/* Determine if bluetooth is also supported (combo chip.) */
174	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
175	subsysid = PCI_PRODUCT(reg);
176	if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA ||
177	    subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA)
178		sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE;
179	else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE)
180		sc->sc_flags |= ATHN_FLAG_BTCOEX2WIRE;
181
182	/*
183	 * Setup memory-mapping of PCI registers.
184	 */
185	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ATHN_PCI_MMBA);
186	if (memtype != PCI_MAPREG_TYPE_MEM &&
187	    memtype != PCI_MAPREG_MEM_TYPE_64BIT) {
188		aprint_error_dev(self, "bad pci register type %d\n",
189		    (int)memtype);
190		goto fail;
191	}
192	error = pci_mapreg_map(pa, ATHN_PCI_MMBA, memtype, 0, &psc->psc_iot,
193	    &psc->psc_ioh, NULL, &psc->psc_mapsz);
194	if (error != 0) {
195		aprint_error_dev(self, "cannot map register space\n");
196		goto fail;
197	}
198
199	/*
200	 * Arrange interrupt line.
201	 */
202	if (pci_intr_map(pa, &psc->psc_pih) != 0) {
203		aprint_error_dev(self, "couldn't map interrupt\n");
204		goto fail1;
205	}
206
207	intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih);
208	psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
209	    athn_intr, sc);
210	if (psc->psc_ih == NULL) {
211		aprint_error_dev(self, "couldn't map interrupt\n");
212		goto fail1;
213	}
214
215	ic->ic_ifp = &sc->sc_if;
216	if (athn_attach(sc) != 0)
217		goto fail2;
218
219	aprint_verbose_dev(self, "interrupting at %s\n", intrstr);
220
221	if (pmf_device_register(self, athn_pci_suspend, athn_pci_resume)) {
222		pmf_class_network_register(self, &sc->sc_if);
223		pmf_device_suspend(self, &sc->sc_qual);
224	}
225	else
226		aprint_error_dev(self, "couldn't establish power handler\n");
227
228	ieee80211_announce(ic);
229	return;
230
231 fail2:
232	pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
233	psc->psc_ih = NULL;
234 fail1:
235	bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz);
236	psc->psc_mapsz = 0;
237 fail:
238	return;
239}
240
241Static int
242athn_pci_detach(device_t self, int flags)
243{
244	struct athn_pci_softc *psc = device_private(self);
245	struct athn_softc *sc = &psc->psc_sc;
246
247	if (psc->psc_ih != NULL) {
248		athn_detach(sc);
249		pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
250		psc->psc_ih = NULL;
251	}
252	if (psc->psc_mapsz > 0) {
253		bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz);
254		psc->psc_mapsz = 0;
255	}
256	return 0;
257}
258
259Static int
260athn_pci_activate(device_t self, enum devact act)
261{
262	struct athn_pci_softc *psc = device_private(self);
263	struct athn_softc *sc = &psc->psc_sc;
264
265	switch (act) {
266	case DVACT_DEACTIVATE:
267		if_deactivate(sc->sc_ic.ic_ifp);
268		break;
269	}
270	return 0;
271}
272
273Static bool
274athn_pci_suspend(device_t self, const pmf_qual_t *qual)
275{
276	struct athn_pci_softc *psc = device_private(self);
277	struct athn_softc *sc = &psc->psc_sc;
278
279	athn_suspend(sc);
280	if (psc->psc_ih != NULL) {
281		pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
282		psc->psc_ih = NULL;
283	}
284	return true;
285}
286
287Static bool
288athn_pci_resume(device_t self, const pmf_qual_t *qual)
289{
290	struct athn_pci_softc *psc = device_private(self);
291	struct athn_softc *sc = &psc->psc_sc;
292	pcireg_t reg;
293
294	/*
295	 * XXX: see comment in athn_attach().
296	 */
297	reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 0x40);
298	if (reg & 0xff00)
299		pci_conf_write(psc->psc_pc, psc->psc_tag, 0x40, reg & ~0xff00);
300
301	psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
302	    athn_intr, sc);
303	if (psc->psc_ih == NULL) {
304		aprint_error_dev(self, "couldn't map interrupt\n");
305		return false;
306	}
307	return athn_resume(sc);
308}
309
310Static uint32_t
311athn_pci_read(struct athn_softc *sc, uint32_t addr)
312{
313	struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
314
315	return bus_space_read_4(psc->psc_iot, psc->psc_ioh, addr);
316}
317
318Static void
319athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
320{
321	struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
322
323	bus_space_write_4(psc->psc_iot, psc->psc_ioh, addr, val);
324}
325
326Static void
327athn_pci_write_barrier(struct athn_softc *sc)
328{
329	struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
330
331	bus_space_barrier(psc->psc_iot, psc->psc_ioh, 0, psc->psc_mapsz,
332	    BUS_SPACE_BARRIER_WRITE);
333}
334
335Static void
336athn_pci_disable_aspm(struct athn_softc *sc)
337{
338	struct athn_pci_softc *psc = (struct athn_pci_softc *)sc;
339	pcireg_t reg;
340
341	/* Disable PCIe Active State Power Management (ASPM). */
342	reg = pci_conf_read(psc->psc_pc, psc->psc_tag,
343	    psc->psc_cap_off + PCIE_LCSR);
344	reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1);
345	pci_conf_write(psc->psc_pc, psc->psc_tag,
346	    psc->psc_cap_off + PCIE_LCSR, reg);
347}
348