1/************************************************************************** 2 3Copyright (c) 2007, Chelsio Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28***************************************************************************/ 29#ifndef T3_CPL_H 30#define T3_CPL_H 31 32enum CPL_opcode { 33 CPL_PASS_OPEN_REQ = 0x1, 34 CPL_PASS_ACCEPT_RPL = 0x2, 35 CPL_ACT_OPEN_REQ = 0x3, 36 CPL_SET_TCB = 0x4, 37 CPL_SET_TCB_FIELD = 0x5, 38 CPL_GET_TCB = 0x6, 39 CPL_PCMD = 0x7, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TX_PKT_LSO = 0x16, 55 CPL_PCMD_READ = 0x17, 56 CPL_BARRIER = 0x18, 57 CPL_TID_RELEASE = 0x1A, 58 59 CPL_CLOSE_LISTSRV_RPL = 0x20, 60 CPL_ERROR = 0x21, 61 CPL_GET_TCB_RPL = 0x22, 62 CPL_L2T_WRITE_RPL = 0x23, 63 CPL_PCMD_READ_RPL = 0x24, 64 CPL_PCMD_RPL = 0x25, 65 CPL_PEER_CLOSE = 0x26, 66 CPL_RTE_DELETE_RPL = 0x27, 67 CPL_RTE_WRITE_RPL = 0x28, 68 CPL_RX_DDP_COMPLETE = 0x29, 69 CPL_RX_PHYS_ADDR = 0x2A, 70 CPL_RX_PKT = 0x2B, 71 CPL_RX_URG_NOTIFY = 0x2C, 72 CPL_SET_TCB_RPL = 0x2D, 73 CPL_SMT_WRITE_RPL = 0x2E, 74 CPL_TX_DATA_ACK = 0x2F, 75 76 CPL_ABORT_REQ_RSS = 0x30, 77 CPL_ABORT_RPL_RSS = 0x31, 78 CPL_CLOSE_CON_RPL = 0x32, 79 CPL_ISCSI_HDR = 0x33, 80 CPL_L2T_READ_RPL = 0x34, 81 CPL_RDMA_CQE = 0x35, 82 CPL_RDMA_CQE_READ_RSP = 0x36, 83 CPL_RDMA_CQE_ERR = 0x37, 84 CPL_RTE_READ_RPL = 0x38, 85 CPL_RX_DATA = 0x39, 86 87 CPL_ACT_OPEN_RPL = 0x40, 88 CPL_PASS_OPEN_RPL = 0x41, 89 CPL_RX_DATA_DDP = 0x42, 90 CPL_SMT_READ_RPL = 0x43, 91 92 CPL_ACT_ESTABLISH = 0x50, 93 CPL_PASS_ESTABLISH = 0x51, 94 95 CPL_PASS_ACCEPT_REQ = 0x70, 96 97 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 98 99 CPL_TX_DMA_ACK = 0xA0, 100 CPL_RDMA_READ_REQ = 0xA1, 101 CPL_RDMA_TERMINATE = 0xA2, 102 CPL_TRACE_PKT = 0xA3, 103 CPL_RDMA_EC_STATUS = 0xA5, 104 105 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 106}; 107 108enum CPL_error { 109 CPL_ERR_NONE = 0, 110 CPL_ERR_TCAM_PARITY = 1, 111 CPL_ERR_TCAM_FULL = 3, 112 CPL_ERR_CONN_RESET = 20, 113 CPL_ERR_CONN_EXIST = 22, 114 CPL_ERR_ARP_MISS = 23, 115 CPL_ERR_BAD_SYN = 24, 116 CPL_ERR_CONN_TIMEDOUT = 30, 117 CPL_ERR_XMIT_TIMEDOUT = 31, 118 CPL_ERR_PERSIST_TIMEDOUT = 32, 119 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 120 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 121 CPL_ERR_RTX_NEG_ADVICE = 35, 122 CPL_ERR_PERSIST_NEG_ADVICE = 36, 123 CPL_ERR_ABORT_FAILED = 42, 124 CPL_ERR_GENERAL = 99 125}; 126 127enum { 128 CPL_CONN_POLICY_AUTO = 0, 129 CPL_CONN_POLICY_ASK = 1, 130 CPL_CONN_POLICY_FILTER = 2, 131 CPL_CONN_POLICY_DENY = 3 132}; 133 134enum { 135 ULP_MODE_NONE = 0, 136 ULP_MODE_TCP_DDP = 1, 137 ULP_MODE_ISCSI = 2, 138 ULP_MODE_RDMA = 4, 139 ULP_MODE_TCPDDP = 5 140}; 141 142enum { 143 ULP_CRC_HEADER = 1 << 0, 144 ULP_CRC_DATA = 1 << 1 145}; 146 147enum { 148 CPL_PASS_OPEN_ACCEPT, 149 CPL_PASS_OPEN_REJECT 150}; 151 152enum { 153 CPL_ABORT_SEND_RST = 0, 154 CPL_ABORT_NO_RST, 155 CPL_ABORT_POST_CLOSE_REQ = 2 156}; 157 158enum { /* TX_PKT_LSO ethernet types */ 159 CPL_ETH_II, 160 CPL_ETH_II_VLAN, 161 CPL_ETH_802_3, 162 CPL_ETH_802_3_VLAN 163}; 164 165enum { /* TCP congestion control algorithms */ 166 CONG_ALG_RENO, 167 CONG_ALG_TAHOE, 168 CONG_ALG_NEWRENO, 169 CONG_ALG_HIGHSPEED 170}; 171 172enum { /* RSS hash type */ 173 RSS_HASH_NONE = 0, 174 RSS_HASH_2_TUPLE = 1 << 0, 175 RSS_HASH_4_TUPLE = 1 << 1 176}; 177 178union opcode_tid { 179 __be32 opcode_tid; 180 __u8 opcode; 181}; 182 183#define S_OPCODE 24 184#define V_OPCODE(x) ((x) << S_OPCODE) 185#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 186#define G_TID(x) ((x) & 0xFFFFFF) 187 188#define S_HASHTYPE 22 189#define M_HASHTYPE 0x3 190#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 191 192#define S_QNUM 0 193#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) 194 195/* tid is assumed to be 24-bits */ 196#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 197 198#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 199 200/* extract the TID from a CPL command */ 201#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 202 203struct tcp_options { 204 __be16 mss; 205 __u8 wsf; 206#if defined(__LITTLE_ENDIAN_BITFIELD) 207 __u8 :5; 208 __u8 ecn:1; 209 __u8 sack:1; 210 __u8 tstamp:1; 211#else 212 __u8 tstamp:1; 213 __u8 sack:1; 214 __u8 ecn:1; 215 __u8 :5; 216#endif 217}; 218 219struct rss_header { 220 __u8 opcode; 221#if defined(__LITTLE_ENDIAN_BITFIELD) 222 __u8 cpu_idx:6; 223 __u8 hash_type:2; 224#else 225 __u8 hash_type:2; 226 __u8 cpu_idx:6; 227#endif 228 __be16 cq_idx; 229 __be32 rss_hash_val; 230}; 231 232#ifndef CHELSIO_FW 233struct work_request_hdr { 234 __be32 wr_hi; 235 __be32 wr_lo; 236}; 237 238/* wr_hi fields */ 239#define S_WR_SGE_CREDITS 0 240#define M_WR_SGE_CREDITS 0xFF 241#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 242#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 243 244#define S_WR_SGLSFLT 8 245#define M_WR_SGLSFLT 0xFF 246#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 247#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 248 249#define S_WR_BCNTLFLT 16 250#define M_WR_BCNTLFLT 0xF 251#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 252#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 253 254/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before 255 * and after the BYPASS WR if the ATOMIC bit is set. 256 */ 257#define S_WR_ATOMIC 16 258#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 259#define F_WR_ATOMIC V_WR_ATOMIC(1U) 260 261/* Applicable to BYPASS WRs only: the uP will flush buffered non abort 262 * related WRs. 263 */ 264#define S_WR_FLUSH 17 265#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 266#define F_WR_FLUSH V_WR_FLUSH(1U) 267 268#define S_WR_DATATYPE 20 269#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 270#define F_WR_DATATYPE V_WR_DATATYPE(1U) 271 272#define S_WR_COMPL 21 273#define V_WR_COMPL(x) ((x) << S_WR_COMPL) 274#define F_WR_COMPL V_WR_COMPL(1U) 275 276#define S_WR_EOP 22 277#define V_WR_EOP(x) ((x) << S_WR_EOP) 278#define F_WR_EOP V_WR_EOP(1U) 279 280#define S_WR_SOP 23 281#define V_WR_SOP(x) ((x) << S_WR_SOP) 282#define F_WR_SOP V_WR_SOP(1U) 283 284#define S_WR_OP 24 285#define M_WR_OP 0xFF 286#define V_WR_OP(x) ((x) << S_WR_OP) 287#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 288 289/* wr_lo fields */ 290#define S_WR_LEN 0 291#define M_WR_LEN 0xFF 292#define V_WR_LEN(x) ((x) << S_WR_LEN) 293#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 294 295#define S_WR_TID 8 296#define M_WR_TID 0xFFFFF 297#define V_WR_TID(x) ((x) << S_WR_TID) 298#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 299 300#define S_WR_CR_FLUSH 30 301#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 302#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 303 304#define S_WR_GEN 31 305#define V_WR_GEN(x) ((x) << S_WR_GEN) 306#define F_WR_GEN V_WR_GEN(1U) 307 308# define WR_HDR struct work_request_hdr wr 309# define RSS_HDR 310#else 311# define WR_HDR 312# define RSS_HDR struct rss_header rss_hdr; 313#endif 314 315/* option 0 lower-half fields */ 316#define S_CPL_STATUS 0 317#define M_CPL_STATUS 0xFF 318#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 319#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 320 321#define S_INJECT_TIMER 6 322#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 323#define F_INJECT_TIMER V_INJECT_TIMER(1U) 324 325#define S_NO_OFFLOAD 7 326#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 327#define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 328 329#define S_ULP_MODE 8 330#define M_ULP_MODE 0xF 331#define V_ULP_MODE(x) ((x) << S_ULP_MODE) 332#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 333 334#define S_RCV_BUFSIZ 12 335#define M_RCV_BUFSIZ 0x3FFF 336#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 337#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 338 339#define S_TOS 26 340#define M_TOS 0x3F 341#define V_TOS(x) ((x) << S_TOS) 342#define G_TOS(x) (((x) >> S_TOS) & M_TOS) 343 344/* option 0 upper-half fields */ 345#define S_DELACK 0 346#define V_DELACK(x) ((x) << S_DELACK) 347#define F_DELACK V_DELACK(1U) 348 349#define S_NO_CONG 1 350#define V_NO_CONG(x) ((x) << S_NO_CONG) 351#define F_NO_CONG V_NO_CONG(1U) 352 353#define S_SRC_MAC_SEL 2 354#define M_SRC_MAC_SEL 0x3 355#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 356#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 357 358#define S_L2T_IDX 4 359#define M_L2T_IDX 0x7FF 360#define V_L2T_IDX(x) ((x) << S_L2T_IDX) 361#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 362 363#define S_TX_CHANNEL 15 364#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 365#define F_TX_CHANNEL V_TX_CHANNEL(1U) 366 367#define S_TCAM_BYPASS 16 368#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 369#define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 370 371#define S_NAGLE 17 372#define V_NAGLE(x) ((x) << S_NAGLE) 373#define F_NAGLE V_NAGLE(1U) 374 375#define S_WND_SCALE 18 376#define M_WND_SCALE 0xF 377#define V_WND_SCALE(x) ((x) << S_WND_SCALE) 378#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 379 380#define S_KEEP_ALIVE 22 381#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 382#define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 383 384#define S_MAX_RETRANS 23 385#define M_MAX_RETRANS 0xF 386#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 387#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 388 389#define S_MAX_RETRANS_OVERRIDE 27 390#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 391#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 392 393#define S_MSS_IDX 28 394#define M_MSS_IDX 0xF 395#define V_MSS_IDX(x) ((x) << S_MSS_IDX) 396#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 397 398/* option 1 fields */ 399#define S_RSS_ENABLE 0 400#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 401#define F_RSS_ENABLE V_RSS_ENABLE(1U) 402 403#define S_RSS_MASK_LEN 1 404#define M_RSS_MASK_LEN 0x7 405#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 406#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 407 408#define S_CPU_IDX 4 409#define M_CPU_IDX 0x3F 410#define V_CPU_IDX(x) ((x) << S_CPU_IDX) 411#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 412 413#define S_OPT1_VLAN 6 414#define M_OPT1_VLAN 0xFFF 415#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 416#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 417 418#define S_MAC_MATCH_VALID 18 419#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 420#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 421 422#define S_CONN_POLICY 19 423#define M_CONN_POLICY 0x3 424#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 425#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 426 427#define S_SYN_DEFENSE 21 428#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 429#define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 430 431#define S_VLAN_PRI 22 432#define M_VLAN_PRI 0x3 433#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 434#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 435 436#define S_VLAN_PRI_VALID 24 437#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 438#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 439 440#define S_PKT_TYPE 25 441#define M_PKT_TYPE 0x3 442#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 443#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 444 445#define S_MAC_MATCH 27 446#define M_MAC_MATCH 0x1F 447#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 448#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 449 450/* option 2 fields */ 451#define S_CPU_INDEX 0 452#define M_CPU_INDEX 0x7F 453#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 454#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 455 456#define S_CPU_INDEX_VALID 7 457#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 458#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 459 460#define S_RX_COALESCE 8 461#define M_RX_COALESCE 0x3 462#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 463#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 464 465#define S_RX_COALESCE_VALID 10 466#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 467#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 468 469#define S_CONG_CONTROL_FLAVOR 11 470#define M_CONG_CONTROL_FLAVOR 0x3 471#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 472#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 473 474#define S_PACING_FLAVOR 13 475#define M_PACING_FLAVOR 0x3 476#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 477#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 478 479#define S_FLAVORS_VALID 15 480#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 481#define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 482 483#define S_RX_FC_DISABLE 16 484#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 485#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 486 487#define S_RX_FC_VALID 17 488#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 489#define F_RX_FC_VALID V_RX_FC_VALID(1U) 490 491struct cpl_pass_open_req { 492 WR_HDR; 493 union opcode_tid ot; 494 __be16 local_port; 495 __be16 peer_port; 496 __be32 local_ip; 497 __be32 peer_ip; 498 __be32 opt0h; 499 __be32 opt0l; 500 __be32 peer_netmask; 501 __be32 opt1; 502}; 503 504struct cpl_pass_open_rpl { 505 RSS_HDR 506 union opcode_tid ot; 507 __be16 local_port; 508 __be16 peer_port; 509 __be32 local_ip; 510 __be32 peer_ip; 511 __u8 resvd[7]; 512 __u8 status; 513}; 514 515struct cpl_pass_establish { 516 RSS_HDR 517 union opcode_tid ot; 518 __be16 local_port; 519 __be16 peer_port; 520 __be32 local_ip; 521 __be32 peer_ip; 522 __be32 tos_tid; 523 __be16 l2t_idx; 524 __be16 tcp_opt; 525 __be32 snd_isn; 526 __be32 rcv_isn; 527}; 528 529/* cpl_pass_establish.tos_tid fields */ 530#define S_PASS_OPEN_TID 0 531#define M_PASS_OPEN_TID 0xFFFFFF 532#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 533#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 534 535#define S_PASS_OPEN_TOS 24 536#define M_PASS_OPEN_TOS 0xFF 537#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 538#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 539 540/* cpl_pass_establish.l2t_idx fields */ 541#define S_L2T_IDX16 5 542#define M_L2T_IDX16 0x7FF 543#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 544#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 545 546/* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 547#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 548#define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 549#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 550#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 551#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 552 553struct cpl_pass_accept_req { 554 RSS_HDR 555 union opcode_tid ot; 556 __be16 local_port; 557 __be16 peer_port; 558 __be32 local_ip; 559 __be32 peer_ip; 560 __be32 tos_tid; 561 struct tcp_options tcp_options; 562 __u8 dst_mac[6]; 563 __be16 vlan_tag; 564 __u8 src_mac[6]; 565#if defined(__LITTLE_ENDIAN_BITFIELD) 566 __u8 :3; 567 __u8 addr_idx:3; 568 __u8 port_idx:1; 569 __u8 exact_match:1; 570#else 571 __u8 exact_match:1; 572 __u8 port_idx:1; 573 __u8 addr_idx:3; 574 __u8 :3; 575#endif 576 __u8 rsvd; 577 __be32 rcv_isn; 578 __be32 rsvd2; 579}; 580 581struct cpl_pass_accept_rpl { 582 WR_HDR; 583 union opcode_tid ot; 584 __be32 opt2; 585 __be32 rsvd; 586 __be32 peer_ip; 587 __be32 opt0h; 588 __be32 opt0l_status; 589}; 590 591struct cpl_act_open_req { 592 WR_HDR; 593 union opcode_tid ot; 594 __be16 local_port; 595 __be16 peer_port; 596 __be32 local_ip; 597 __be32 peer_ip; 598 __be32 opt0h; 599 __be32 opt0l; 600 __be32 params; 601 __be32 opt2; 602}; 603 604/* cpl_act_open_req.params fields */ 605#define S_AOPEN_VLAN_PRI 9 606#define M_AOPEN_VLAN_PRI 0x3 607#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 608#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 609 610#define S_AOPEN_VLAN_PRI_VALID 11 611#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 612#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 613 614#define S_AOPEN_PKT_TYPE 12 615#define M_AOPEN_PKT_TYPE 0x3 616#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 617#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 618 619#define S_AOPEN_MAC_MATCH 14 620#define M_AOPEN_MAC_MATCH 0x1F 621#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 622#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 623 624#define S_AOPEN_MAC_MATCH_VALID 19 625#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 626#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 627 628#define S_AOPEN_IFF_VLAN 20 629#define M_AOPEN_IFF_VLAN 0xFFF 630#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 631#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 632 633struct cpl_act_open_rpl { 634 RSS_HDR 635 union opcode_tid ot; 636 __be16 local_port; 637 __be16 peer_port; 638 __be32 local_ip; 639 __be32 peer_ip; 640 __be32 atid; 641 __u8 rsvd[3]; 642 __u8 status; 643}; 644 645struct cpl_act_establish { 646 RSS_HDR 647 union opcode_tid ot; 648 __be16 local_port; 649 __be16 peer_port; 650 __be32 local_ip; 651 __be32 peer_ip; 652 __be32 tos_tid; 653 __be16 l2t_idx; 654 __be16 tcp_opt; 655 __be32 snd_isn; 656 __be32 rcv_isn; 657}; 658 659struct cpl_get_tcb { 660 WR_HDR; 661 union opcode_tid ot; 662 __be16 cpuno; 663 __be16 rsvd; 664}; 665 666struct cpl_get_tcb_rpl { 667 RSS_HDR 668 union opcode_tid ot; 669 __u8 rsvd; 670 __u8 status; 671 __be16 len; 672}; 673 674struct cpl_set_tcb { 675 WR_HDR; 676 union opcode_tid ot; 677 __u8 reply; 678 __u8 cpu_idx; 679 __be16 len; 680}; 681 682/* cpl_set_tcb.reply fields */ 683#define S_NO_REPLY 7 684#define V_NO_REPLY(x) ((x) << S_NO_REPLY) 685#define F_NO_REPLY V_NO_REPLY(1U) 686 687struct cpl_set_tcb_field { 688 WR_HDR; 689 union opcode_tid ot; 690 __u8 reply; 691 __u8 cpu_idx; 692 __be16 word; 693 __be64 mask; 694 __be64 val; 695}; 696 697struct cpl_set_tcb_rpl { 698 RSS_HDR 699 union opcode_tid ot; 700 __u8 rsvd[3]; 701 __u8 status; 702}; 703 704struct cpl_pcmd { 705 WR_HDR; 706 union opcode_tid ot; 707 __u8 rsvd[3]; 708#if defined(__LITTLE_ENDIAN_BITFIELD) 709 __u8 src:1; 710 __u8 bundle:1; 711 __u8 channel:1; 712 __u8 :5; 713#else 714 __u8 :5; 715 __u8 channel:1; 716 __u8 bundle:1; 717 __u8 src:1; 718#endif 719 __be32 pcmd_parm[2]; 720}; 721 722struct cpl_pcmd_reply { 723 RSS_HDR 724 union opcode_tid ot; 725 __u8 status; 726 __u8 rsvd; 727 __be16 len; 728}; 729 730struct cpl_close_con_req { 731 WR_HDR; 732 union opcode_tid ot; 733 __be32 rsvd; 734}; 735 736struct cpl_close_con_rpl { 737 RSS_HDR 738 union opcode_tid ot; 739 __u8 rsvd[3]; 740 __u8 status; 741 __be32 snd_nxt; 742 __be32 rcv_nxt; 743}; 744 745struct cpl_close_listserv_req { 746 WR_HDR; 747 union opcode_tid ot; 748 __u8 rsvd0; 749 __u8 cpu_idx; 750 __be16 rsvd1; 751}; 752 753struct cpl_close_listserv_rpl { 754 RSS_HDR 755 union opcode_tid ot; 756 __u8 rsvd[3]; 757 __u8 status; 758}; 759 760struct cpl_abort_req_rss { 761 RSS_HDR 762 union opcode_tid ot; 763 __be32 rsvd0; 764 __u8 rsvd1; 765 __u8 status; 766 __u8 rsvd2[6]; 767}; 768 769struct cpl_abort_req { 770 WR_HDR; 771 union opcode_tid ot; 772 __be32 rsvd0; 773 __u8 rsvd1; 774 __u8 cmd; 775 __u8 rsvd2[6]; 776}; 777 778struct cpl_abort_rpl_rss { 779 RSS_HDR 780 union opcode_tid ot; 781 __be32 rsvd0; 782 __u8 rsvd1; 783 __u8 status; 784 __u8 rsvd2[6]; 785}; 786 787struct cpl_abort_rpl { 788 WR_HDR; 789 union opcode_tid ot; 790 __be32 rsvd0; 791 __u8 rsvd1; 792 __u8 cmd; 793 __u8 rsvd2[6]; 794}; 795 796struct cpl_peer_close { 797 RSS_HDR 798 union opcode_tid ot; 799 __be32 rcv_nxt; 800}; 801 802struct tx_data_wr { 803 __be32 wr_hi; 804 __be32 wr_lo; 805 __be32 len; 806 __be32 flags; 807 __be32 sndseq; 808 __be32 param; 809}; 810 811/* tx_data_wr.flags fields */ 812#define S_TX_ACK_PAGES 21 813#define M_TX_ACK_PAGES 0x7 814#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 815#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 816 817/* tx_data_wr.param fields */ 818#define S_TX_PORT 0 819#define M_TX_PORT 0x7 820#define V_TX_PORT(x) ((x) << S_TX_PORT) 821#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 822 823#define S_TX_MSS 4 824#define M_TX_MSS 0xF 825#define V_TX_MSS(x) ((x) << S_TX_MSS) 826#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 827 828#define S_TX_QOS 8 829#define M_TX_QOS 0xFF 830#define V_TX_QOS(x) ((x) << S_TX_QOS) 831#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 832 833#define S_TX_SNDBUF 16 834#define M_TX_SNDBUF 0xFFFF 835#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 836#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 837 838struct cpl_tx_data { 839 union opcode_tid ot; 840 __be32 len; 841 __be32 rsvd; 842 __be16 urg; 843 __be16 flags; 844}; 845 846/* cpl_tx_data.flags fields */ 847#define S_TX_ULP_SUBMODE 6 848#define M_TX_ULP_SUBMODE 0xF 849#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 850#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 851 852#define S_TX_ULP_MODE 10 853#define M_TX_ULP_MODE 0xF 854#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 855#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 856 857#define S_TX_SHOVE 14 858#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 859#define F_TX_SHOVE V_TX_SHOVE(1U) 860 861#define S_TX_MORE 15 862#define V_TX_MORE(x) ((x) << S_TX_MORE) 863#define F_TX_MORE V_TX_MORE(1U) 864 865/* additional tx_data_wr.flags fields */ 866#define S_TX_CPU_IDX 0 867#define M_TX_CPU_IDX 0x3F 868#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 869#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 870 871#define S_TX_URG 16 872#define V_TX_URG(x) ((x) << S_TX_URG) 873#define F_TX_URG V_TX_URG(1U) 874 875#define S_TX_CLOSE 17 876#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 877#define F_TX_CLOSE V_TX_CLOSE(1U) 878 879#define S_TX_INIT 18 880#define V_TX_INIT(x) ((x) << S_TX_INIT) 881#define F_TX_INIT V_TX_INIT(1U) 882 883#define S_TX_IMM_ACK 19 884#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 885#define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 886 887#define S_TX_IMM_DMA 20 888#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 889#define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 890 891struct cpl_tx_data_ack { 892 RSS_HDR 893 union opcode_tid ot; 894 __be32 ack_seq; 895}; 896 897struct cpl_wr_ack { 898 RSS_HDR 899 union opcode_tid ot; 900 __be16 credits; 901 __be16 rsvd; 902 __be32 snd_nxt; 903 __be32 snd_una; 904}; 905 906struct cpl_rdma_ec_status { 907 RSS_HDR 908 union opcode_tid ot; 909 __u8 rsvd[3]; 910 __u8 status; 911}; 912 913struct mngt_pktsched_wr { 914 __be32 wr_hi; 915 __be32 wr_lo; 916 __u8 mngt_opcode; 917 __u8 rsvd[7]; 918 __u8 sched; 919 __u8 idx; 920 __u8 min; 921 __u8 max; 922 __u8 binding; 923 __u8 rsvd1[3]; 924}; 925 926struct cpl_iscsi_hdr { 927 RSS_HDR 928 union opcode_tid ot; 929 __be16 pdu_len_ddp; 930 __be16 len; 931 __be32 seq; 932 __be16 urg; 933 __u8 rsvd; 934 __u8 status; 935}; 936 937/* cpl_iscsi_hdr.pdu_len_ddp fields */ 938#define S_ISCSI_PDU_LEN 0 939#define M_ISCSI_PDU_LEN 0x7FFF 940#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 941#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 942 943#define S_ISCSI_DDP 15 944#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 945#define F_ISCSI_DDP V_ISCSI_DDP(1U) 946 947struct cpl_rx_data { 948 RSS_HDR 949 union opcode_tid ot; 950 __be16 rsvd; 951 __be16 len; 952 __be32 seq; 953 __be16 urg; 954#if defined(__LITTLE_ENDIAN_BITFIELD) 955 __u8 dack_mode:2; 956 __u8 psh:1; 957 __u8 heartbeat:1; 958 __u8 :4; 959#else 960 __u8 :4; 961 __u8 heartbeat:1; 962 __u8 psh:1; 963 __u8 dack_mode:2; 964#endif 965 __u8 status; 966}; 967 968struct cpl_rx_data_ack { 969 WR_HDR; 970 union opcode_tid ot; 971 __be32 credit_dack; 972}; 973 974/* cpl_rx_data_ack.ack_seq fields */ 975#define S_RX_CREDITS 0 976#define M_RX_CREDITS 0x7FFFFFF 977#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 978#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 979 980#define S_RX_MODULATE 27 981#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 982#define F_RX_MODULATE V_RX_MODULATE(1U) 983 984#define S_RX_FORCE_ACK 28 985#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 986#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 987 988#define S_RX_DACK_MODE 29 989#define M_RX_DACK_MODE 0x3 990#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 991#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 992 993#define S_RX_DACK_CHANGE 31 994#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 995#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 996 997struct cpl_rx_urg_notify { 998 RSS_HDR 999 union opcode_tid ot; 1000 __be32 seq; 1001}; 1002 1003struct cpl_rx_ddp_complete { 1004 RSS_HDR 1005 union opcode_tid ot; 1006 __be32 ddp_report; 1007}; 1008 1009struct cpl_rx_data_ddp { 1010 RSS_HDR 1011 union opcode_tid ot; 1012 __be16 urg; 1013 __be16 len; 1014 __be32 seq; 1015 union { 1016 __be32 nxt_seq; 1017 __be32 ddp_report; 1018 } u; 1019 __be32 ulp_crc; 1020 __be32 ddpvld_status; 1021}; 1022 1023/* cpl_rx_data_ddp.ddpvld_status fields */ 1024#define S_DDP_STATUS 0 1025#define M_DDP_STATUS 0xFF 1026#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1027#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1028 1029#define S_DDP_VALID 15 1030#define M_DDP_VALID 0x1FFFF 1031#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1032#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1033 1034#define S_DDP_PPOD_MISMATCH 15 1035#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1036#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1037 1038#define S_DDP_PDU 16 1039#define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1040#define F_DDP_PDU V_DDP_PDU(1U) 1041 1042#define S_DDP_LLIMIT_ERR 17 1043#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1044#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1045 1046#define S_DDP_PPOD_PARITY_ERR 18 1047#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1048#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1049 1050#define S_DDP_PADDING_ERR 19 1051#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1052#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1053 1054#define S_DDP_HDRCRC_ERR 20 1055#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1056#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1057 1058#define S_DDP_DATACRC_ERR 21 1059#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1060#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1061 1062#define S_DDP_INVALID_TAG 22 1063#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1064#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1065 1066#define S_DDP_ULIMIT_ERR 23 1067#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1068#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1069 1070#define S_DDP_OFFSET_ERR 24 1071#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1072#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1073 1074#define S_DDP_COLOR_ERR 25 1075#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1076#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1077 1078#define S_DDP_TID_MISMATCH 26 1079#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1080#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1081 1082#define S_DDP_INVALID_PPOD 27 1083#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1084#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1085 1086#define S_DDP_ULP_MODE 28 1087#define M_DDP_ULP_MODE 0xF 1088#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1089#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1090 1091/* cpl_rx_data_ddp.ddp_report fields */ 1092#define S_DDP_OFFSET 0 1093#define M_DDP_OFFSET 0x3FFFFF 1094#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1095#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1096 1097#define S_DDP_URG 24 1098#define V_DDP_URG(x) ((x) << S_DDP_URG) 1099#define F_DDP_URG V_DDP_URG(1U) 1100 1101#define S_DDP_PSH 25 1102#define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1103#define F_DDP_PSH V_DDP_PSH(1U) 1104 1105#define S_DDP_BUF_COMPLETE 26 1106#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1107#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1108 1109#define S_DDP_BUF_TIMED_OUT 27 1110#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1111#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1112 1113#define S_DDP_BUF_IDX 28 1114#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1115#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1116 1117struct cpl_tx_pkt { 1118 WR_HDR; 1119 __be32 cntrl; 1120 __be32 len; 1121}; 1122 1123struct cpl_tx_pkt_lso { 1124 WR_HDR; 1125 __be32 cntrl; 1126 __be32 len; 1127 1128 __be32 rsvd; 1129 __be32 lso_info; 1130}; 1131 1132/* cpl_tx_pkt*.cntrl fields */ 1133#define S_TXPKT_VLAN 0 1134#define M_TXPKT_VLAN 0xFFFF 1135#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1136#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1137 1138#define S_TXPKT_INTF 16 1139#define M_TXPKT_INTF 0xF 1140#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1141#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1142 1143#define S_TXPKT_IPCSUM_DIS 20 1144#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1145#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1146 1147#define S_TXPKT_L4CSUM_DIS 21 1148#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1149#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1150 1151#define S_TXPKT_VLAN_VLD 22 1152#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1153#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1154 1155#define S_TXPKT_LOOPBACK 23 1156#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1157#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1158 1159#define S_TXPKT_OPCODE 24 1160#define M_TXPKT_OPCODE 0xFF 1161#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1162#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1163 1164/* cpl_tx_pkt_lso.lso_info fields */ 1165#define S_LSO_MSS 0 1166#define M_LSO_MSS 0x3FFF 1167#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1168#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1169 1170#define S_LSO_ETH_TYPE 14 1171#define M_LSO_ETH_TYPE 0x3 1172#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1173#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1174 1175#define S_LSO_TCPHDR_WORDS 16 1176#define M_LSO_TCPHDR_WORDS 0xF 1177#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1178#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1179 1180#define S_LSO_IPHDR_WORDS 20 1181#define M_LSO_IPHDR_WORDS 0xF 1182#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1183#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1184 1185#define S_LSO_IPV6 24 1186#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1187#define F_LSO_IPV6 V_LSO_IPV6(1U) 1188 1189struct cpl_trace_pkt { 1190#ifdef CHELSIO_FW 1191 __u8 rss_opcode; 1192#if defined(__LITTLE_ENDIAN_BITFIELD) 1193 __u8 err:1; 1194 __u8 :7; 1195#else 1196 __u8 :7; 1197 __u8 err:1; 1198#endif 1199 __u8 rsvd0; 1200#if defined(__LITTLE_ENDIAN_BITFIELD) 1201 __u8 qid:4; 1202 __u8 :4; 1203#else 1204 __u8 :4; 1205 __u8 qid:4; 1206#endif 1207 __be32 tstamp; 1208#endif /* CHELSIO_FW */ 1209 1210 __u8 opcode; 1211#if defined(__LITTLE_ENDIAN_BITFIELD) 1212 __u8 iff:4; 1213 __u8 :4; 1214#else 1215 __u8 :4; 1216 __u8 iff:4; 1217#endif 1218 __u8 rsvd[4]; 1219 __be16 len; 1220}; 1221 1222struct cpl_rx_pkt { 1223 RSS_HDR 1224 __u8 opcode; 1225#if defined(__LITTLE_ENDIAN_BITFIELD) 1226 __u8 iff:4; 1227 __u8 csum_valid:1; 1228 __u8 ipmi_pkt:1; 1229 __u8 vlan_valid:1; 1230 __u8 fragment:1; 1231#else 1232 __u8 fragment:1; 1233 __u8 vlan_valid:1; 1234 __u8 ipmi_pkt:1; 1235 __u8 csum_valid:1; 1236 __u8 iff:4; 1237#endif 1238 __be16 csum; 1239 __be16 vlan; 1240 __be16 len; 1241}; 1242 1243struct cpl_l2t_write_req { 1244 WR_HDR; 1245 union opcode_tid ot; 1246 __be32 params; 1247 __u8 rsvd[2]; 1248 __u8 dst_mac[6]; 1249}; 1250 1251/* cpl_l2t_write_req.params fields */ 1252#define S_L2T_W_IDX 0 1253#define M_L2T_W_IDX 0x7FF 1254#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1255#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1256 1257#define S_L2T_W_VLAN 11 1258#define M_L2T_W_VLAN 0xFFF 1259#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1260#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1261 1262#define S_L2T_W_IFF 23 1263#define M_L2T_W_IFF 0xF 1264#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1265#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1266 1267#define S_L2T_W_PRIO 27 1268#define M_L2T_W_PRIO 0x7 1269#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1270#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1271 1272struct cpl_l2t_write_rpl { 1273 RSS_HDR 1274 union opcode_tid ot; 1275 __u8 status; 1276 __u8 rsvd[3]; 1277}; 1278 1279struct cpl_l2t_read_req { 1280 WR_HDR; 1281 union opcode_tid ot; 1282 __be16 rsvd; 1283 __be16 l2t_idx; 1284}; 1285 1286struct cpl_l2t_read_rpl { 1287 RSS_HDR 1288 union opcode_tid ot; 1289 __be32 params; 1290 __u8 rsvd[2]; 1291 __u8 dst_mac[6]; 1292}; 1293 1294/* cpl_l2t_read_rpl.params fields */ 1295#define S_L2T_R_PRIO 0 1296#define M_L2T_R_PRIO 0x7 1297#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1298#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1299 1300#define S_L2T_R_VLAN 8 1301#define M_L2T_R_VLAN 0xFFF 1302#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1303#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1304 1305#define S_L2T_R_IFF 20 1306#define M_L2T_R_IFF 0xF 1307#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1308#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1309 1310#define S_L2T_STATUS 24 1311#define M_L2T_STATUS 0xFF 1312#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1313#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1314 1315struct cpl_smt_write_req { 1316 WR_HDR; 1317 union opcode_tid ot; 1318 __u8 rsvd0; 1319#if defined(__LITTLE_ENDIAN_BITFIELD) 1320 __u8 mtu_idx:4; 1321 __u8 iff:4; 1322#else 1323 __u8 iff:4; 1324 __u8 mtu_idx:4; 1325#endif 1326 __be16 rsvd2; 1327 __be16 rsvd3; 1328 __u8 src_mac1[6]; 1329 __be16 rsvd4; 1330 __u8 src_mac0[6]; 1331}; 1332 1333struct cpl_smt_write_rpl { 1334 RSS_HDR 1335 union opcode_tid ot; 1336 __u8 status; 1337 __u8 rsvd[3]; 1338}; 1339 1340struct cpl_smt_read_req { 1341 WR_HDR; 1342 union opcode_tid ot; 1343 __u8 rsvd0; 1344#if defined(__LITTLE_ENDIAN_BITFIELD) 1345 __u8 :4; 1346 __u8 iff:4; 1347#else 1348 __u8 iff:4; 1349 __u8 :4; 1350#endif 1351 __be16 rsvd2; 1352}; 1353 1354struct cpl_smt_read_rpl { 1355 RSS_HDR 1356 union opcode_tid ot; 1357 __u8 status; 1358#if defined(__LITTLE_ENDIAN_BITFIELD) 1359 __u8 mtu_idx:4; 1360 __u8 :4; 1361#else 1362 __u8 :4; 1363 __u8 mtu_idx:4; 1364#endif 1365 __be16 rsvd2; 1366 __be16 rsvd3; 1367 __u8 src_mac1[6]; 1368 __be16 rsvd4; 1369 __u8 src_mac0[6]; 1370}; 1371 1372struct cpl_rte_delete_req { 1373 WR_HDR; 1374 union opcode_tid ot; 1375 __be32 params; 1376}; 1377 1378/* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1379#define S_RTE_REQ_LUT_IX 8 1380#define M_RTE_REQ_LUT_IX 0x7FF 1381#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1382#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1383 1384#define S_RTE_REQ_LUT_BASE 19 1385#define M_RTE_REQ_LUT_BASE 0x7FF 1386#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1387#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1388 1389#define S_RTE_READ_REQ_SELECT 31 1390#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1391#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1392 1393struct cpl_rte_delete_rpl { 1394 RSS_HDR 1395 union opcode_tid ot; 1396 __u8 status; 1397 __u8 rsvd[3]; 1398}; 1399 1400struct cpl_rte_write_req { 1401 WR_HDR; 1402 union opcode_tid ot; 1403#if defined(__LITTLE_ENDIAN_BITFIELD) 1404 __u8 :6; 1405 __u8 write_tcam:1; 1406 __u8 write_l2t_lut:1; 1407#else 1408 __u8 write_l2t_lut:1; 1409 __u8 write_tcam:1; 1410 __u8 :6; 1411#endif 1412 __u8 rsvd[3]; 1413 __be32 lut_params; 1414 __be16 rsvd2; 1415 __be16 l2t_idx; 1416 __be32 netmask; 1417 __be32 faddr; 1418}; 1419 1420/* cpl_rte_write_req.lut_params fields */ 1421#define S_RTE_WRITE_REQ_LUT_IX 10 1422#define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1423#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1424#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1425 1426#define S_RTE_WRITE_REQ_LUT_BASE 21 1427#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1428#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1429#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1430 1431struct cpl_rte_write_rpl { 1432 RSS_HDR 1433 union opcode_tid ot; 1434 __u8 status; 1435 __u8 rsvd[3]; 1436}; 1437 1438struct cpl_rte_read_req { 1439 WR_HDR; 1440 union opcode_tid ot; 1441 __be32 params; 1442}; 1443 1444struct cpl_rte_read_rpl { 1445 RSS_HDR 1446 union opcode_tid ot; 1447 __u8 status; 1448 __u8 rsvd0; 1449 __be16 l2t_idx; 1450#if defined(__LITTLE_ENDIAN_BITFIELD) 1451 __u8 :7; 1452 __u8 select:1; 1453#else 1454 __u8 select:1; 1455 __u8 :7; 1456#endif 1457 __u8 rsvd2[3]; 1458 __be32 addr; 1459}; 1460 1461struct cpl_tid_release { 1462 WR_HDR; 1463 union opcode_tid ot; 1464 __be32 rsvd; 1465}; 1466 1467struct cpl_barrier { 1468 WR_HDR; 1469 __u8 opcode; 1470 __u8 rsvd[7]; 1471}; 1472 1473struct cpl_rdma_read_req { 1474 __u8 opcode; 1475 __u8 rsvd[15]; 1476}; 1477 1478struct cpl_rdma_terminate { 1479#ifdef CHELSIO_FW 1480 __u8 opcode; 1481 __u8 rsvd[2]; 1482#if defined(__LITTLE_ENDIAN_BITFIELD) 1483 __u8 rspq:3; 1484 __u8 :5; 1485#else 1486 __u8 :5; 1487 __u8 rspq:3; 1488#endif 1489 __be32 tid_len; 1490#endif 1491 __be32 msn; 1492 __be32 mo; 1493 __u8 data[0]; 1494}; 1495 1496/* cpl_rdma_terminate.tid_len fields */ 1497#define S_FLIT_CNT 0 1498#define M_FLIT_CNT 0xFF 1499#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1500#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1501 1502#define S_TERM_TID 8 1503#define M_TERM_TID 0xFFFFF 1504#define V_TERM_TID(x) ((x) << S_TERM_TID) 1505#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1506 1507/* ULP_TX opcodes */ 1508enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1509 1510#define S_ULPTX_CMD 28 1511#define M_ULPTX_CMD 0xF 1512#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1513 1514#define S_ULPTX_NFLITS 0 1515#define M_ULPTX_NFLITS 0xFF 1516#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1517 1518struct ulp_mem_io { 1519 WR_HDR; 1520 __be32 cmd_lock_addr; 1521 __be32 len; 1522}; 1523 1524/* ulp_mem_io.cmd_lock_addr fields */ 1525#define S_ULP_MEMIO_ADDR 0 1526#define M_ULP_MEMIO_ADDR 0x7FFFFFF 1527#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1528 1529#define S_ULP_MEMIO_LOCK 27 1530#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1531#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1532 1533/* ulp_mem_io.len fields */ 1534#define S_ULP_MEMIO_DATA_LEN 28 1535#define M_ULP_MEMIO_DATA_LEN 0xF 1536#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1537 1538struct ulp_txpkt { 1539 __be32 cmd_dest; 1540 __be32 len; 1541}; 1542 1543/* ulp_txpkt.cmd_dest fields */ 1544#define S_ULP_TXPKT_DEST 24 1545#define M_ULP_TXPKT_DEST 0xF 1546#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1547 1548#endif /* T3_CPL_H */ 1549