cs4281.c revision 1.54
1/* $NetBSD: cs4281.c,v 1.54 2019/03/16 12:09:58 isaki Exp $ */ 2 3/* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45#include <sys/cdefs.h> 46__KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.54 2019/03/16 12:09:58 isaki Exp $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/kernel.h> 51#include <sys/malloc.h> 52#include <sys/fcntl.h> 53#include <sys/device.h> 54#include <sys/systm.h> 55 56#include <dev/pci/pcidevs.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/cs4281reg.h> 59#include <dev/pci/cs428xreg.h> 60 61#include <sys/audioio.h> 62#include <dev/audio_if.h> 63#include <dev/midi_if.h> 64#include <dev/mulaw.h> 65#include <dev/auconv.h> 66 67#include <dev/ic/ac97reg.h> 68#include <dev/ic/ac97var.h> 69 70#include <dev/pci/cs428x.h> 71 72#include <sys/bus.h> 73 74#if defined(ENABLE_SECONDARY_CODEC) 75#define MAX_CHANNELS (4) 76#define MAX_FIFO_SIZE 32 /* 128/4channels */ 77#else 78#define MAX_CHANNELS (2) 79#define MAX_FIFO_SIZE 64 /* 128/2channels */ 80#endif 81 82/* IF functions for audio driver */ 83static int cs4281_match(device_t, cfdata_t, void *); 84static void cs4281_attach(device_t, device_t, void *); 85static int cs4281_intr(void *); 86static int cs4281_query_encoding(void *, struct audio_encoding *); 87static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90static int cs4281_halt_output(void *); 91static int cs4281_halt_input(void *); 92static int cs4281_getdev(void *, struct audio_device *); 93static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100static int cs4281_reset_codec(void *); 101 102/* Internal functions */ 103static uint8_t cs4281_sr2regval(int); 104static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106static int cs4281_init(struct cs428x_softc *, int); 107 108/* Power Management */ 109static bool cs4281_suspend(device_t, const pmf_qual_t *); 110static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112static const struct audio_hw_if cs4281_hw_if = { 113 .query_encoding = cs4281_query_encoding, 114 .set_params = cs4281_set_params, 115 .round_blocksize = cs428x_round_blocksize, 116 .halt_output = cs4281_halt_output, 117 .halt_input = cs4281_halt_input, 118 .getdev = cs4281_getdev, 119 .set_port = cs428x_mixer_set_port, 120 .get_port = cs428x_mixer_get_port, 121 .query_devinfo = cs428x_query_devinfo, 122 .allocm = cs428x_malloc, 123 .freem = cs428x_free, 124 .round_buffersize = cs428x_round_buffersize, 125 .mappage = cs428x_mappage, 126 .get_props = cs428x_get_props, 127 .trigger_output = cs4281_trigger_output, 128 .trigger_input = cs4281_trigger_input, 129 .get_locks = cs428x_get_locks, 130}; 131 132#if NMIDI > 0 && 0 133/* Midi Interface */ 134static void cs4281_midi_close(void*); 135static void cs4281_midi_getinfo(void *, struct midi_info *); 136static int cs4281_midi_open(void *, int, void (*)(void *, int), 137 void (*)(void *), void *); 138static int cs4281_midi_output(void *, int); 139 140static const struct midi_hw_if cs4281_midi_hw_if = { 141 cs4281_midi_open, 142 cs4281_midi_close, 143 cs4281_midi_output, 144 cs4281_midi_getinfo, 145 0, 146 cs428x_get_locks, 147}; 148#endif 149 150CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc), 151 cs4281_match, cs4281_attach, NULL, NULL); 152 153static struct audio_device cs4281_device = { 154 "CS4281", 155 "", 156 "cs4281" 157}; 158 159 160static int 161cs4281_match(device_t parent, cfdata_t match, void *aux) 162{ 163 struct pci_attach_args *pa; 164 165 pa = (struct pci_attach_args *)aux; 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 167 return 0; 168 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 169 return 1; 170 return 0; 171} 172 173static void 174cs4281_attach(device_t parent, device_t self, void *aux) 175{ 176 struct cs428x_softc *sc; 177 struct pci_attach_args *pa; 178 pci_chipset_tag_t pc; 179 char const *intrstr; 180 pcireg_t reg; 181 int error; 182 char intrbuf[PCI_INTRSTR_LEN]; 183 184 sc = device_private(self); 185 sc->sc_dev = self; 186 pa = (struct pci_attach_args *)aux; 187 pc = pa->pa_pc; 188 189 pci_aprint_devinfo(pa, "Audio controller"); 190 191 sc->sc_pc = pa->pa_pc; 192 sc->sc_pt = pa->pa_tag; 193 194 /* Map I/O register */ 195 if (pci_mapreg_map(pa, PCI_BA0, 196 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 197 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 198 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 199 return; 200 } 201 if (pci_mapreg_map(pa, PCI_BA1, 202 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 203 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 204 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 205 return; 206 } 207 208 sc->sc_dmatag = pa->pa_dmat; 209 210 /* power up chip */ 211 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 212 pci_activate_null)) && error != EOPNOTSUPP) { 213 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 214 return; 215 } 216 217 /* Enable the device (set bus master flag) */ 218 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 220 reg | PCI_COMMAND_MASTER_ENABLE); 221 222#if 0 223 /* LATENCY_TIMER setting */ 224 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 225 if (PCI_LATTIMER(temp1) < 32) { 226 temp1 &= 0xffff00ff; 227 temp1 |= 0x00002000; 228 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 229 } 230#endif 231 232 /* Map and establish the interrupt. */ 233 if (pci_intr_map(pa, &sc->intrh)) { 234 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 235 return; 236 } 237 intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf)); 238 239 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 240 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 241 242 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->intrh, IPL_AUDIO, 243 cs4281_intr, sc, device_xname(self)); 244 if (sc->sc_ih == NULL) { 245 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 246 if (intrstr != NULL) 247 aprint_error(" at %s", intrstr); 248 aprint_error("\n"); 249 mutex_destroy(&sc->sc_lock); 250 mutex_destroy(&sc->sc_intr_lock); 251 return; 252 } 253 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 254 255 /* 256 * Sound System start-up 257 */ 258 if (cs4281_init(sc, 1) != 0) { 259 mutex_destroy(&sc->sc_lock); 260 mutex_destroy(&sc->sc_intr_lock); 261 return; 262 } 263 264 sc->type = TYPE_CS4281; 265 sc->halt_input = cs4281_halt_input; 266 sc->halt_output = cs4281_halt_output; 267 268 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 269 sc->dma_align = 0x10; 270 sc->hw_blocksize = sc->dma_size / 2; 271 272 /* AC 97 attachment */ 273 sc->host_if.arg = sc; 274 sc->host_if.attach = cs428x_attach_codec; 275 sc->host_if.read = cs428x_read_codec; 276 sc->host_if.write = cs428x_write_codec; 277 sc->host_if.reset = cs4281_reset_codec; 278 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 279 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 280 mutex_destroy(&sc->sc_lock); 281 mutex_destroy(&sc->sc_intr_lock); 282 return; 283 } 284 audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev); 285 286#if NMIDI > 0 && 0 287 midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev); 288#endif 289 290 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 291 aprint_error_dev(self, "couldn't establish power handler\n"); 292} 293 294static int 295cs4281_intr(void *p) 296{ 297 struct cs428x_softc *sc; 298 uint32_t intr, hdsr0, hdsr1; 299 char *empty_dma; 300 int handled; 301 302 sc = p; 303 handled = 0; 304 hdsr0 = 0; 305 hdsr1 = 0; 306 307 mutex_spin_enter(&sc->sc_intr_lock); 308 309 /* grab interrupt register */ 310 intr = BA0READ4(sc, CS4281_HISR); 311 312 DPRINTF(("cs4281_intr:")); 313 /* not for me */ 314 if ((intr & HISR_INTENA) == 0) { 315 /* clear the interrupt register */ 316 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 317 mutex_spin_exit(&sc->sc_intr_lock); 318 return 0; 319 } 320 321 if (intr & HISR_DMA0) 322 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 323 if (intr & HISR_DMA1) 324 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 328#ifdef CS4280_DEBUG 329 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 330 intr, hdsr0, hdsr1)); 331#else 332 __USE(hdsr0); 333 __USE(hdsr1); 334#endif 335 336 /* Playback Interrupt */ 337 if (intr & HISR_DMA0) { 338 handled = 1; 339 if (sc->sc_prun) { 340 DPRINTF((" PB DMA 0x%x(%d)", 341 (int)BA0READ4(sc, CS4281_DCA0), 342 (int)BA0READ4(sc, CS4281_DCC0))); 343 if ((sc->sc_pi%sc->sc_pcount) == 0) 344 sc->sc_pintr(sc->sc_parg); 345 /* copy buffer */ 346 ++sc->sc_pi; 347 empty_dma = sc->sc_pdma->addr; 348 if (sc->sc_pi&1) 349 empty_dma += sc->hw_blocksize; 350 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 351 sc->sc_pn += sc->hw_blocksize; 352 if (sc->sc_pn >= sc->sc_pe) 353 sc->sc_pn = sc->sc_ps; 354 } else { 355 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 356 } 357 } 358 if (intr & HISR_DMA1) { 359 handled = 1; 360 if (sc->sc_rrun) { 361 /* copy from DMA */ 362 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 363 (int)BA0READ4(sc, CS4281_DCC1))); 364 ++sc->sc_ri; 365 empty_dma = sc->sc_rdma->addr; 366 if ((sc->sc_ri & 1) == 0) 367 empty_dma += sc->hw_blocksize; 368 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 369 sc->sc_rn += sc->hw_blocksize; 370 if (sc->sc_rn >= sc->sc_re) 371 sc->sc_rn = sc->sc_rs; 372 if ((sc->sc_ri % sc->sc_rcount) == 0) 373 sc->sc_rintr(sc->sc_rarg); 374 } else { 375 aprint_error_dev(sc->sc_dev, 376 "unexpected record intr\n"); 377 } 378 } 379 DPRINTF(("\n")); 380 381 mutex_spin_exit(&sc->sc_intr_lock); 382 383 return handled; 384} 385 386static int 387cs4281_query_encoding(void *addr, struct audio_encoding *fp) 388{ 389 390 switch (fp->index) { 391 case 0: 392 strcpy(fp->name, AudioEulinear); 393 fp->encoding = AUDIO_ENCODING_ULINEAR; 394 fp->precision = 8; 395 fp->flags = 0; 396 break; 397 case 1: 398 strcpy(fp->name, AudioEmulaw); 399 fp->encoding = AUDIO_ENCODING_ULAW; 400 fp->precision = 8; 401 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 402 break; 403 case 2: 404 strcpy(fp->name, AudioEalaw); 405 fp->encoding = AUDIO_ENCODING_ALAW; 406 fp->precision = 8; 407 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 408 break; 409 case 3: 410 strcpy(fp->name, AudioEslinear); 411 fp->encoding = AUDIO_ENCODING_SLINEAR; 412 fp->precision = 8; 413 fp->flags = 0; 414 break; 415 case 4: 416 strcpy(fp->name, AudioEslinear_le); 417 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 418 fp->precision = 16; 419 fp->flags = 0; 420 break; 421 case 5: 422 strcpy(fp->name, AudioEulinear_le); 423 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 424 fp->precision = 16; 425 fp->flags = 0; 426 break; 427 case 6: 428 strcpy(fp->name, AudioEslinear_be); 429 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 430 fp->precision = 16; 431 fp->flags = 0; 432 break; 433 case 7: 434 strcpy(fp->name, AudioEulinear_be); 435 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 436 fp->precision = 16; 437 fp->flags = 0; 438 break; 439 default: 440 return EINVAL; 441 } 442 return 0; 443} 444 445static int 446cs4281_set_params(void *addr, int setmode, int usemode, 447 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 448 stream_filter_list_t *rfil) 449{ 450 audio_params_t hw; 451 struct cs428x_softc *sc; 452 audio_params_t *p; 453 stream_filter_list_t *fil; 454 int mode; 455 456 sc = addr; 457 for (mode = AUMODE_RECORD; mode != -1; 458 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 459 if ((setmode & mode) == 0) 460 continue; 461 462 p = mode == AUMODE_PLAY ? play : rec; 463 464 if (p == play) { 465 DPRINTFN(5, 466 ("play: sample=%u precision=%u channels=%u\n", 467 p->sample_rate, p->precision, p->channels)); 468 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 469 (p->precision != 8 && p->precision != 16) || 470 (p->channels != 1 && p->channels != 2)) { 471 return EINVAL; 472 } 473 } else { 474 DPRINTFN(5, 475 ("rec: sample=%u precision=%u channels=%u\n", 476 p->sample_rate, p->precision, p->channels)); 477 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 478 (p->precision != 8 && p->precision != 16) || 479 (p->channels != 1 && p->channels != 2)) { 480 return EINVAL; 481 } 482 } 483 hw = *p; 484 fil = mode == AUMODE_PLAY ? pfil : rfil; 485 486 switch (p->encoding) { 487 case AUDIO_ENCODING_SLINEAR_BE: 488 break; 489 case AUDIO_ENCODING_SLINEAR_LE: 490 break; 491 case AUDIO_ENCODING_ULINEAR_BE: 492 break; 493 case AUDIO_ENCODING_ULINEAR_LE: 494 break; 495 case AUDIO_ENCODING_ULAW: 496 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 497 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 498 : linear8_to_mulaw, &hw); 499 break; 500 case AUDIO_ENCODING_ALAW: 501 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 502 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 503 : linear8_to_alaw, &hw); 504 break; 505 default: 506 return EINVAL; 507 } 508 } 509 510 /* set sample rate */ 511 cs4281_set_dac_rate(sc, play->sample_rate); 512 cs4281_set_adc_rate(sc, rec->sample_rate); 513 return 0; 514} 515 516static int 517cs4281_halt_output(void *addr) 518{ 519 struct cs428x_softc *sc; 520 521 sc = addr; 522 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 523 sc->sc_prun = 0; 524 return 0; 525} 526 527static int 528cs4281_halt_input(void *addr) 529{ 530 struct cs428x_softc *sc; 531 532 sc = addr; 533 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 534 sc->sc_rrun = 0; 535 return 0; 536} 537 538static int 539cs4281_getdev(void *addr, struct audio_device *retp) 540{ 541 542 *retp = cs4281_device; 543 return 0; 544} 545 546static int 547cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 548 void (*intr)(void *), void *arg, 549 const audio_params_t *param) 550{ 551 struct cs428x_softc *sc; 552 uint32_t fmt; 553 struct cs428x_dma *p; 554 int dma_count; 555 556 sc = addr; 557 fmt = 0; 558#ifdef DIAGNOSTIC 559 if (sc->sc_prun) 560 printf("cs4281_trigger_output: already running\n"); 561#endif 562 sc->sc_prun = 1; 563 564 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 565 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 566 sc->sc_pintr = intr; 567 sc->sc_parg = arg; 568 569 /* stop playback DMA */ 570 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 571 572 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 573 param->precision, param->channels, param->encoding)); 574 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 575 continue; 576 if (p == NULL) { 577 printf("cs4281_trigger_output: bad addr %p\n", start); 578 return EINVAL; 579 } 580 581 sc->sc_pcount = blksize / sc->hw_blocksize; 582 sc->sc_ps = (char *)start; 583 sc->sc_pe = (char *)end; 584 sc->sc_pdma = p; 585 sc->sc_pbuf = KERNADDR(p); 586 sc->sc_pi = 0; 587 sc->sc_pn = sc->sc_ps; 588 if (blksize >= sc->dma_size) { 589 sc->sc_pn = sc->sc_ps + sc->dma_size; 590 memcpy(sc->sc_pbuf, start, sc->dma_size); 591 ++sc->sc_pi; 592 } else { 593 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 594 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 595 } 596 597 dma_count = sc->dma_size; 598 if (param->precision != 8) 599 dma_count /= 2; /* 16 bit */ 600 if (param->channels > 1) 601 dma_count /= 2; /* Stereo */ 602 603 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 604 (int)DMAADDR(p), dma_count)); 605 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 606 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 607 608 /* set playback format */ 609 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 610 if (param->precision == 8) 611 fmt |= DMRn_SIZE8; 612 if (param->channels == 1) 613 fmt |= DMRn_MONO; 614 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 615 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 616 fmt |= DMRn_BEND; 617 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 618 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 619 fmt |= DMRn_USIGN; 620 BA0WRITE4(sc, CS4281_DMR0, fmt); 621 622 /* set sample rate */ 623 sc->sc_prate = param->sample_rate; 624 cs4281_set_dac_rate(sc, param->sample_rate); 625 626 /* start DMA */ 627 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 628 /* Enable interrupts */ 629 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 630 631 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 632 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 633 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 634 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 635 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 636 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 637 BA0READ4(sc, CS4281_DACSR))); 638 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 639 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 640 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 641 642 return 0; 643} 644 645static int 646cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 647 void (*intr)(void *), void *arg, 648 const audio_params_t *param) 649{ 650 struct cs428x_softc *sc; 651 struct cs428x_dma *p; 652 uint32_t fmt; 653 int dma_count; 654 655 sc = addr; 656 fmt = 0; 657#ifdef DIAGNOSTIC 658 if (sc->sc_rrun) 659 printf("cs4281_trigger_input: already running\n"); 660#endif 661 sc->sc_rrun = 1; 662 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 663 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 664 sc->sc_rintr = intr; 665 sc->sc_rarg = arg; 666 667 /* stop recording DMA */ 668 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 669 670 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 671 continue; 672 if (!p) { 673 printf("cs4281_trigger_input: bad addr %p\n", start); 674 return EINVAL; 675 } 676 677 sc->sc_rcount = blksize / sc->hw_blocksize; 678 sc->sc_rs = (char *)start; 679 sc->sc_re = (char *)end; 680 sc->sc_rdma = p; 681 sc->sc_rbuf = KERNADDR(p); 682 sc->sc_ri = 0; 683 sc->sc_rn = sc->sc_rs; 684 685 dma_count = sc->dma_size; 686 if (param->precision != 8) 687 dma_count /= 2; 688 if (param->channels > 1) 689 dma_count /= 2; 690 691 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 692 (int)DMAADDR(p), dma_count)); 693 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 694 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 695 696 /* set recording format */ 697 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 698 if (param->precision == 8) 699 fmt |= DMRn_SIZE8; 700 if (param->channels == 1) 701 fmt |= DMRn_MONO; 702 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 703 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 704 fmt |= DMRn_BEND; 705 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 706 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 707 fmt |= DMRn_USIGN; 708 BA0WRITE4(sc, CS4281_DMR1, fmt); 709 710 /* set sample rate */ 711 sc->sc_rrate = param->sample_rate; 712 cs4281_set_adc_rate(sc, param->sample_rate); 713 714 /* Start DMA */ 715 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 716 /* Enable interrupts */ 717 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 718 719 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 720 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 721 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 722 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 723 724 return 0; 725} 726 727static bool 728cs4281_suspend(device_t dv, const pmf_qual_t *qual) 729{ 730 struct cs428x_softc *sc = device_private(dv); 731 732 mutex_enter(&sc->sc_lock); 733 mutex_spin_exit(&sc->sc_intr_lock); 734 735 /* save current playback status */ 736 if (sc->sc_prun) { 737 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 738 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 739 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 740 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 741 } 742 743 /* save current capture status */ 744 if (sc->sc_rrun) { 745 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 746 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 747 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 748 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 749 } 750 /* Stop DMA */ 751 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 752 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 753 754 mutex_spin_exit(&sc->sc_intr_lock); 755 mutex_exit(&sc->sc_lock); 756 757 return true; 758} 759 760static bool 761cs4281_resume(device_t dv, const pmf_qual_t *qual) 762{ 763 struct cs428x_softc *sc = device_private(dv); 764 765 mutex_enter(&sc->sc_lock); 766 mutex_spin_enter(&sc->sc_intr_lock); 767 768 cs4281_init(sc, 0); 769 cs4281_reset_codec(sc); 770 771 /* restore ac97 registers */ 772 mutex_spin_exit(&sc->sc_intr_lock); 773 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 774 mutex_spin_enter(&sc->sc_intr_lock); 775 776 /* restore DMA related status */ 777 if (sc->sc_prun) { 778 cs4281_set_dac_rate(sc, sc->sc_prate); 779 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 780 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 781 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 782 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 783 } 784 if (sc->sc_rrun) { 785 cs4281_set_adc_rate(sc, sc->sc_rrate); 786 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 787 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 788 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 789 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 790 } 791 /* enable intterupts */ 792 if (sc->sc_prun || sc->sc_rrun) 793 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 794 795 mutex_spin_exit(&sc->sc_intr_lock); 796 mutex_exit(&sc->sc_lock); 797 798 return true; 799} 800 801/* control AC97 codec */ 802static int 803cs4281_reset_codec(void *addr) 804{ 805 struct cs428x_softc *sc; 806 uint16_t data; 807 uint32_t dat32; 808 int n; 809 810 sc = addr; 811 812 DPRINTFN(3, ("cs4281_reset_codec\n")); 813 814 /* Reset codec */ 815 BA0WRITE4(sc, CS428X_ACCTL, 0); 816 delay(50); /* delay 50us */ 817 818 BA0WRITE4(sc, CS4281_SPMC, 0); 819 delay(100); /* delay 100us */ 820 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 821#if defined(ENABLE_SECONDARY_CODEC) 822 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 823 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 824#endif 825 delay(50000); /* XXX: delay 50ms */ 826 827 /* Enable ASYNC generation */ 828 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 829 830 /* Wait for codec ready. Linux driver waits 50ms here */ 831 n = 0; 832 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 833 delay(100); 834 if (++n > 1000) { 835 printf("reset_codec: AC97 codec ready timeout\n"); 836 return ETIMEDOUT; 837 } 838 } 839#if defined(ENABLE_SECONDARY_CODEC) 840 /* secondary codec ready*/ 841 n = 0; 842 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 843 delay(100); 844 if (++n > 1000) 845 return 0; 846 } 847#endif 848 /* Set the serial timing configuration */ 849 /* XXX: undocumented but the Linux driver do this */ 850 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 851 852 /* Wait for codec ready signal */ 853 n = 0; 854 do { 855 delay(1000); 856 if (++n > 1000) { 857 aprint_error_dev(sc->sc_dev, 858 "timeout waiting for codec ready\n"); 859 return ETIMEDOUT; 860 } 861 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 862 } while (dat32 == 0); 863 864 /* Enable Valid Frame output on ASDOUT */ 865 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 866 867 /* Wait until codec calibration is finished. Codec register 26h */ 868 n = 0; 869 do { 870 delay(1); 871 if (++n > 1000) { 872 aprint_error_dev(sc->sc_dev, 873 "timeout waiting for codec calibration\n"); 874 return ETIMEDOUT; 875 } 876 cs428x_read_codec(sc, AC97_REG_POWER, &data); 877 } while ((data & 0x0f) != 0x0f); 878 879 /* Set the serial timing configuration again */ 880 /* XXX: undocumented but the Linux driver do this */ 881 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 882 883 /* Wait until we've sampled input slots 3 & 4 as valid */ 884 n = 0; 885 do { 886 delay(1000); 887 if (++n > 1000) { 888 aprint_error_dev(sc->sc_dev, "timeout waiting for " 889 "sampled input slots as valid\n"); 890 return ETIMEDOUT; 891 } 892 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 893 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 894 895 /* Start digital data transfer of audio data to the codec */ 896 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 897 return 0; 898} 899 900 901/* Internal functions */ 902 903/* convert sample rate to register value */ 904static uint8_t 905cs4281_sr2regval(int rate) 906{ 907 uint8_t retval; 908 909 /* We don't have to change here. but anyway ... */ 910 if (rate > 48000) 911 rate = 48000; 912 if (rate < 6023) 913 rate = 6023; 914 915 switch (rate) { 916 case 8000: 917 retval = 5; 918 break; 919 case 11025: 920 retval = 4; 921 break; 922 case 16000: 923 retval = 3; 924 break; 925 case 22050: 926 retval = 2; 927 break; 928 case 44100: 929 retval = 1; 930 break; 931 case 48000: 932 retval = 0; 933 break; 934 default: 935 retval = 1536000/rate; /* == 24576000/(rate*16) */ 936 } 937 return retval; 938} 939 940static void 941cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 942{ 943 944 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 945} 946 947static void 948cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 949{ 950 951 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 952} 953 954static int 955cs4281_init(struct cs428x_softc *sc, int init) 956{ 957 int n; 958 uint16_t data; 959 uint32_t dat32; 960 961 /* set "Configuration Write Protect" register to 962 * 0x4281 to allow to write */ 963 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 964 965 /* 966 * Unset "Full Power-Down bit of Extended PCI Power Management 967 * Control" register to release the reset state. 968 */ 969 dat32 = BA0READ4(sc, CS4281_EPPMC); 970 if (dat32 & EPPMC_FPDN) { 971 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 972 } 973 974 /* Start PLL out in known state */ 975 BA0WRITE4(sc, CS4281_CLKCR1, 0); 976 /* Start serial ports out in known state */ 977 BA0WRITE4(sc, CS4281_SERMC, 0); 978 979 /* Reset codec */ 980 BA0WRITE4(sc, CS428X_ACCTL, 0); 981 delay(50); /* delay 50us */ 982 983 BA0WRITE4(sc, CS4281_SPMC, 0); 984 delay(100); /* delay 100us */ 985 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 986#if defined(ENABLE_SECONDARY_CODEC) 987 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 988 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 989#endif 990 delay(50000); /* XXX: delay 50ms */ 991 992 /* Turn on Sound System clocks based on ABITCLK */ 993 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 994 delay(50000); /* XXX: delay 50ms */ 995 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 996 997 /* Set enables for sections that are needed in the SSPM registers */ 998 BA0WRITE4(sc, CS4281_SSPM, 999 SSPM_MIXEN | /* Mixer */ 1000 SSPM_CSRCEN | /* Capture SRC */ 1001 SSPM_PSRCEN | /* Playback SRC */ 1002 SSPM_JSEN | /* Joystick */ 1003 SSPM_ACLEN | /* AC LINK */ 1004 SSPM_FMEN /* FM */ 1005 ); 1006 1007 /* Wait for clock stabilization */ 1008 n = 0; 1009#if 1 1010 /* what document says */ 1011 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1012 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1013 delay(100); 1014 if (++n > 1000) { 1015 aprint_error_dev(sc->sc_dev, 1016 "timeout waiting for clock stabilization\n"); 1017 return -1; 1018 } 1019 } 1020#else 1021 /* Cirrus driver for Linux does */ 1022 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1023 delay(1000); 1024 if (++n > 1000) { 1025 aprint_error_dev(sc->sc_dev, 1026 "timeout waiting for clock stabilization\n"); 1027 return -1; 1028 } 1029 } 1030#endif 1031 1032 /* Enable ASYNC generation */ 1033 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1034 1035 /* Wait for codec ready. Linux driver waits 50ms here */ 1036 n = 0; 1037 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1038 delay(100); 1039 if (++n > 1000) { 1040 aprint_error_dev(sc->sc_dev, 1041 "timeout waiting for codec ready\n"); 1042 return -1; 1043 } 1044 } 1045 1046#if defined(ENABLE_SECONDARY_CODEC) 1047 /* secondary codec ready*/ 1048 n = 0; 1049 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1050 delay(100); 1051 if (++n > 1000) { 1052 aprint_error_dev(sc->sc_dev, 1053 "timeout waiting for secondary codec ready\n"); 1054 return -1; 1055 } 1056 } 1057#endif 1058 1059 /* Set the serial timing configuration */ 1060 /* XXX: undocumented but the Linux driver do this */ 1061 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1062 1063 /* Wait for codec ready signal */ 1064 n = 0; 1065 do { 1066 delay(1000); 1067 if (++n > 1000) { 1068 aprint_error_dev(sc->sc_dev, 1069 "timeout waiting for codec ready\n"); 1070 return -1; 1071 } 1072 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1073 } while (dat32 == 0); 1074 1075 /* Enable Valid Frame output on ASDOUT */ 1076 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1077 1078 /* Wait until codec calibration is finished. codec register 26h */ 1079 n = 0; 1080 do { 1081 delay(1); 1082 if (++n > 1000) { 1083 aprint_error_dev(sc->sc_dev, 1084 "timeout waiting for codec calibration\n"); 1085 return -1; 1086 } 1087 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1088 } while ((data & 0x0f) != 0x0f); 1089 1090 /* Set the serial timing configuration again */ 1091 /* XXX: undocumented but the Linux driver do this */ 1092 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1093 1094 /* Wait until we've sampled input slots 3 & 4 as valid */ 1095 n = 0; 1096 do { 1097 delay(1000); 1098 if (++n > 1000) { 1099 aprint_error_dev(sc->sc_dev, "timeout waiting for " 1100 "sampled input slots as valid\n"); 1101 return -1; 1102 } 1103 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1104 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1105 1106 /* Start digital data transfer of audio data to the codec */ 1107 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1108 1109 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1110 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1111 1112 /* Power on the DAC */ 1113 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1114 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1115 1116 /* Wait until we sample a DAC ready state. 1117 * Not documented, but Linux driver does. 1118 */ 1119 for (n = 0; n < 32; ++n) { 1120 delay(1000); 1121 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1122 if (data & 0x02) 1123 break; 1124 } 1125 1126 /* Power on the ADC */ 1127 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1128 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1129 1130 /* Wait until we sample ADC ready state. 1131 * Not documented, but Linux driver does. 1132 */ 1133 for (n = 0; n < 32; ++n) { 1134 delay(1000); 1135 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1136 if (data & 0x01) 1137 break; 1138 } 1139 1140#if 0 1141 /* Initialize AC-Link features */ 1142 /* variable sample-rate support */ 1143 mem = BA0READ4(sc, CS4281_SERMC); 1144 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1145 BA0WRITE4(sc, CS4281_SERMC, mem); 1146 /* XXX: more... */ 1147 1148 /* Initialize SSCR register features */ 1149 /* XXX: hardware volume setting */ 1150 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1151#endif 1152 1153 /* disable Sound Blaster Pro emulation */ 1154 /* XXX: 1155 * Cannot set since the documents does not describe which bit is 1156 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1157 * we can ignore it.*/ 1158#if 0 1159 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1160#endif 1161 1162 /* map AC97 PCM playback to DMA Channel 0 */ 1163 /* Reset FEN bit to setup first */ 1164 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1165 /* 1166 *| RS[4:0]/| | 1167 *| LS[4:0] | AC97 | Slot Function 1168 *|---------+--------+-------------------- 1169 *| 0 | 3 | Left PCM Playback 1170 *| 1 | 4 | Right PCM Playback 1171 *| 2 | 5 | Phone Line 1 DAC 1172 *| 3 | 6 | Center PCM Playback 1173 *.... 1174 * quoted from Table 29(p109) 1175 */ 1176 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1177 0x00 << 16 | /* LS[4:0] = 0 see above */ 1178 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1179 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1180 BA0WRITE4(sc, CS4281_FCR0, dat32); 1181 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1182 1183 /* map AC97 PCM record to DMA Channel 1 */ 1184 /* Reset FEN bit to setup first */ 1185 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1186 /* 1187 *| RS[4:0]/| 1188 *| LS[4:0] | AC97 | Slot Function 1189 *|---------+------+------------------- 1190 *| 10 | 3 | Left PCM Record 1191 *| 11 | 4 | Right PCM Record 1192 *| 12 | 5 | Phone Line 1 ADC 1193 *| 13 | 6 | Mic ADC 1194 *.... 1195 * quoted from Table 30(p109) 1196 */ 1197 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1198 0x0a << 16 | /* LS[4:0] = 10 See above */ 1199 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1200 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1201 1202 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1203 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1204 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1205 1206#if 0 1207 /* Disable DMA Channel 2, 3 */ 1208 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1209 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1210#endif 1211 1212 /* Set the SRC Slot Assignment accordingly */ 1213 /*| PLSS[4:0]/ 1214 *| PRSS[4:0] | AC97 | Slot Function 1215 *|-----------+------+---------------- 1216 *| 0 | 3 | Left PCM Playback 1217 *| 1 | 4 | Right PCM Playback 1218 *| 2 | 5 | phone line 1 DAC 1219 *| 3 | 6 | Center PCM Playback 1220 *| 4 | 7 | Left Surround PCM Playback 1221 *| 5 | 8 | Right Surround PCM Playback 1222 *...... 1223 * 1224 *| CLSS[4:0]/ 1225 *| CRSS[4:0] | AC97 | Codec |Slot Function 1226 *|-----------+------+-------+----------------- 1227 *| 10 | 3 |Primary| Left PCM Record 1228 *| 11 | 4 |Primary| Right PCM Record 1229 *| 12 | 5 |Primary| Phone Line 1 ADC 1230 *| 13 | 6 |Primary| Mic ADC 1231 *|..... 1232 *| 20 | 3 | Sec. | Left PCM Record 1233 *| 21 | 4 | Sec. | Right PCM Record 1234 *| 22 | 5 | Sec. | Phone Line 1 ADC 1235 *| 23 | 6 | Sec. | Mic ADC 1236 */ 1237 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1238 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1239 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1240 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1241 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1242 1243 /* Set interrupt to occurred at Half and Full terminal 1244 * count interrupt enable for DMA channel 0 and 1. 1245 * To keep DMA stop, set MSK. 1246 */ 1247 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1248 BA0WRITE4(sc, CS4281_DCR0, dat32); 1249 BA0WRITE4(sc, CS4281_DCR1, dat32); 1250 1251 /* Set Auto-Initialize Contorl enable */ 1252 BA0WRITE4(sc, CS4281_DMR0, 1253 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1254 BA0WRITE4(sc, CS4281_DMR1, 1255 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1256 1257 /* Clear DMA Mask in HIMR */ 1258 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1259 BA0WRITE4(sc, CS4281_HIMR, 1260 BA0READ4(sc, CS4281_HIMR) & dat32); 1261 1262 /* set current status */ 1263 if (init != 0) { 1264 sc->sc_prun = 0; 1265 sc->sc_rrun = 0; 1266 } 1267 1268 /* setup playback volume */ 1269 BA0WRITE4(sc, CS4281_PPRVC, 7); 1270 BA0WRITE4(sc, CS4281_PPLVC, 7); 1271 1272 return 0; 1273} 1274