cs4281.c revision 1.48
1/* $NetBSD: cs4281.c,v 1.48 2012/10/27 17:18:31 chs Exp $ */ 2 3/* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45#include <sys/cdefs.h> 46__KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.48 2012/10/27 17:18:31 chs Exp $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/kernel.h> 51#include <sys/malloc.h> 52#include <sys/fcntl.h> 53#include <sys/device.h> 54#include <sys/systm.h> 55 56#include <dev/pci/pcidevs.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/cs4281reg.h> 59#include <dev/pci/cs428xreg.h> 60 61#include <sys/audioio.h> 62#include <dev/audio_if.h> 63#include <dev/midi_if.h> 64#include <dev/mulaw.h> 65#include <dev/auconv.h> 66 67#include <dev/ic/ac97reg.h> 68#include <dev/ic/ac97var.h> 69 70#include <dev/pci/cs428x.h> 71 72#include <sys/bus.h> 73 74#if defined(ENABLE_SECONDARY_CODEC) 75#define MAX_CHANNELS (4) 76#define MAX_FIFO_SIZE 32 /* 128/4channels */ 77#else 78#define MAX_CHANNELS (2) 79#define MAX_FIFO_SIZE 64 /* 128/2channels */ 80#endif 81 82/* IF functions for audio driver */ 83static int cs4281_match(device_t, cfdata_t, void *); 84static void cs4281_attach(device_t, device_t, void *); 85static int cs4281_intr(void *); 86static int cs4281_query_encoding(void *, struct audio_encoding *); 87static int cs4281_set_params(void *, int, int, audio_params_t *, 88 audio_params_t *, stream_filter_list_t *, 89 stream_filter_list_t *); 90static int cs4281_halt_output(void *); 91static int cs4281_halt_input(void *); 92static int cs4281_getdev(void *, struct audio_device *); 93static int cs4281_trigger_output(void *, void *, void *, int, 94 void (*)(void *), void *, 95 const audio_params_t *); 96static int cs4281_trigger_input(void *, void *, void *, int, 97 void (*)(void *), void *, 98 const audio_params_t *); 99 100static int cs4281_reset_codec(void *); 101 102/* Internal functions */ 103static uint8_t cs4281_sr2regval(int); 104static void cs4281_set_dac_rate(struct cs428x_softc *, int); 105static void cs4281_set_adc_rate(struct cs428x_softc *, int); 106static int cs4281_init(struct cs428x_softc *, int); 107 108/* Power Management */ 109static bool cs4281_suspend(device_t, const pmf_qual_t *); 110static bool cs4281_resume(device_t, const pmf_qual_t *); 111 112static const struct audio_hw_if cs4281_hw_if = { 113 NULL, /* open */ 114 NULL, /* close */ 115 NULL, 116 cs4281_query_encoding, 117 cs4281_set_params, 118 cs428x_round_blocksize, 119 NULL, 120 NULL, 121 NULL, 122 NULL, 123 NULL, 124 cs4281_halt_output, 125 cs4281_halt_input, 126 NULL, 127 cs4281_getdev, 128 NULL, 129 cs428x_mixer_set_port, 130 cs428x_mixer_get_port, 131 cs428x_query_devinfo, 132 cs428x_malloc, 133 cs428x_free, 134 cs428x_round_buffersize, 135 cs428x_mappage, 136 cs428x_get_props, 137 cs4281_trigger_output, 138 cs4281_trigger_input, 139 NULL, 140 cs428x_get_locks, 141}; 142 143#if NMIDI > 0 && 0 144/* Midi Interface */ 145static void cs4281_midi_close(void*); 146static void cs4281_midi_getinfo(void *, struct midi_info *); 147static int cs4281_midi_open(void *, int, void (*)(void *, int), 148 void (*)(void *), void *); 149static int cs4281_midi_output(void *, int); 150 151static const struct midi_hw_if cs4281_midi_hw_if = { 152 cs4281_midi_open, 153 cs4281_midi_close, 154 cs4281_midi_output, 155 cs4281_midi_getinfo, 156 0, 157 cs428x_get_locks, 158}; 159#endif 160 161CFATTACH_DECL_NEW(clct, sizeof(struct cs428x_softc), 162 cs4281_match, cs4281_attach, NULL, NULL); 163 164static struct audio_device cs4281_device = { 165 "CS4281", 166 "", 167 "cs4281" 168}; 169 170 171static int 172cs4281_match(device_t parent, cfdata_t match, void *aux) 173{ 174 struct pci_attach_args *pa; 175 176 pa = (struct pci_attach_args *)aux; 177 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 178 return 0; 179 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 180 return 1; 181 return 0; 182} 183 184static void 185cs4281_attach(device_t parent, device_t self, void *aux) 186{ 187 struct cs428x_softc *sc; 188 struct pci_attach_args *pa; 189 pci_chipset_tag_t pc; 190 char const *intrstr; 191 pcireg_t reg; 192 int error; 193 194 sc = device_private(self); 195 sc->sc_dev = self; 196 pa = (struct pci_attach_args *)aux; 197 pc = pa->pa_pc; 198 199 pci_aprint_devinfo(pa, "Audio controller"); 200 201 sc->sc_pc = pa->pa_pc; 202 sc->sc_pt = pa->pa_tag; 203 204 /* Map I/O register */ 205 if (pci_mapreg_map(pa, PCI_BA0, 206 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 207 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 208 aprint_error_dev(sc->sc_dev, "can't map BA0 space\n"); 209 return; 210 } 211 if (pci_mapreg_map(pa, PCI_BA1, 212 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 213 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 214 aprint_error_dev(sc->sc_dev, "can't map BA1 space\n"); 215 return; 216 } 217 218 sc->sc_dmatag = pa->pa_dmat; 219 220 /* power up chip */ 221 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 222 pci_activate_null)) && error != EOPNOTSUPP) { 223 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 224 return; 225 } 226 227 /* Enable the device (set bus master flag) */ 228 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 230 reg | PCI_COMMAND_MASTER_ENABLE); 231 232#if 0 233 /* LATENCY_TIMER setting */ 234 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 235 if (PCI_LATTIMER(temp1) < 32) { 236 temp1 &= 0xffff00ff; 237 temp1 |= 0x00002000; 238 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 239 } 240#endif 241 242 /* Map and establish the interrupt. */ 243 if (pci_intr_map(pa, &sc->intrh)) { 244 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 245 return; 246 } 247 intrstr = pci_intr_string(pc, sc->intrh); 248 249 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 250 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 251 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO, 253 cs4281_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 mutex_destroy(&sc->sc_lock); 260 mutex_destroy(&sc->sc_intr_lock); 261 return; 262 } 263 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 264 265 /* 266 * Sound System start-up 267 */ 268 if (cs4281_init(sc, 1) != 0) { 269 mutex_destroy(&sc->sc_lock); 270 mutex_destroy(&sc->sc_intr_lock); 271 return; 272 } 273 274 sc->type = TYPE_CS4281; 275 sc->halt_input = cs4281_halt_input; 276 sc->halt_output = cs4281_halt_output; 277 278 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 279 sc->dma_align = 0x10; 280 sc->hw_blocksize = sc->dma_size / 2; 281 282 /* AC 97 attachment */ 283 sc->host_if.arg = sc; 284 sc->host_if.attach = cs428x_attach_codec; 285 sc->host_if.read = cs428x_read_codec; 286 sc->host_if.write = cs428x_write_codec; 287 sc->host_if.reset = cs4281_reset_codec; 288 if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) { 289 aprint_error_dev(sc->sc_dev, "ac97_attach failed\n"); 290 mutex_destroy(&sc->sc_lock); 291 mutex_destroy(&sc->sc_intr_lock); 292 return; 293 } 294 audio_attach_mi(&cs4281_hw_if, sc, sc->sc_dev); 295 296#if NMIDI > 0 && 0 297 midi_attach_mi(&cs4281_midi_hw_if, sc, sc->sc_dev); 298#endif 299 300 if (!pmf_device_register(self, cs4281_suspend, cs4281_resume)) 301 aprint_error_dev(self, "couldn't establish power handler\n"); 302} 303 304static int 305cs4281_intr(void *p) 306{ 307 struct cs428x_softc *sc; 308 uint32_t intr, hdsr0, hdsr1; 309 char *empty_dma; 310 int handled; 311 312 sc = p; 313 handled = 0; 314 hdsr0 = 0; 315 hdsr1 = 0; 316 317 mutex_spin_enter(&sc->sc_intr_lock); 318 319 /* grab interrupt register */ 320 intr = BA0READ4(sc, CS4281_HISR); 321 322 DPRINTF(("cs4281_intr:")); 323 /* not for me */ 324 if ((intr & HISR_INTENA) == 0) { 325 /* clear the interrupt register */ 326 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 327 mutex_spin_exit(&sc->sc_intr_lock); 328 return 0; 329 } 330 331 if (intr & HISR_DMA0) 332 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 333 if (intr & HISR_DMA1) 334 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 335 /* clear the interrupt register */ 336 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 337 338 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 339 intr, hdsr0, hdsr1)); 340 341 /* Playback Interrupt */ 342 if (intr & HISR_DMA0) { 343 handled = 1; 344 if (sc->sc_prun) { 345 DPRINTF((" PB DMA 0x%x(%d)", 346 (int)BA0READ4(sc, CS4281_DCA0), 347 (int)BA0READ4(sc, CS4281_DCC0))); 348 if ((sc->sc_pi%sc->sc_pcount) == 0) 349 sc->sc_pintr(sc->sc_parg); 350 /* copy buffer */ 351 ++sc->sc_pi; 352 empty_dma = sc->sc_pdma->addr; 353 if (sc->sc_pi&1) 354 empty_dma += sc->hw_blocksize; 355 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 356 sc->sc_pn += sc->hw_blocksize; 357 if (sc->sc_pn >= sc->sc_pe) 358 sc->sc_pn = sc->sc_ps; 359 } else { 360 aprint_error_dev(sc->sc_dev, "unexpected play intr\n"); 361 } 362 } 363 if (intr & HISR_DMA1) { 364 handled = 1; 365 if (sc->sc_rrun) { 366 /* copy from DMA */ 367 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 368 (int)BA0READ4(sc, CS4281_DCC1))); 369 ++sc->sc_ri; 370 empty_dma = sc->sc_rdma->addr; 371 if ((sc->sc_ri & 1) == 0) 372 empty_dma += sc->hw_blocksize; 373 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 374 sc->sc_rn += sc->hw_blocksize; 375 if (sc->sc_rn >= sc->sc_re) 376 sc->sc_rn = sc->sc_rs; 377 if ((sc->sc_ri % sc->sc_rcount) == 0) 378 sc->sc_rintr(sc->sc_rarg); 379 } else { 380 aprint_error_dev(sc->sc_dev, 381 "unexpected record intr\n"); 382 } 383 } 384 DPRINTF(("\n")); 385 386 mutex_spin_exit(&sc->sc_intr_lock); 387 388 return handled; 389} 390 391static int 392cs4281_query_encoding(void *addr, struct audio_encoding *fp) 393{ 394 395 switch (fp->index) { 396 case 0: 397 strcpy(fp->name, AudioEulinear); 398 fp->encoding = AUDIO_ENCODING_ULINEAR; 399 fp->precision = 8; 400 fp->flags = 0; 401 break; 402 case 1: 403 strcpy(fp->name, AudioEmulaw); 404 fp->encoding = AUDIO_ENCODING_ULAW; 405 fp->precision = 8; 406 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 407 break; 408 case 2: 409 strcpy(fp->name, AudioEalaw); 410 fp->encoding = AUDIO_ENCODING_ALAW; 411 fp->precision = 8; 412 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 413 break; 414 case 3: 415 strcpy(fp->name, AudioEslinear); 416 fp->encoding = AUDIO_ENCODING_SLINEAR; 417 fp->precision = 8; 418 fp->flags = 0; 419 break; 420 case 4: 421 strcpy(fp->name, AudioEslinear_le); 422 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 423 fp->precision = 16; 424 fp->flags = 0; 425 break; 426 case 5: 427 strcpy(fp->name, AudioEulinear_le); 428 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 429 fp->precision = 16; 430 fp->flags = 0; 431 break; 432 case 6: 433 strcpy(fp->name, AudioEslinear_be); 434 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 435 fp->precision = 16; 436 fp->flags = 0; 437 break; 438 case 7: 439 strcpy(fp->name, AudioEulinear_be); 440 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 441 fp->precision = 16; 442 fp->flags = 0; 443 break; 444 default: 445 return EINVAL; 446 } 447 return 0; 448} 449 450static int 451cs4281_set_params(void *addr, int setmode, int usemode, 452 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, 453 stream_filter_list_t *rfil) 454{ 455 audio_params_t hw; 456 struct cs428x_softc *sc; 457 audio_params_t *p; 458 stream_filter_list_t *fil; 459 int mode; 460 461 sc = addr; 462 for (mode = AUMODE_RECORD; mode != -1; 463 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 464 if ((setmode & mode) == 0) 465 continue; 466 467 p = mode == AUMODE_PLAY ? play : rec; 468 469 if (p == play) { 470 DPRINTFN(5, 471 ("play: sample=%u precision=%u channels=%u\n", 472 p->sample_rate, p->precision, p->channels)); 473 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 474 (p->precision != 8 && p->precision != 16) || 475 (p->channels != 1 && p->channels != 2)) { 476 return EINVAL; 477 } 478 } else { 479 DPRINTFN(5, 480 ("rec: sample=%u precision=%u channels=%u\n", 481 p->sample_rate, p->precision, p->channels)); 482 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 483 (p->precision != 8 && p->precision != 16) || 484 (p->channels != 1 && p->channels != 2)) { 485 return EINVAL; 486 } 487 } 488 hw = *p; 489 fil = mode == AUMODE_PLAY ? pfil : rfil; 490 491 switch (p->encoding) { 492 case AUDIO_ENCODING_SLINEAR_BE: 493 break; 494 case AUDIO_ENCODING_SLINEAR_LE: 495 break; 496 case AUDIO_ENCODING_ULINEAR_BE: 497 break; 498 case AUDIO_ENCODING_ULINEAR_LE: 499 break; 500 case AUDIO_ENCODING_ULAW: 501 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 502 fil->append(fil, mode == AUMODE_PLAY ? mulaw_to_linear8 503 : linear8_to_mulaw, &hw); 504 break; 505 case AUDIO_ENCODING_ALAW: 506 hw.encoding = AUDIO_ENCODING_SLINEAR_LE; 507 fil->append(fil, mode == AUMODE_PLAY ? alaw_to_linear8 508 : linear8_to_alaw, &hw); 509 break; 510 default: 511 return EINVAL; 512 } 513 } 514 515 /* set sample rate */ 516 cs4281_set_dac_rate(sc, play->sample_rate); 517 cs4281_set_adc_rate(sc, rec->sample_rate); 518 return 0; 519} 520 521static int 522cs4281_halt_output(void *addr) 523{ 524 struct cs428x_softc *sc; 525 526 sc = addr; 527 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 528 sc->sc_prun = 0; 529 return 0; 530} 531 532static int 533cs4281_halt_input(void *addr) 534{ 535 struct cs428x_softc *sc; 536 537 sc = addr; 538 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 539 sc->sc_rrun = 0; 540 return 0; 541} 542 543static int 544cs4281_getdev(void *addr, struct audio_device *retp) 545{ 546 547 *retp = cs4281_device; 548 return 0; 549} 550 551static int 552cs4281_trigger_output(void *addr, void *start, void *end, int blksize, 553 void (*intr)(void *), void *arg, 554 const audio_params_t *param) 555{ 556 struct cs428x_softc *sc; 557 uint32_t fmt; 558 struct cs428x_dma *p; 559 int dma_count; 560 561 sc = addr; 562 fmt = 0; 563#ifdef DIAGNOSTIC 564 if (sc->sc_prun) 565 printf("cs4281_trigger_output: already running\n"); 566#endif 567 sc->sc_prun = 1; 568 569 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 570 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 571 sc->sc_pintr = intr; 572 sc->sc_parg = arg; 573 574 /* stop playback DMA */ 575 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 576 577 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 578 param->precision, param->channels, param->encoding)); 579 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 580 continue; 581 if (p == NULL) { 582 printf("cs4281_trigger_output: bad addr %p\n", start); 583 return EINVAL; 584 } 585 586 sc->sc_pcount = blksize / sc->hw_blocksize; 587 sc->sc_ps = (char *)start; 588 sc->sc_pe = (char *)end; 589 sc->sc_pdma = p; 590 sc->sc_pbuf = KERNADDR(p); 591 sc->sc_pi = 0; 592 sc->sc_pn = sc->sc_ps; 593 if (blksize >= sc->dma_size) { 594 sc->sc_pn = sc->sc_ps + sc->dma_size; 595 memcpy(sc->sc_pbuf, start, sc->dma_size); 596 ++sc->sc_pi; 597 } else { 598 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 599 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 600 } 601 602 dma_count = sc->dma_size; 603 if (param->precision != 8) 604 dma_count /= 2; /* 16 bit */ 605 if (param->channels > 1) 606 dma_count /= 2; /* Stereo */ 607 608 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 609 (int)DMAADDR(p), dma_count)); 610 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 611 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 612 613 /* set playback format */ 614 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 615 if (param->precision == 8) 616 fmt |= DMRn_SIZE8; 617 if (param->channels == 1) 618 fmt |= DMRn_MONO; 619 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 620 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 621 fmt |= DMRn_BEND; 622 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 623 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 624 fmt |= DMRn_USIGN; 625 BA0WRITE4(sc, CS4281_DMR0, fmt); 626 627 /* set sample rate */ 628 sc->sc_prate = param->sample_rate; 629 cs4281_set_dac_rate(sc, param->sample_rate); 630 631 /* start DMA */ 632 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 633 /* Enable interrupts */ 634 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 635 636 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 637 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 638 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 639 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 640 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 641 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 642 BA0READ4(sc, CS4281_DACSR))); 643 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 644 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 645 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 646 647 return 0; 648} 649 650static int 651cs4281_trigger_input(void *addr, void *start, void *end, int blksize, 652 void (*intr)(void *), void *arg, 653 const audio_params_t *param) 654{ 655 struct cs428x_softc *sc; 656 struct cs428x_dma *p; 657 uint32_t fmt; 658 int dma_count; 659 660 sc = addr; 661 fmt = 0; 662#ifdef DIAGNOSTIC 663 if (sc->sc_rrun) 664 printf("cs4281_trigger_input: already running\n"); 665#endif 666 sc->sc_rrun = 1; 667 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 668 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 669 sc->sc_rintr = intr; 670 sc->sc_rarg = arg; 671 672 /* stop recording DMA */ 673 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 674 675 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 676 continue; 677 if (!p) { 678 printf("cs4281_trigger_input: bad addr %p\n", start); 679 return EINVAL; 680 } 681 682 sc->sc_rcount = blksize / sc->hw_blocksize; 683 sc->sc_rs = (char *)start; 684 sc->sc_re = (char *)end; 685 sc->sc_rdma = p; 686 sc->sc_rbuf = KERNADDR(p); 687 sc->sc_ri = 0; 688 sc->sc_rn = sc->sc_rs; 689 690 dma_count = sc->dma_size; 691 if (param->precision != 8) 692 dma_count /= 2; 693 if (param->channels > 1) 694 dma_count /= 2; 695 696 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 697 (int)DMAADDR(p), dma_count)); 698 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 699 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 700 701 /* set recording format */ 702 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 703 if (param->precision == 8) 704 fmt |= DMRn_SIZE8; 705 if (param->channels == 1) 706 fmt |= DMRn_MONO; 707 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 708 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 709 fmt |= DMRn_BEND; 710 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 711 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 712 fmt |= DMRn_USIGN; 713 BA0WRITE4(sc, CS4281_DMR1, fmt); 714 715 /* set sample rate */ 716 sc->sc_rrate = param->sample_rate; 717 cs4281_set_adc_rate(sc, param->sample_rate); 718 719 /* Start DMA */ 720 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 721 /* Enable interrupts */ 722 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 723 724 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 725 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 726 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 727 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 728 729 return 0; 730} 731 732static bool 733cs4281_suspend(device_t dv, const pmf_qual_t *qual) 734{ 735 struct cs428x_softc *sc = device_private(dv); 736 737 mutex_enter(&sc->sc_lock); 738 mutex_spin_exit(&sc->sc_intr_lock); 739 740 /* save current playback status */ 741 if (sc->sc_prun) { 742 sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0); 743 sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0); 744 sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0); 745 sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0); 746 } 747 748 /* save current capture status */ 749 if (sc->sc_rrun) { 750 sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1); 751 sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1); 752 sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1); 753 sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1); 754 } 755 /* Stop DMA */ 756 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 757 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 758 759 mutex_spin_exit(&sc->sc_intr_lock); 760 mutex_exit(&sc->sc_lock); 761 762 return true; 763} 764 765static bool 766cs4281_resume(device_t dv, const pmf_qual_t *qual) 767{ 768 struct cs428x_softc *sc = device_private(dv); 769 770 mutex_enter(&sc->sc_lock); 771 mutex_spin_enter(&sc->sc_intr_lock); 772 773 cs4281_init(sc, 0); 774 cs4281_reset_codec(sc); 775 776 /* restore ac97 registers */ 777 mutex_spin_exit(&sc->sc_intr_lock); 778 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 779 mutex_spin_enter(&sc->sc_intr_lock); 780 781 /* restore DMA related status */ 782 if (sc->sc_prun) { 783 cs4281_set_dac_rate(sc, sc->sc_prate); 784 BA0WRITE4(sc, CS4281_DBA0, sc->sc_suspend_state.cs4281.dba0); 785 BA0WRITE4(sc, CS4281_DBC0, sc->sc_suspend_state.cs4281.dbc0); 786 BA0WRITE4(sc, CS4281_DMR0, sc->sc_suspend_state.cs4281.dmr0); 787 BA0WRITE4(sc, CS4281_DCR0, sc->sc_suspend_state.cs4281.dcr0); 788 } 789 if (sc->sc_rrun) { 790 cs4281_set_adc_rate(sc, sc->sc_rrate); 791 BA0WRITE4(sc, CS4281_DBA1, sc->sc_suspend_state.cs4281.dba1); 792 BA0WRITE4(sc, CS4281_DBC1, sc->sc_suspend_state.cs4281.dbc1); 793 BA0WRITE4(sc, CS4281_DMR1, sc->sc_suspend_state.cs4281.dmr1); 794 BA0WRITE4(sc, CS4281_DCR1, sc->sc_suspend_state.cs4281.dcr1); 795 } 796 /* enable intterupts */ 797 if (sc->sc_prun || sc->sc_rrun) 798 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 799 800 mutex_spin_exit(&sc->sc_intr_lock); 801 mutex_exit(&sc->sc_lock); 802 803 return true; 804} 805 806/* control AC97 codec */ 807static int 808cs4281_reset_codec(void *addr) 809{ 810 struct cs428x_softc *sc; 811 uint16_t data; 812 uint32_t dat32; 813 int n; 814 815 sc = addr; 816 817 DPRINTFN(3, ("cs4281_reset_codec\n")); 818 819 /* Reset codec */ 820 BA0WRITE4(sc, CS428X_ACCTL, 0); 821 delay(50); /* delay 50us */ 822 823 BA0WRITE4(sc, CS4281_SPMC, 0); 824 delay(100); /* delay 100us */ 825 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 826#if defined(ENABLE_SECONDARY_CODEC) 827 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 828 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 829#endif 830 delay(50000); /* XXX: delay 50ms */ 831 832 /* Enable ASYNC generation */ 833 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 834 835 /* Wait for codec ready. Linux driver waits 50ms here */ 836 n = 0; 837 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 838 delay(100); 839 if (++n > 1000) { 840 printf("reset_codec: AC97 codec ready timeout\n"); 841 return ETIMEDOUT; 842 } 843 } 844#if defined(ENABLE_SECONDARY_CODEC) 845 /* secondary codec ready*/ 846 n = 0; 847 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 848 delay(100); 849 if (++n > 1000) 850 return 0; 851 } 852#endif 853 /* Set the serial timing configuration */ 854 /* XXX: undocumented but the Linux driver do this */ 855 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 856 857 /* Wait for codec ready signal */ 858 n = 0; 859 do { 860 delay(1000); 861 if (++n > 1000) { 862 aprint_error_dev(sc->sc_dev, 863 "timeout waiting for codec ready\n"); 864 return ETIMEDOUT; 865 } 866 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 867 } while (dat32 == 0); 868 869 /* Enable Valid Frame output on ASDOUT */ 870 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 871 872 /* Wait until codec calibration is finished. Codec register 26h */ 873 n = 0; 874 do { 875 delay(1); 876 if (++n > 1000) { 877 aprint_error_dev(sc->sc_dev, 878 "timeout waiting for codec calibration\n"); 879 return ETIMEDOUT; 880 } 881 cs428x_read_codec(sc, AC97_REG_POWER, &data); 882 } while ((data & 0x0f) != 0x0f); 883 884 /* Set the serial timing configuration again */ 885 /* XXX: undocumented but the Linux driver do this */ 886 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 887 888 /* Wait until we've sampled input slots 3 & 4 as valid */ 889 n = 0; 890 do { 891 delay(1000); 892 if (++n > 1000) { 893 aprint_error_dev(sc->sc_dev, "timeout waiting for " 894 "sampled input slots as valid\n"); 895 return ETIMEDOUT; 896 } 897 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 898 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 899 900 /* Start digital data transfer of audio data to the codec */ 901 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 902 return 0; 903} 904 905 906/* Internal functions */ 907 908/* convert sample rate to register value */ 909static uint8_t 910cs4281_sr2regval(int rate) 911{ 912 uint8_t retval; 913 914 /* We don't have to change here. but anyway ... */ 915 if (rate > 48000) 916 rate = 48000; 917 if (rate < 6023) 918 rate = 6023; 919 920 switch (rate) { 921 case 8000: 922 retval = 5; 923 break; 924 case 11025: 925 retval = 4; 926 break; 927 case 16000: 928 retval = 3; 929 break; 930 case 22050: 931 retval = 2; 932 break; 933 case 44100: 934 retval = 1; 935 break; 936 case 48000: 937 retval = 0; 938 break; 939 default: 940 retval = 1536000/rate; /* == 24576000/(rate*16) */ 941 } 942 return retval; 943} 944 945static void 946cs4281_set_adc_rate(struct cs428x_softc *sc, int rate) 947{ 948 949 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 950} 951 952static void 953cs4281_set_dac_rate(struct cs428x_softc *sc, int rate) 954{ 955 956 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 957} 958 959static int 960cs4281_init(struct cs428x_softc *sc, int init) 961{ 962 int n; 963 uint16_t data; 964 uint32_t dat32; 965 966 /* set "Configuration Write Protect" register to 967 * 0x4281 to allow to write */ 968 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 969 970 /* 971 * Unset "Full Power-Down bit of Extended PCI Power Management 972 * Control" register to release the reset state. 973 */ 974 dat32 = BA0READ4(sc, CS4281_EPPMC); 975 if (dat32 & EPPMC_FPDN) { 976 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 977 } 978 979 /* Start PLL out in known state */ 980 BA0WRITE4(sc, CS4281_CLKCR1, 0); 981 /* Start serial ports out in known state */ 982 BA0WRITE4(sc, CS4281_SERMC, 0); 983 984 /* Reset codec */ 985 BA0WRITE4(sc, CS428X_ACCTL, 0); 986 delay(50); /* delay 50us */ 987 988 BA0WRITE4(sc, CS4281_SPMC, 0); 989 delay(100); /* delay 100us */ 990 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 991#if defined(ENABLE_SECONDARY_CODEC) 992 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 993 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 994#endif 995 delay(50000); /* XXX: delay 50ms */ 996 997 /* Turn on Sound System clocks based on ABITCLK */ 998 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 999 delay(50000); /* XXX: delay 50ms */ 1000 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1001 1002 /* Set enables for sections that are needed in the SSPM registers */ 1003 BA0WRITE4(sc, CS4281_SSPM, 1004 SSPM_MIXEN | /* Mixer */ 1005 SSPM_CSRCEN | /* Capture SRC */ 1006 SSPM_PSRCEN | /* Playback SRC */ 1007 SSPM_JSEN | /* Joystick */ 1008 SSPM_ACLEN | /* AC LINK */ 1009 SSPM_FMEN /* FM */ 1010 ); 1011 1012 /* Wait for clock stabilization */ 1013 n = 0; 1014#if 1 1015 /* what document says */ 1016 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1017 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1018 delay(100); 1019 if (++n > 1000) { 1020 aprint_error_dev(sc->sc_dev, 1021 "timeout waiting for clock stabilization\n"); 1022 return -1; 1023 } 1024 } 1025#else 1026 /* Cirrus driver for Linux does */ 1027 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1028 delay(1000); 1029 if (++n > 1000) { 1030 aprint_error_dev(sc->sc_dev, 1031 "timeout waiting for clock stabilization\n"); 1032 return -1; 1033 } 1034 } 1035#endif 1036 1037 /* Enable ASYNC generation */ 1038 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1039 1040 /* Wait for codec ready. Linux driver waits 50ms here */ 1041 n = 0; 1042 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1043 delay(100); 1044 if (++n > 1000) { 1045 aprint_error_dev(sc->sc_dev, 1046 "timeout waiting for codec ready\n"); 1047 return -1; 1048 } 1049 } 1050 1051#if defined(ENABLE_SECONDARY_CODEC) 1052 /* secondary codec ready*/ 1053 n = 0; 1054 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1055 delay(100); 1056 if (++n > 1000) { 1057 aprint_error_dev(sc->sc_dev, 1058 "timeout waiting for secondary codec ready\n"); 1059 return -1; 1060 } 1061 } 1062#endif 1063 1064 /* Set the serial timing configuration */ 1065 /* XXX: undocumented but the Linux driver do this */ 1066 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1067 1068 /* Wait for codec ready signal */ 1069 n = 0; 1070 do { 1071 delay(1000); 1072 if (++n > 1000) { 1073 aprint_error_dev(sc->sc_dev, 1074 "timeout waiting for codec ready\n"); 1075 return -1; 1076 } 1077 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1078 } while (dat32 == 0); 1079 1080 /* Enable Valid Frame output on ASDOUT */ 1081 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1082 1083 /* Wait until codec calibration is finished. codec register 26h */ 1084 n = 0; 1085 do { 1086 delay(1); 1087 if (++n > 1000) { 1088 aprint_error_dev(sc->sc_dev, 1089 "timeout waiting for codec calibration\n"); 1090 return -1; 1091 } 1092 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1093 } while ((data & 0x0f) != 0x0f); 1094 1095 /* Set the serial timing configuration again */ 1096 /* XXX: undocumented but the Linux driver do this */ 1097 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1098 1099 /* Wait until we've sampled input slots 3 & 4 as valid */ 1100 n = 0; 1101 do { 1102 delay(1000); 1103 if (++n > 1000) { 1104 aprint_error_dev(sc->sc_dev, "timeout waiting for " 1105 "sampled input slots as valid\n"); 1106 return -1; 1107 } 1108 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1109 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1110 1111 /* Start digital data transfer of audio data to the codec */ 1112 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1113 1114 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1115 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1116 1117 /* Power on the DAC */ 1118 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1119 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1120 1121 /* Wait until we sample a DAC ready state. 1122 * Not documented, but Linux driver does. 1123 */ 1124 for (n = 0; n < 32; ++n) { 1125 delay(1000); 1126 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1127 if (data & 0x02) 1128 break; 1129 } 1130 1131 /* Power on the ADC */ 1132 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1133 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1134 1135 /* Wait until we sample ADC ready state. 1136 * Not documented, but Linux driver does. 1137 */ 1138 for (n = 0; n < 32; ++n) { 1139 delay(1000); 1140 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1141 if (data & 0x01) 1142 break; 1143 } 1144 1145#if 0 1146 /* Initialize AC-Link features */ 1147 /* variable sample-rate support */ 1148 mem = BA0READ4(sc, CS4281_SERMC); 1149 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1150 BA0WRITE4(sc, CS4281_SERMC, mem); 1151 /* XXX: more... */ 1152 1153 /* Initialize SSCR register features */ 1154 /* XXX: hardware volume setting */ 1155 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1156#endif 1157 1158 /* disable Sound Blaster Pro emulation */ 1159 /* XXX: 1160 * Cannot set since the documents does not describe which bit is 1161 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1162 * we can ignore it.*/ 1163#if 0 1164 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1165#endif 1166 1167 /* map AC97 PCM playback to DMA Channel 0 */ 1168 /* Reset FEN bit to setup first */ 1169 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1170 /* 1171 *| RS[4:0]/| | 1172 *| LS[4:0] | AC97 | Slot Function 1173 *|---------+--------+-------------------- 1174 *| 0 | 3 | Left PCM Playback 1175 *| 1 | 4 | Right PCM Playback 1176 *| 2 | 5 | Phone Line 1 DAC 1177 *| 3 | 6 | Center PCM Playback 1178 *.... 1179 * quoted from Table 29(p109) 1180 */ 1181 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1182 0x00 << 16 | /* LS[4:0] = 0 see above */ 1183 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1184 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1185 BA0WRITE4(sc, CS4281_FCR0, dat32); 1186 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1187 1188 /* map AC97 PCM record to DMA Channel 1 */ 1189 /* Reset FEN bit to setup first */ 1190 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1191 /* 1192 *| RS[4:0]/| 1193 *| LS[4:0] | AC97 | Slot Function 1194 *|---------+------+------------------- 1195 *| 10 | 3 | Left PCM Record 1196 *| 11 | 4 | Right PCM Record 1197 *| 12 | 5 | Phone Line 1 ADC 1198 *| 13 | 6 | Mic ADC 1199 *.... 1200 * quoted from Table 30(p109) 1201 */ 1202 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1203 0x0a << 16 | /* LS[4:0] = 10 See above */ 1204 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1205 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1206 1207 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1208 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1209 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1210 1211#if 0 1212 /* Disable DMA Channel 2, 3 */ 1213 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1214 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1215#endif 1216 1217 /* Set the SRC Slot Assignment accordingly */ 1218 /*| PLSS[4:0]/ 1219 *| PRSS[4:0] | AC97 | Slot Function 1220 *|-----------+------+---------------- 1221 *| 0 | 3 | Left PCM Playback 1222 *| 1 | 4 | Right PCM Playback 1223 *| 2 | 5 | phone line 1 DAC 1224 *| 3 | 6 | Center PCM Playback 1225 *| 4 | 7 | Left Surround PCM Playback 1226 *| 5 | 8 | Right Surround PCM Playback 1227 *...... 1228 * 1229 *| CLSS[4:0]/ 1230 *| CRSS[4:0] | AC97 | Codec |Slot Function 1231 *|-----------+------+-------+----------------- 1232 *| 10 | 3 |Primary| Left PCM Record 1233 *| 11 | 4 |Primary| Right PCM Record 1234 *| 12 | 5 |Primary| Phone Line 1 ADC 1235 *| 13 | 6 |Primary| Mic ADC 1236 *|..... 1237 *| 20 | 3 | Sec. | Left PCM Record 1238 *| 21 | 4 | Sec. | Right PCM Record 1239 *| 22 | 5 | Sec. | Phone Line 1 ADC 1240 *| 23 | 6 | Sec. | Mic ADC 1241 */ 1242 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1243 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1244 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1245 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1246 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1247 1248 /* Set interrupt to occurred at Half and Full terminal 1249 * count interrupt enable for DMA channel 0 and 1. 1250 * To keep DMA stop, set MSK. 1251 */ 1252 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1253 BA0WRITE4(sc, CS4281_DCR0, dat32); 1254 BA0WRITE4(sc, CS4281_DCR1, dat32); 1255 1256 /* Set Auto-Initialize Contorl enable */ 1257 BA0WRITE4(sc, CS4281_DMR0, 1258 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1259 BA0WRITE4(sc, CS4281_DMR1, 1260 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1261 1262 /* Clear DMA Mask in HIMR */ 1263 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1264 BA0WRITE4(sc, CS4281_HIMR, 1265 BA0READ4(sc, CS4281_HIMR) & dat32); 1266 1267 /* set current status */ 1268 if (init != 0) { 1269 sc->sc_prun = 0; 1270 sc->sc_rrun = 0; 1271 } 1272 1273 /* setup playback volume */ 1274 BA0WRITE4(sc, CS4281_PPRVC, 7); 1275 BA0WRITE4(sc, CS4281_PPLVC, 7); 1276 1277 return 0; 1278} 1279