cs4281.c revision 1.21
1/* $NetBSD: cs4281.c,v 1.21 2004/11/02 00:40:08 yamt Exp $ */ 2 3/* 4 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tatoku Ogaito 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Cirrus Logic CS4281 driver. 35 * Data sheets can be found 36 * http://www.cirrus.com/ftp/pub/4281.pdf 37 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 38 * 39 * TODO: 40 * 1: midi and FM support 41 * 2: ... 42 * 43 */ 44 45#include <sys/cdefs.h> 46__KERNEL_RCSID(0, "$NetBSD: cs4281.c,v 1.21 2004/11/02 00:40:08 yamt Exp $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/kernel.h> 51#include <sys/malloc.h> 52#include <sys/fcntl.h> 53#include <sys/device.h> 54#include <sys/systm.h> 55 56#include <dev/pci/pcidevs.h> 57#include <dev/pci/pcivar.h> 58#include <dev/pci/cs4281reg.h> 59#include <dev/pci/cs428xreg.h> 60 61#include <sys/audioio.h> 62#include <dev/audio_if.h> 63#include <dev/midi_if.h> 64#include <dev/mulaw.h> 65#include <dev/auconv.h> 66 67#include <dev/ic/ac97reg.h> 68#include <dev/ic/ac97var.h> 69 70#include <dev/pci/cs428x.h> 71 72#include <machine/bus.h> 73 74#if defined(ENABLE_SECONDARY_CODEC) 75#define MAX_CHANNELS (4) 76#define MAX_FIFO_SIZE 32 /* 128/4channels */ 77#else 78#define MAX_CHANNELS (2) 79#define MAX_FIFO_SIZE 64 /* 128/2channels */ 80#endif 81 82/* IF functions for audio driver */ 83int cs4281_match(struct device *, struct cfdata *, void *); 84void cs4281_attach(struct device *, struct device *, void *); 85int cs4281_intr(void *); 86int cs4281_query_encoding(void *, struct audio_encoding *); 87int cs4281_set_params(void *, int, int, struct audio_params *, struct audio_params *); 88int cs4281_halt_output(void *); 89int cs4281_halt_input(void *); 90int cs4281_getdev(void *, struct audio_device *); 91int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 92 void *, struct audio_params *); 93int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 94 void *, struct audio_params *); 95 96int cs4281_reset_codec(void *); 97 98/* Internal functions */ 99u_int8_t cs4281_sr2regval(int); 100void cs4281_set_dac_rate(struct cs428x_softc *, int); 101void cs4281_set_adc_rate(struct cs428x_softc *, int); 102int cs4281_init(struct cs428x_softc *, int); 103 104/* Power Management */ 105void cs4281_power(int, void *); 106 107const struct audio_hw_if cs4281_hw_if = { 108 cs428x_open, 109 cs428x_close, 110 NULL, 111 cs4281_query_encoding, 112 cs4281_set_params, 113 cs428x_round_blocksize, 114 NULL, 115 NULL, 116 NULL, 117 NULL, 118 NULL, 119 cs4281_halt_output, 120 cs4281_halt_input, 121 NULL, 122 cs4281_getdev, 123 NULL, 124 cs428x_mixer_set_port, 125 cs428x_mixer_get_port, 126 cs428x_query_devinfo, 127 cs428x_malloc, 128 cs428x_free, 129 cs428x_round_buffersize, 130 cs428x_mappage, 131 cs428x_get_props, 132 cs4281_trigger_output, 133 cs4281_trigger_input, 134 NULL, 135}; 136 137#if NMIDI > 0 && 0 138/* Midi Interface */ 139void cs4281_midi_close(void*); 140void cs4281_midi_getinfo(void *, struct midi_info *); 141int cs4281_midi_open(void *, int, void (*)(void *, int), 142 void (*)(void *), void *); 143int cs4281_midi_output(void *, int); 144 145const struct midi_hw_if cs4281_midi_hw_if = { 146 cs4281_midi_open, 147 cs4281_midi_close, 148 cs4281_midi_output, 149 cs4281_midi_getinfo, 150 0, 151}; 152#endif 153 154CFATTACH_DECL(clct, sizeof(struct cs428x_softc), 155 cs4281_match, cs4281_attach, NULL, NULL); 156 157struct audio_device cs4281_device = { 158 "CS4281", 159 "", 160 "cs4281" 161}; 162 163 164int 165cs4281_match(parent, match, aux) 166 struct device *parent; 167 struct cfdata *match; 168 void *aux; 169{ 170 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 173 return 0; 174 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4281) 175 return 1; 176 return 0; 177} 178 179void 180cs4281_attach(parent, self, aux) 181 struct device *parent; 182 struct device *self; 183 void *aux; 184{ 185 struct cs428x_softc *sc = (struct cs428x_softc *)self; 186 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 187 pci_chipset_tag_t pc = pa->pa_pc; 188 char const *intrstr; 189 pci_intr_handle_t ih; 190 pcireg_t reg; 191 char devinfo[256]; 192 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 193 194 aprint_naive(": Audio controller\n"); 195 196 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 197 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 198 PCI_REVISION(pa->pa_class)); 199 200 /* Map I/O register */ 201 if (pci_mapreg_map(pa, PCI_BA0, 202 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 203 &sc->ba0t, &sc->ba0h, NULL, NULL)) { 204 aprint_error("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 205 return; 206 } 207 if (pci_mapreg_map(pa, PCI_BA1, 208 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 209 &sc->ba1t, &sc->ba1h, NULL, NULL)) { 210 aprint_error("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 211 return; 212 } 213 214 sc->sc_dmatag = pa->pa_dmat; 215 216 /* 217 * Set Power State D0. 218 * Without do this, 0xffffffff is read from all registers after 219 * using Windows. 220 * On my IBM Thinkpad X20, it is set to D3 after using Windows2000. 221 */ 222 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 223 &pci_pwrmgmt_cap_reg, 0)) { 224 225 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + PCI_PMCSR; 226 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 227 pci_pwrmgmt_csr_reg); 228 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 229 pci_conf_write(pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 230 (reg & ~PCI_PMCSR_STATE_MASK) | 231 PCI_PMCSR_STATE_D0); 232 } 233 } 234 235 /* Enable the device (set bus master flag) */ 236 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 237 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 238 reg | PCI_COMMAND_MASTER_ENABLE); 239 240#if 0 241 /* LATENCY_TIMER setting */ 242 temp1 = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 243 if (PCI_LATTIMER(temp1) < 32) { 244 temp1 &= 0xffff00ff; 245 temp1 |= 0x00002000; 246 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, temp1); 247 } 248#endif 249 250 /* Map and establish the interrupt. */ 251 if (pci_intr_map(pa, &ih)) { 252 aprint_error("%s: couldn't map interrupt\n", 253 sc->sc_dev.dv_xname); 254 return; 255 } 256 intrstr = pci_intr_string(pc, ih); 257 258 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc); 259 if (sc->sc_ih == NULL) { 260 aprint_error("%s: couldn't establish interrupt", 261 sc->sc_dev.dv_xname); 262 if (intrstr != NULL) 263 aprint_normal(" at %s", intrstr); 264 aprint_normal("\n"); 265 return; 266 } 267 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 268 269 /* 270 * Sound System start-up 271 */ 272 if (cs4281_init(sc, 1) != 0) 273 return; 274 275 sc->type = TYPE_CS4281; 276 sc->halt_input = cs4281_halt_input; 277 sc->halt_output = cs4281_halt_output; 278 279 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 280 sc->dma_align = 0x10; 281 sc->hw_blocksize = sc->dma_size / 2; 282 283 /* AC 97 attachment */ 284 sc->host_if.arg = sc; 285 sc->host_if.attach = cs428x_attach_codec; 286 sc->host_if.read = cs428x_read_codec; 287 sc->host_if.write = cs428x_write_codec; 288 sc->host_if.reset = cs4281_reset_codec; 289 if (ac97_attach(&sc->host_if) != 0) { 290 aprint_error("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 291 return; 292 } 293 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 294 295#if NMIDI > 0 && 0 296 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 297#endif 298 299 sc->sc_suspend = PWR_RESUME; 300 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 301} 302 303int 304cs4281_intr(p) 305 void *p; 306{ 307 struct cs428x_softc *sc = p; 308 u_int32_t intr, hdsr0, hdsr1; 309 char *empty_dma; 310 int handled = 0; 311 312 hdsr0 = 0; 313 hdsr1 = 0; 314 315 /* grab interrupt register */ 316 intr = BA0READ4(sc, CS4281_HISR); 317 318 DPRINTF(("cs4281_intr:")); 319 /* not for me */ 320 if ((intr & HISR_INTENA) == 0) { 321 /* clear the interrupt register */ 322 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 323 return 0; 324 } 325 326 if (intr & HISR_DMA0) 327 hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 328 if (intr & HISR_DMA1) 329 hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 330 /* clear the interrupt register */ 331 BA0WRITE4(sc, CS4281_HICR, HICR_CHGM | HICR_IEV); 332 333 DPRINTF(("intr = 0x%08x, hdsr0 = 0x%08x hdsr1 = 0x%08x\n", 334 intr, hdsr0, hdsr1)); 335 336 /* Playback Interrupt */ 337 if (intr & HISR_DMA0) { 338 handled = 1; 339 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 340 (int)BA0READ4(sc, CS4281_DCC0))); 341 if (sc->sc_prun) { 342 if ((sc->sc_pi%sc->sc_pcount) == 0) 343 sc->sc_pintr(sc->sc_parg); 344 } else { 345 printf("unexpected play intr\n"); 346 } 347 /* copy buffer */ 348 ++sc->sc_pi; 349 empty_dma = sc->sc_pdma->addr; 350 if (sc->sc_pi&1) 351 empty_dma += sc->hw_blocksize; 352 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 353 sc->sc_pn += sc->hw_blocksize; 354 if (sc->sc_pn >= sc->sc_pe) 355 sc->sc_pn = sc->sc_ps; 356 } 357 if (intr & HISR_DMA1) { 358 handled = 1; 359 /* copy from DMA */ 360 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 361 (int)BA0READ4(sc, CS4281_DCC1))); 362 ++sc->sc_ri; 363 empty_dma = sc->sc_rdma->addr; 364 if ((sc->sc_ri & 1) == 0) 365 empty_dma += sc->hw_blocksize; 366 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 367 sc->sc_rn += sc->hw_blocksize; 368 if (sc->sc_rn >= sc->sc_re) 369 sc->sc_rn = sc->sc_rs; 370 if (sc->sc_rrun) { 371 if ((sc->sc_ri % sc->sc_rcount) == 0) 372 sc->sc_rintr(sc->sc_rarg); 373 } else { 374 printf("unexpected record intr\n"); 375 } 376 } 377 DPRINTF(("\n")); 378 379 return handled; 380} 381 382int 383cs4281_query_encoding(addr, fp) 384 void *addr; 385 struct audio_encoding *fp; 386{ 387 388 switch (fp->index) { 389 case 0: 390 strcpy(fp->name, AudioEulinear); 391 fp->encoding = AUDIO_ENCODING_ULINEAR; 392 fp->precision = 8; 393 fp->flags = 0; 394 break; 395 case 1: 396 strcpy(fp->name, AudioEmulaw); 397 fp->encoding = AUDIO_ENCODING_ULAW; 398 fp->precision = 8; 399 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 400 break; 401 case 2: 402 strcpy(fp->name, AudioEalaw); 403 fp->encoding = AUDIO_ENCODING_ALAW; 404 fp->precision = 8; 405 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 406 break; 407 case 3: 408 strcpy(fp->name, AudioEslinear); 409 fp->encoding = AUDIO_ENCODING_SLINEAR; 410 fp->precision = 8; 411 fp->flags = 0; 412 break; 413 case 4: 414 strcpy(fp->name, AudioEslinear_le); 415 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 416 fp->precision = 16; 417 fp->flags = 0; 418 break; 419 case 5: 420 strcpy(fp->name, AudioEulinear_le); 421 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 422 fp->precision = 16; 423 fp->flags = 0; 424 break; 425 case 6: 426 strcpy(fp->name, AudioEslinear_be); 427 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 428 fp->precision = 16; 429 fp->flags = 0; 430 break; 431 case 7: 432 strcpy(fp->name, AudioEulinear_be); 433 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 434 fp->precision = 16; 435 fp->flags = 0; 436 break; 437 default: 438 return EINVAL; 439 } 440 return 0; 441} 442 443int 444cs4281_set_params(addr, setmode, usemode, play, rec) 445 void *addr; 446 int setmode, usemode; 447 struct audio_params *play, *rec; 448{ 449 struct cs428x_softc *sc = addr; 450 struct audio_params *p; 451 int mode; 452 453 for (mode = AUMODE_RECORD; mode != -1; 454 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 455 if ((setmode & mode) == 0) 456 continue; 457 458 p = mode == AUMODE_PLAY ? play : rec; 459 460 if (p == play) { 461 DPRINTFN(5, ("play: sample=%ld precision=%d channels=%d\n", 462 p->sample_rate, p->precision, p->channels)); 463 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 464 (p->precision != 8 && p->precision != 16) || 465 (p->channels != 1 && p->channels != 2)) { 466 return (EINVAL); 467 } 468 } else { 469 DPRINTFN(5, ("rec: sample=%ld precision=%d channels=%d\n", 470 p->sample_rate, p->precision, p->channels)); 471 if (p->sample_rate < 6023 || p->sample_rate > 48000 || 472 (p->precision != 8 && p->precision != 16) || 473 (p->channels != 1 && p->channels != 2)) { 474 return (EINVAL); 475 } 476 } 477 p->factor = 1; 478 p->sw_code = 0; 479 480 switch (p->encoding) { 481 case AUDIO_ENCODING_SLINEAR_BE: 482 break; 483 case AUDIO_ENCODING_SLINEAR_LE: 484 break; 485 case AUDIO_ENCODING_ULINEAR_BE: 486 break; 487 case AUDIO_ENCODING_ULINEAR_LE: 488 break; 489 case AUDIO_ENCODING_ULAW: 490 if (mode == AUMODE_PLAY) { 491 p->sw_code = mulaw_to_slinear8; 492 } else { 493 p->sw_code = slinear8_to_mulaw; 494 } 495 break; 496 case AUDIO_ENCODING_ALAW: 497 if (mode == AUMODE_PLAY) { 498 p->sw_code = alaw_to_slinear8; 499 } else { 500 p->sw_code = slinear8_to_alaw; 501 } 502 break; 503 default: 504 return (EINVAL); 505 } 506 } 507 508 /* set sample rate */ 509 cs4281_set_dac_rate(sc, play->sample_rate); 510 cs4281_set_adc_rate(sc, rec->sample_rate); 511 return 0; 512} 513 514int 515cs4281_halt_output(addr) 516 void *addr; 517{ 518 struct cs428x_softc *sc = addr; 519 520 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 521 sc->sc_prun = 0; 522 return 0; 523} 524 525int 526cs4281_halt_input(addr) 527 void *addr; 528{ 529 struct cs428x_softc *sc = addr; 530 531 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 532 sc->sc_rrun = 0; 533 return 0; 534} 535 536int 537cs4281_getdev(addr, retp) 538 void *addr; 539 struct audio_device *retp; 540{ 541 542 *retp = cs4281_device; 543 return 0; 544} 545 546int 547cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 548 void *addr; 549 void *start, *end; 550 int blksize; 551 void (*intr) __P((void *)); 552 void *arg; 553 struct audio_params *param; 554{ 555 struct cs428x_softc *sc = addr; 556 u_int32_t fmt=0; 557 struct cs428x_dma *p; 558 int dma_count; 559 560#ifdef DIAGNOSTIC 561 if (sc->sc_prun) 562 printf("cs4281_trigger_output: already running\n"); 563#endif 564 sc->sc_prun = 1; 565 566 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 567 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 568 sc->sc_pintr = intr; 569 sc->sc_parg = arg; 570 571 /* stop playback DMA */ 572 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 573 574 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 575 param->precision, param->factor, param->channels, 576 param->encoding)); 577 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 578 ; 579 if (p == NULL) { 580 printf("cs4281_trigger_output: bad addr %p\n", start); 581 return (EINVAL); 582 } 583 584 sc->sc_pcount = blksize / sc->hw_blocksize; 585 sc->sc_ps = (char *)start; 586 sc->sc_pe = (char *)end; 587 sc->sc_pdma = p; 588 sc->sc_pbuf = KERNADDR(p); 589 sc->sc_pi = 0; 590 sc->sc_pn = sc->sc_ps; 591 if (blksize >= sc->dma_size) { 592 sc->sc_pn = sc->sc_ps + sc->dma_size; 593 memcpy(sc->sc_pbuf, start, sc->dma_size); 594 ++sc->sc_pi; 595 } else { 596 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 597 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 598 } 599 600 dma_count = sc->dma_size; 601 if (param->precision * param->factor != 8) 602 dma_count /= 2; /* 16 bit */ 603 if (param->channels > 1) 604 dma_count /= 2; /* Stereo */ 605 606 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 607 (int)DMAADDR(p), dma_count)); 608 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 609 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 610 611 /* set playback format */ 612 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 613 if (param->precision * param->factor == 8) 614 fmt |= DMRn_SIZE8; 615 if (param->channels == 1) 616 fmt |= DMRn_MONO; 617 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 618 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 619 fmt |= DMRn_BEND; 620 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 621 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 622 fmt |= DMRn_USIGN; 623 BA0WRITE4(sc, CS4281_DMR0, fmt); 624 625 /* set sample rate */ 626 sc->sc_prate = param->sample_rate; 627 cs4281_set_dac_rate(sc, param->sample_rate); 628 629 /* start DMA */ 630 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 631 /* Enable interrupts */ 632 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 633 634 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 635 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 636 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 637 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 638 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 639 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 640 BA0READ4(sc, CS4281_DACSR))); 641 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 642 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 643 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 644 645 return 0; 646} 647 648int 649cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 650 void *addr; 651 void *start, *end; 652 int blksize; 653 void (*intr) __P((void *)); 654 void *arg; 655 struct audio_params *param; 656{ 657 struct cs428x_softc *sc = addr; 658 struct cs428x_dma *p; 659 u_int32_t fmt=0; 660 int dma_count; 661 662#ifdef DIAGNOSTIC 663 if (sc->sc_rrun) 664 printf("cs4281_trigger_input: already running\n"); 665#endif 666 sc->sc_rrun = 1; 667 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 668 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 669 sc->sc_rintr = intr; 670 sc->sc_rarg = arg; 671 672 /* stop recording DMA */ 673 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 674 675 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 676 ; 677 if (!p) { 678 printf("cs4281_trigger_input: bad addr %p\n", start); 679 return (EINVAL); 680 } 681 682 sc->sc_rcount = blksize / sc->hw_blocksize; 683 sc->sc_rs = (char *)start; 684 sc->sc_re = (char *)end; 685 sc->sc_rdma = p; 686 sc->sc_rbuf = KERNADDR(p); 687 sc->sc_ri = 0; 688 sc->sc_rn = sc->sc_rs; 689 690 dma_count = sc->dma_size; 691 if (param->precision * param->factor != 8) 692 dma_count /= 2; 693 if (param->channels > 1) 694 dma_count /= 2; 695 696 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 697 (int)DMAADDR(p), dma_count)); 698 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 699 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 700 701 /* set recording format */ 702 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 703 if (param->precision * param->factor == 8) 704 fmt |= DMRn_SIZE8; 705 if (param->channels == 1) 706 fmt |= DMRn_MONO; 707 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 708 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 709 fmt |= DMRn_BEND; 710 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 711 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 712 fmt |= DMRn_USIGN; 713 BA0WRITE4(sc, CS4281_DMR1, fmt); 714 715 /* set sample rate */ 716 sc->sc_rrate = param->sample_rate; 717 cs4281_set_adc_rate(sc, param->sample_rate); 718 719 /* Start DMA */ 720 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 721 /* Enable interrupts */ 722 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 723 724 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 725 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 726 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 727 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 728 729 return 0; 730} 731 732/* Power Hook */ 733void 734cs4281_power(why, v) 735 int why; 736 void *v; 737{ 738 struct cs428x_softc *sc = (struct cs428x_softc *)v; 739 static u_int32_t dba0 = 0, dbc0 = 0, dmr0 = 0, dcr0 = 0; 740 static u_int32_t dba1 = 0, dbc1 = 0, dmr1 = 0, dcr1 = 0; 741 742 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 743 switch (why) { 744 case PWR_SUSPEND: 745 case PWR_STANDBY: 746 sc->sc_suspend = why; 747 748 /* save current playback status */ 749 if (sc->sc_prun) { 750 dcr0 = BA0READ4(sc, CS4281_DCR0); 751 dmr0 = BA0READ4(sc, CS4281_DMR0); 752 dbc0 = BA0READ4(sc, CS4281_DBC0); 753 dba0 = BA0READ4(sc, CS4281_DBA0); 754 } 755 756 /* save current capture status */ 757 if (sc->sc_rrun) { 758 dcr1 = BA0READ4(sc, CS4281_DCR1); 759 dmr1 = BA0READ4(sc, CS4281_DMR1); 760 dbc1 = BA0READ4(sc, CS4281_DBC1); 761 dba1 = BA0READ4(sc, CS4281_DBA1); 762 } 763 /* Stop DMA */ 764 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 765 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 766 break; 767 case PWR_RESUME: 768 if (sc->sc_suspend == PWR_RESUME) { 769 printf("cs4281_power: odd, resume without suspend.\n"); 770 sc->sc_suspend = why; 771 return; 772 } 773 sc->sc_suspend = why; 774 cs4281_init(sc, 0); 775 cs4281_reset_codec(sc); 776 777 /* restore ac97 registers */ 778 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if); 779 780 /* restore DMA related status */ 781 if (sc->sc_prun) { 782 cs4281_set_dac_rate(sc, sc->sc_prate); 783 BA0WRITE4(sc, CS4281_DBA0, dba0); 784 BA0WRITE4(sc, CS4281_DBC0, dbc0); 785 BA0WRITE4(sc, CS4281_DMR0, dmr0); 786 BA0WRITE4(sc, CS4281_DCR0, dcr0); 787 } 788 if (sc->sc_rrun) { 789 cs4281_set_adc_rate(sc, sc->sc_rrate); 790 BA0WRITE4(sc, CS4281_DBA1, dba1); 791 BA0WRITE4(sc, CS4281_DBC1, dbc1); 792 BA0WRITE4(sc, CS4281_DMR1, dmr1); 793 BA0WRITE4(sc, CS4281_DCR1, dcr1); 794 } 795 /* enable intterupts */ 796 if (sc->sc_prun || sc->sc_rrun) 797 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 798 break; 799 case PWR_SOFTSUSPEND: 800 case PWR_SOFTSTANDBY: 801 case PWR_SOFTRESUME: 802 break; 803 } 804} 805 806/* control AC97 codec */ 807int 808cs4281_reset_codec(void *addr) 809{ 810 struct cs428x_softc *sc; 811 u_int16_t data; 812 u_int32_t dat32; 813 int n; 814 815 sc = addr; 816 817 DPRINTFN(3, ("cs4281_reset_codec\n")); 818 819 /* Reset codec */ 820 BA0WRITE4(sc, CS428X_ACCTL, 0); 821 delay(50); /* delay 50us */ 822 823 BA0WRITE4(sc, CS4281_SPMC, 0); 824 delay(100); /* delay 100us */ 825 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 826#if defined(ENABLE_SECONDARY_CODEC) 827 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 828 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 829#endif 830 delay(50000); /* XXX: delay 50ms */ 831 832 /* Enable ASYNC generation */ 833 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 834 835 /* Wait for codec ready. Linux driver waits 50ms here */ 836 n = 0; 837 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 838 delay(100); 839 if (++n > 1000) { 840 printf("reset_codec: AC97 codec ready timeout\n"); 841 return ETIMEDOUT; 842 } 843 } 844#if defined(ENABLE_SECONDARY_CODEC) 845 /* secondary codec ready*/ 846 n = 0; 847 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 848 delay(100); 849 if (++n > 1000) 850 return 0; 851 } 852#endif 853 /* Set the serial timing configuration */ 854 /* XXX: undocumented but the Linux driver do this */ 855 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 856 857 /* Wait for codec ready signal */ 858 n = 0; 859 do { 860 delay(1000); 861 if (++n > 1000) { 862 printf("%s: timeout waiting for codec ready\n", 863 sc->sc_dev.dv_xname); 864 return ETIMEDOUT; 865 } 866 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 867 } while (dat32 == 0); 868 869 /* Enable Valid Frame output on ASDOUT */ 870 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 871 872 /* Wait until codec calibration is finished. Codec register 26h */ 873 n = 0; 874 do { 875 delay(1); 876 if (++n > 1000) { 877 printf("%s: timeout waiting for codec calibration\n", 878 sc->sc_dev.dv_xname); 879 return ETIMEDOUT; 880 } 881 cs428x_read_codec(sc, AC97_REG_POWER, &data); 882 } while ((data & 0x0f) != 0x0f); 883 884 /* Set the serial timing configuration again */ 885 /* XXX: undocumented but the Linux driver do this */ 886 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 887 888 /* Wait until we've sampled input slots 3 & 4 as valid */ 889 n = 0; 890 do { 891 delay(1000); 892 if (++n > 1000) { 893 printf("%s: timeout waiting for sampled input slots as valid\n", 894 sc->sc_dev.dv_xname); 895 return ETIMEDOUT; 896 } 897 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 898 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 899 900 /* Start digital data transfer of audio data to the codec */ 901 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 902 return 0; 903} 904 905 906/* Internal functions */ 907 908/* convert sample rate to register value */ 909u_int8_t 910cs4281_sr2regval(rate) 911 int rate; 912{ 913 u_int8_t retval; 914 915 /* We don't have to change here. but anyway ... */ 916 if (rate > 48000) 917 rate = 48000; 918 if (rate < 6023) 919 rate = 6023; 920 921 switch (rate) { 922 case 8000: 923 retval = 5; 924 break; 925 case 11025: 926 retval = 4; 927 break; 928 case 16000: 929 retval = 3; 930 break; 931 case 22050: 932 retval = 2; 933 break; 934 case 44100: 935 retval = 1; 936 break; 937 case 48000: 938 retval = 0; 939 break; 940 default: 941 retval = 1536000/rate; /* == 24576000/(rate*16) */ 942 } 943 return retval; 944} 945 946void 947cs4281_set_adc_rate(sc, rate) 948 struct cs428x_softc *sc; 949 int rate; 950{ 951 952 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 953} 954 955void 956cs4281_set_dac_rate(sc, rate) 957 struct cs428x_softc *sc; 958 int rate; 959{ 960 961 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 962} 963 964int 965cs4281_init(sc, init) 966 struct cs428x_softc *sc; 967 int init; 968{ 969 int n; 970 u_int16_t data; 971 u_int32_t dat32; 972 973 /* set "Configuration Write Protect" register to 974 * 0x4281 to allow to write */ 975 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 976 977 /* 978 * Unset "Full Power-Down bit of Extended PCI Power Management 979 * Control" register to release the reset state. 980 */ 981 dat32 = BA0READ4(sc, CS4281_EPPMC); 982 if (dat32 & EPPMC_FPDN) { 983 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 984 } 985 986 /* Start PLL out in known state */ 987 BA0WRITE4(sc, CS4281_CLKCR1, 0); 988 /* Start serial ports out in known state */ 989 BA0WRITE4(sc, CS4281_SERMC, 0); 990 991 /* Reset codec */ 992 BA0WRITE4(sc, CS428X_ACCTL, 0); 993 delay(50); /* delay 50us */ 994 995 BA0WRITE4(sc, CS4281_SPMC, 0); 996 delay(100); /* delay 100us */ 997 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 998#if defined(ENABLE_SECONDARY_CODEC) 999 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 1000 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 1001#endif 1002 delay(50000); /* XXX: delay 50ms */ 1003 1004 /* Turn on Sound System clocks based on ABITCLK */ 1005 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 1006 delay(50000); /* XXX: delay 50ms */ 1007 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 1008 1009 /* Set enables for sections that are needed in the SSPM registers */ 1010 BA0WRITE4(sc, CS4281_SSPM, 1011 SSPM_MIXEN | /* Mixer */ 1012 SSPM_CSRCEN | /* Capture SRC */ 1013 SSPM_PSRCEN | /* Playback SRC */ 1014 SSPM_JSEN | /* Joystick */ 1015 SSPM_ACLEN | /* AC LINK */ 1016 SSPM_FMEN /* FM */ 1017 ); 1018 1019 /* Wait for clock stabilization */ 1020 n = 0; 1021#if 1 1022 /* what document says */ 1023 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 1024 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 1025 delay(100); 1026 if (++n > 1000) { 1027 printf("%s: timeout waiting for clock stabilization\n", 1028 sc->sc_dev.dv_xname); 1029 return -1; 1030 } 1031 } 1032#else 1033 /* Cirrus driver for Linux does */ 1034 while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) { 1035 delay(1000); 1036 if (++n > 1000) { 1037 printf("%s: timeout waiting for clock stabilization\n", 1038 sc->sc_dev.dv_xname); 1039 return -1; 1040 } 1041 } 1042#endif 1043 1044 /* Enable ASYNC generation */ 1045 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN); 1046 1047 /* Wait for codec ready. Linux driver waits 50ms here */ 1048 n = 0; 1049 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) { 1050 delay(100); 1051 if (++n > 1000) { 1052 printf("%s: timeout waiting for codec ready\n", 1053 sc->sc_dev.dv_xname); 1054 return -1; 1055 } 1056 } 1057 1058#if defined(ENABLE_SECONDARY_CODEC) 1059 /* secondary codec ready*/ 1060 n = 0; 1061 while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1062 delay(100); 1063 if (++n > 1000) { 1064 printf("%s: timeout waiting for secondary codec ready\n", 1065 sc->sc_dev.dv_xname); 1066 return -1; 1067 } 1068 } 1069#endif 1070 1071 /* Set the serial timing configuration */ 1072 /* XXX: undocumented but the Linux driver do this */ 1073 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1074 1075 /* Wait for codec ready signal */ 1076 n = 0; 1077 do { 1078 delay(1000); 1079 if (++n > 1000) { 1080 printf("%s: timeout waiting for codec ready\n", 1081 sc->sc_dev.dv_xname); 1082 return -1; 1083 } 1084 dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY; 1085 } while (dat32 == 0); 1086 1087 /* Enable Valid Frame output on ASDOUT */ 1088 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1089 1090 /* Wait until codec calibration is finished. codec register 26h */ 1091 n = 0; 1092 do { 1093 delay(1); 1094 if (++n > 1000) { 1095 printf("%s: timeout waiting for codec calibration\n", 1096 sc->sc_dev.dv_xname); 1097 return -1; 1098 } 1099 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1100 } while ((data & 0x0f) != 0x0f); 1101 1102 /* Set the serial timing configuration again */ 1103 /* XXX: undocumented but the Linux driver do this */ 1104 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1105 1106 /* Wait until we've sampled input slots 3 & 4 as valid */ 1107 n = 0; 1108 do { 1109 delay(1000); 1110 if (++n > 1000) { 1111 printf("%s: timeout waiting for sampled input slots as valid\n", 1112 sc->sc_dev.dv_xname); 1113 return -1; 1114 } 1115 dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 1116 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1117 1118 /* Start digital data transfer of audio data to the codec */ 1119 BA0WRITE4(sc, CS428X_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1120 1121 cs428x_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 1122 cs428x_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 1123 1124 /* Power on the DAC */ 1125 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1126 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfdff); 1127 1128 /* Wait until we sample a DAC ready state. 1129 * Not documented, but Linux driver does. 1130 */ 1131 for (n = 0; n < 32; ++n) { 1132 delay(1000); 1133 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1134 if (data & 0x02) 1135 break; 1136 } 1137 1138 /* Power on the ADC */ 1139 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1140 cs428x_write_codec(sc, AC97_REG_POWER, data & 0xfeff); 1141 1142 /* Wait until we sample ADC ready state. 1143 * Not documented, but Linux driver does. 1144 */ 1145 for (n = 0; n < 32; ++n) { 1146 delay(1000); 1147 cs428x_read_codec(sc, AC97_REG_POWER, &data); 1148 if (data & 0x01) 1149 break; 1150 } 1151 1152#if 0 1153 /* Initialize AC-Link features */ 1154 /* variable sample-rate support */ 1155 mem = BA0READ4(sc, CS4281_SERMC); 1156 mem |= (SERMC_ODSEN1 | SERMC_ODSEN2); 1157 BA0WRITE4(sc, CS4281_SERMC, mem); 1158 /* XXX: more... */ 1159 1160 /* Initialize SSCR register features */ 1161 /* XXX: hardware volume setting */ 1162 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1163#endif 1164 1165 /* disable Sound Blaster Pro emulation */ 1166 /* XXX: 1167 * Cannot set since the documents does not describe which bit is 1168 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1169 * we can ignore it.*/ 1170#if 0 1171 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1172#endif 1173 1174 /* map AC97 PCM playback to DMA Channel 0 */ 1175 /* Reset FEN bit to setup first */ 1176 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN)); 1177 /* 1178 *| RS[4:0]/| | 1179 *| LS[4:0] | AC97 | Slot Function 1180 *|---------+--------+-------------------- 1181 *| 0 | 3 | Left PCM Playback 1182 *| 1 | 4 | Right PCM Playback 1183 *| 2 | 5 | Phone Line 1 DAC 1184 *| 3 | 6 | Center PCM Playback 1185 *.... 1186 * quoted from Table 29(p109) 1187 */ 1188 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1189 0x00 << 16 | /* LS[4:0] = 0 see above */ 1190 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1191 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1192 BA0WRITE4(sc, CS4281_FCR0, dat32); 1193 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1194 1195 /* map AC97 PCM record to DMA Channel 1 */ 1196 /* Reset FEN bit to setup first */ 1197 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN)); 1198 /* 1199 *| RS[4:0]/| 1200 *| LS[4:0] | AC97 | Slot Function 1201 *|---------+------+------------------- 1202 *| 10 | 3 | Left PCM Record 1203 *| 11 | 4 | Right PCM Record 1204 *| 12 | 5 | Phone Line 1 ADC 1205 *| 13 | 6 | Mic ADC 1206 *.... 1207 * quoted from Table 30(p109) 1208 */ 1209 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1210 0x0a << 16 | /* LS[4:0] = 10 See above */ 1211 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1212 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1213 1214 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1215 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1216 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1217 1218#if 0 1219 /* Disable DMA Channel 2, 3 */ 1220 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN)); 1221 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN)); 1222#endif 1223 1224 /* Set the SRC Slot Assignment accordingly */ 1225 /*| PLSS[4:0]/ 1226 *| PRSS[4:0] | AC97 | Slot Function 1227 *|-----------+------+---------------- 1228 *| 0 | 3 | Left PCM Playback 1229 *| 1 | 4 | Right PCM Playback 1230 *| 2 | 5 | phone line 1 DAC 1231 *| 3 | 6 | Center PCM Playback 1232 *| 4 | 7 | Left Surround PCM Playback 1233 *| 5 | 8 | Right Surround PCM Playback 1234 *...... 1235 * 1236 *| CLSS[4:0]/ 1237 *| CRSS[4:0] | AC97 | Codec |Slot Function 1238 *|-----------+------+-------+----------------- 1239 *| 10 | 3 |Primary| Left PCM Record 1240 *| 11 | 4 |Primary| Right PCM Record 1241 *| 12 | 5 |Primary| Phone Line 1 ADC 1242 *| 13 | 6 |Primary| Mic ADC 1243 *|..... 1244 *| 20 | 3 | Sec. | Left PCM Record 1245 *| 21 | 4 | Sec. | Right PCM Record 1246 *| 22 | 5 | Sec. | Phone Line 1 ADC 1247 *| 23 | 6 | Sec. | Mic ADC 1248 */ 1249 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1250 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1251 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1252 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1253 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1254 1255 /* Set interrupt to occurred at Half and Full terminal 1256 * count interrupt enable for DMA channel 0 and 1. 1257 * To keep DMA stop, set MSK. 1258 */ 1259 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1260 BA0WRITE4(sc, CS4281_DCR0, dat32); 1261 BA0WRITE4(sc, CS4281_DCR1, dat32); 1262 1263 /* Set Auto-Initialize Contorl enable */ 1264 BA0WRITE4(sc, CS4281_DMR0, 1265 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1266 BA0WRITE4(sc, CS4281_DMR1, 1267 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1268 1269 /* Clear DMA Mask in HIMR */ 1270 dat32 = ~HIMR_DMAIM & ~HIMR_D1IM & ~HIMR_D0IM; 1271 BA0WRITE4(sc, CS4281_HIMR, 1272 BA0READ4(sc, CS4281_HIMR) & dat32); 1273 1274 /* set current status */ 1275 if (init != 0) { 1276 sc->sc_prun = 0; 1277 sc->sc_rrun = 0; 1278 } 1279 1280 /* setup playback volume */ 1281 BA0WRITE4(sc, CS4281_PPRVC, 7); 1282 BA0WRITE4(sc, CS4281_PPLVC, 7); 1283 1284 return 0; 1285} 1286