1/*	$NetBSD: artsata.c,v 1.30 2023/01/23 21:52:01 andvar Exp $	*/
2
3/*-
4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of Wasabi Systems, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.30 2023/01/23 21:52:01 andvar Exp $");
34
35#include "opt_pciide.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39
40#include <dev/pci/pcivar.h>
41#include <dev/pci/pcidevs.h>
42#include <dev/pci/pciidereg.h>
43#include <dev/pci/pciidevar.h>
44#include <dev/pci/pciide_i31244_reg.h>
45
46#include <dev/ata/satareg.h>
47#include <dev/ata/satavar.h>
48#include <dev/ata/atareg.h>
49#include <dev/ata/atavar.h>
50
51static void artisea_chip_map(struct pciide_softc*,
52    const struct pci_attach_args *);
53
54static int  artsata_match(device_t, cfdata_t, void *);
55static void artsata_attach(device_t, device_t, void *);
56
57static const struct pciide_product_desc pciide_artsata_products[] =  {
58	{ PCI_PRODUCT_INTEL_31244,
59	  0,
60	  "Intel 31244 Serial ATA Controller",
61	  artisea_chip_map,
62	},
63	{ 0,
64	  0,
65	  NULL,
66	  NULL
67	}
68};
69
70struct artisea_cmd_map
71{
72	u_int8_t offset;
73	u_int8_t size;
74};
75
76static const struct artisea_cmd_map artisea_dpa_cmd_map[] =
77{
78	{ARTISEA_SUPDDR, 4},	/* 0 Data */
79	{ARTISEA_SUPDER, 1},	/* 1 Error */
80	{ARTISEA_SUPDCSR, 2},	/* 2 Sector Count */
81	{ARTISEA_SUPDSNR, 2},	/* 3 Sector Number */
82	{ARTISEA_SUPDCLR, 2},	/* 4 Cylinder Low */
83	{ARTISEA_SUPDCHR, 2},	/* 5 Cylinder High */
84	{ARTISEA_SUPDDHR, 1},	/* 6 Device/Head */
85	{ARTISEA_SUPDCR, 1},	/* 7 Command */
86	{ARTISEA_SUPDSR, 1},	/* 8 Status */
87	{ARTISEA_SUPDFR, 2}	/* 9 Feature */
88};
89
90#define ARTISEA_NUM_CHAN 4
91
92CFATTACH_DECL_NEW(artsata, sizeof(struct pciide_softc),
93    artsata_match, artsata_attach, pciide_detach, NULL);
94
95static int
96artsata_match(device_t parent, cfdata_t match, void *aux)
97{
98	struct pci_attach_args *pa = aux;
99
100	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
101		if (pciide_lookup_product(pa->pa_id, pciide_artsata_products))
102			return (2);
103	}
104	return (0);
105}
106
107static void
108artsata_attach(device_t parent, device_t self, void *aux)
109{
110	struct pci_attach_args *pa = aux;
111	struct pciide_softc *sc = device_private(self);
112
113	sc->sc_wdcdev.sc_atac.atac_dev = self;
114
115	pciide_common_attach(sc, pa,
116	    pciide_lookup_product(pa->pa_id, pciide_artsata_products));
117
118}
119
120static void
121artisea_mapregs(const struct pci_attach_args *pa, struct pciide_channel *cp,
122    int (*pci_intr)(void *))
123{
124	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
125	struct ata_channel *wdc_cp = &cp->ata_channel;
126	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
127	const char *intrstr;
128	pci_intr_handle_t intrhandle;
129	int i;
130	char intrbuf[PCI_INTRSTR_LEN];
131
132	cp->compat = 0;
133
134	if (sc->sc_pci_ih == NULL) {
135		if (pci_intr_map(pa, &intrhandle) != 0) {
136			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
137			    "couldn't map native-PCI interrupt\n");
138			goto bad;
139		}
140		intrstr = pci_intr_string(pa->pa_pc, intrhandle,
141		    intrbuf, sizeof(intrbuf));
142		sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
143		    intrhandle, IPL_BIO, pci_intr, sc,
144		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
145		if (sc->sc_pci_ih != NULL) {
146			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
147			    "using %s for native-PCI interrupt\n", intrstr);
148		} else {
149			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
150			    "couldn't establish native-PCI interrupt");
151			if (intrstr != NULL)
152				aprint_error(" at %s", intrstr);
153			aprint_error("\n");
154			goto bad;
155		}
156	}
157	cp->ih = sc->sc_pci_ih;
158	wdr->cmd_iot = sc->sc_ba5_st;
159	if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
160	    ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
161	    &wdr->cmd_baseioh) != 0) {
162		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
163		    "couldn't map %s channel cmd regs\n", cp->name);
164		goto bad;
165	}
166
167	wdr->ctl_iot = sc->sc_ba5_st;
168	if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
169	    ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
170		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
171		    "couldn't map %s channel ctl regs\n", cp->name);
172		goto bad;
173	}
174	wdr->ctl_ioh = cp->ctl_baseioh;
175
176	for (i = 0; i < WDC_NREG + 2; i++) {
177
178		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
179		    artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
180		    &wdr->cmd_iohs[i]) != 0) {
181			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
182			    "couldn't subregion %s channel cmd regs\n",
183			    cp->name);
184			goto bad;
185		}
186	}
187	wdr->data32iot = wdr->cmd_iot;
188	wdr->data32ioh = wdr->cmd_iohs[0];
189
190	wdr->sata_iot = wdr->cmd_iot;
191	wdr->sata_baseioh = wdr->cmd_baseioh;
192
193	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
194	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1,
195	    &wdr->sata_status) != 0) {
196		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
197		    "couldn't map channel %d sata_status regs\n",
198		    wdc_cp->ch_channel);
199		goto bad;
200	}
201	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
202	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1,
203	    &wdr->sata_error) != 0) {
204		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
205		    "couldn't map channel %d sata_error regs\n",
206		    wdc_cp->ch_channel);
207		goto bad;
208	}
209	if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
210	    ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1,
211	    &wdr->sata_control) != 0) {
212		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
213		    "couldn't map channel %d sata_control regs\n",
214		    wdc_cp->ch_channel);
215		goto bad;
216	}
217
218	wdcattach(wdc_cp);
219	return;
220
221bad:
222	wdc_cp->ch_flags |= ATACH_DISABLED;
223	return;
224}
225
226static int
227artisea_chansetup(struct pciide_softc *sc, int channel,
228    pcireg_t interface)
229{
230	struct pciide_channel *cp = &sc->pciide_channels[channel];
231	sc->wdc_chanarray[channel] = &cp->ata_channel;
232	cp->name = PCIIDE_CHANNEL_NAME(channel);
233	cp->ata_channel.ch_channel = channel;
234	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
235
236	return 1;
237}
238
239static void
240artisea_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
241{
242	struct pciide_channel *pc;
243	int chan;
244	u_int32_t dma_ctl;
245	u_int32_t cacheline_len;
246
247	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
248	    "bus-master DMA support present");
249
250	sc->sc_dma_ok = 1;
251
252	/*
253	 * Errata #4 says that if the cacheline length is not set correctly,
254	 * we can get corrupt MWI and Memory-Block-Write transactions.
255	 */
256	cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
257	    PCI_BHLC_REG));
258	if (cacheline_len == 0) {
259		aprint_verbose(", but unused (cacheline size not set in PCI conf)\n");
260		sc->sc_dma_ok = 0;
261		return;
262	}
263
264	/*
265	 * Final step of the work-around is to force the DMA engine to use
266	 * the cache-line length information.
267	 */
268	dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
269	dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
270	pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
271
272	sc->sc_wdcdev.dma_arg = sc;
273	sc->sc_wdcdev.dma_init = pciide_dma_init;
274	sc->sc_wdcdev.dma_start = pciide_dma_start;
275	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
276	sc->sc_dma_iot = sc->sc_ba5_st;
277	sc->sc_dmat = pa->pa_dmat;
278
279	if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
280	    PCIIDE_OPTIONS_NODMA) {
281		aprint_verbose(
282		    ", but unused (forced off by config file)\n");
283		sc->sc_dma_ok = 0;
284		return;
285	}
286
287	/*
288	 * Set up the default handles for the DMA registers.
289	 * Just reserve 32 bits for each handle, unless space
290	 * doesn't permit it.
291	 */
292	for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
293		pc = &sc->pciide_channels[chan];
294		if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
295		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
296		    &pc->dma_iohs[IDEDMA_CMD]) != 0 ||
297		    bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
298		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
299		    &pc->dma_iohs[IDEDMA_CTL]) != 0 ||
300		    bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
301		    ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
302		    &pc->dma_iohs[IDEDMA_TBL]) != 0) {
303			sc->sc_dma_ok = 0;
304			aprint_verbose(", but can't subregion registers\n");
305			return;
306		}
307	}
308
309	aprint_verbose("\n");
310}
311
312static void
313artisea_chip_map_dpa(struct pciide_softc *sc, const struct pci_attach_args *pa)
314{
315	struct pciide_channel *cp;
316	pcireg_t interface;
317	int channel;
318
319	interface = PCI_INTERFACE(pa->pa_class);
320
321	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
322	    "interface wired in DPA mode\n");
323
324	if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT,
325	    0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0)
326		return;
327
328	artisea_mapreg_dma(sc, pa);
329
330	sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
331
332	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
333	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
334	if (sc->sc_dma_ok) {
335		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
336		sc->sc_wdcdev.irqack = pciide_irqack;
337		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
338		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
339	}
340	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
341
342	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
343	sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
344	sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
345	sc->sc_wdcdev.wdc_maxdrives = 1;
346
347	wdc_allocate_regs(&sc->sc_wdcdev);
348
349	/*
350	 * Perform a quick check to ensure that the device isn't configured
351	 * in Spread-spectrum clocking mode.  This feature is buggy and has
352	 * been removed from the latest documentation.
353	 *
354	 * Note that although this bit is in the Channel regs, it's the same
355	 * for all channels, so we check it just once here.
356	 */
357	if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
358	    ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
359	    ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
360		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
361		    "Spread-spectrum clocking not supported by device\n");
362		return;
363	}
364
365	/* Clear the LED0-only bit.  */
366	pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0,
367	    pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) &
368	    ~SUECSR0_LED0_ONLY);
369
370	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
371	     channel++) {
372		cp = &sc->pciide_channels[channel];
373		if (artisea_chansetup(sc, channel, interface) == 0)
374			continue;
375		/* XXX We can probably do interrupts more efficiently.  */
376		artisea_mapregs(pa, cp, pciide_pci_intr);
377	}
378}
379
380static void
381artisea_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
382{
383	struct pciide_channel *cp;
384	pcireg_t interface;
385	int channel;
386
387	if (pciide_chipen(sc, pa) == 0)
388		return;
389
390	interface = PCI_INTERFACE(pa->pa_class);
391
392	if (interface == 0) {
393		artisea_chip_map_dpa (sc, pa);
394		return;
395	}
396
397	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
398	    "bus-master DMA support present");
399#ifdef PCIIDE_I31244_DISABLEDMA
400	if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 &&
401	    PCI_REVISION(pa->pa_class) == 0) {
402		aprint_verbose(" but disabled due to rev. 0");
403		sc->sc_dma_ok = 0;
404	} else
405#endif
406		pciide_mapreg_dma(sc, pa);
407	aprint_verbose("\n");
408
409	/*
410	 * XXX Configure LEDs to show activity.
411	 */
412
413	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
414	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
415	if (sc->sc_dma_ok) {
416		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
417		sc->sc_wdcdev.irqack = pciide_irqack;
418		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
419		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
420	}
421	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
422
423	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
424	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
425
426	wdc_allocate_regs(&sc->sc_wdcdev);
427
428	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
429	     channel++) {
430		cp = &sc->pciide_channels[channel];
431		if (pciide_chansetup(sc, channel, interface) == 0)
432			continue;
433		pciide_mapchan(pa, cp, interface, pciide_pci_intr);
434	}
435}
436