agpreg.h revision 1.6
1/* $NetBSD: agpreg.h,v 1.6 2003/07/20 18:56:32 hannken Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 29 */ 30 31#ifndef _PCI_AGPREG_H_ 32#define _PCI_AGPREG_H_ 33 34/* 35 * Offsets for various AGP configuration registers. 36 */ 37#define AGP_APBASE 0x10 38 39/* 40 * Offsets from the AGP Capability pointer. 41 */ 42#define AGP_CAPID 0xa0 43#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 44#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 45#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 46#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 47 48#define AGP_STATUS 0x4 49#define AGP_COMMAND 0x8 50 51/* 52 * Config registers for Intel AGP chipsets. 53 */ 54/* i845/855PM */ 55#define AGP_I845_AGPMISC 0x51 56# define AGPMISC_AAGN (1U << 1) /* Aperture AccessEN */ 57 58/* i840/850/850E */ 59#define AGP_I840_MCHCFG 0x50 60# define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 61 62/* i82443LX/BX/GX */ 63#define AGP_INTEL_NBXCFG 0x50 64# define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 65# define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 66 67/* Error Status for i8XX Chipset */ 68#define AGP_INTEL_I8XX_ERRSTS 0xc8 69 70/* Common register */ 71#define AGP_INTEL_ERRSTS 0x91 /* Not i8XX */ 72#define AGP_INTEL_AGPCMD 0xa8 73# define AGPCMD_SBA (1U << 9) 74# define AGPCMD_AGPEN (1U << 8) 75# define AGPCMD_FWEN (1U << 4) 76# define AGPCMD_RATE_1X (1U << 1) 77# define AGPCMD_RATE_2X (1U << 2) 78# define AGPCMD_RATE_4X (1U << 3) 79 80#define AGP_INTEL_AGPCTRL 0xb0 81# define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 82# define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 83 84#define AGP_INTEL_APSIZE 0xb4 85# define APSIZE_MASK 0x3f 86 87#define AGP_INTEL_ATTBASE 0xb8 88 89/* 90 * Config offsets for VIA AGP chipsets. 91 */ 92#define AGP_VIA_GARTCTRL 0x80 93#define AGP_VIA_APSIZE 0x84 94#define AGP_VIA_ATTBASE 0x88 95 96/* 97 * Config offsets for SiS AGP chipsets. 98 */ 99#define AGP_SIS_ATTBASE 0x90 100#define AGP_SIS_WINCTRL 0x94 101#define AGP_SIS_TLBCTRL 0x97 102#define AGP_SIS_TLBFLUSH 0x98 103 104/* 105 * Config offsets for Ali AGP chipsets. 106 */ 107#define AGP_ALI_AGPCTRL 0xb8 108#define AGP_ALI_ATTBASE 0xbc 109#define AGP_ALI_TLBCTRL 0xc0 110 111/* 112 * Config offsets for the AMD 751 chipset. 113 */ 114#define AGP_AMD751_REGISTERS 0x14 115#define AGP_AMD751_APCTRL 0xac 116#define AGP_AMD751_MODECTRL 0xb0 117#define AGP_AMD751_MODECTRL_SYNEN 0x80 118#define AGP_AMD751_MODECTRL2 0xb2 119#define AGP_AMD751_MODECTRL2_G1LM 0x01 120#define AGP_AMD751_MODECTRL2_GPDCE 0x02 121#define AGP_AMD751_MODECTRL2_NGSE 0x08 122 123/* 124 * Memory mapped register offsets for AMD 751 chipset. 125 */ 126#define AGP_AMD751_CAPS 0x00 127#define AGP_AMD751_CAPS_EHI 0x0800 128#define AGP_AMD751_CAPS_P2P 0x0400 129#define AGP_AMD751_CAPS_MPC 0x0200 130#define AGP_AMD751_CAPS_VBE 0x0100 131#define AGP_AMD751_CAPS_REV 0x00ff 132#define AGP_AMD751_STATUS 0x02 133#define AGP_AMD751_STATUS_P2PS 0x0800 134#define AGP_AMD751_STATUS_GCS 0x0400 135#define AGP_AMD751_STATUS_MPS 0x0200 136#define AGP_AMD751_STATUS_VBES 0x0100 137#define AGP_AMD751_STATUS_P2PE 0x0008 138#define AGP_AMD751_STATUS_GCE 0x0004 139#define AGP_AMD751_STATUS_VBEE 0x0001 140#define AGP_AMD751_ATTBASE 0x04 141#define AGP_AMD751_TLBCTRL 0x0c 142 143/* 144 * Config registers for i810 device 0 145 */ 146#define AGP_I810_SMRAM 0x70 147#define AGP_I810_SMRAM_GMS 0xc0 148#define AGP_I810_SMRAM_GMS_DISABLED 0x00 149#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 150#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 151#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 152#define AGP_I810_MISCC 0x72 153#define AGP_I810_MISCC_WINSIZE 0x0001 154#define AGP_I810_MISCC_WINSIZE_64 0x0000 155#define AGP_I810_MISCC_WINSIZE_32 0x0001 156#define AGP_I810_MISCC_PLCK 0x0008 157#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 158#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 159#define AGP_I810_MISCC_WPTC 0x0030 160#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 161#define AGP_I810_MISCC_WPTC_62 0x0010 162#define AGP_I810_MISCC_WPTC_50 0x0020 163#define AGP_I810_MISCC_WPTC_37 0x0030 164#define AGP_I810_MISCC_RPTC 0x00c0 165#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 166#define AGP_I810_MISCC_RPTC_62 0x0040 167#define AGP_I810_MISCC_RPTC_50 0x0080 168#define AGP_I810_MISCC_RPTC_37 0x00c0 169 170/* 171 * Config registers for i810 device 1 172 */ 173#define AGP_I810_GMADR 0x10 174#define AGP_I810_MMADR 0x14 175 176/* 177 * Memory mapped register offsets for i810 chipset. 178 */ 179#define AGP_I810_PGTBL_CTL 0x2020 180#define AGP_I810_DRT 0x3000 181#define AGP_I810_DRT_UNPOPULATED 0x00 182#define AGP_I810_DRT_POPULATED 0x01 183#define AGP_I810_GTT 0x10000 184 185/* 186 * Config registers for i830MG device 0 187 */ 188#define AGP_I830_GCC0 0x50 189#define AGP_I830_GCC1 0x52 190#define AGP_I830_GCC1_DEV2 0x08 191#define AGP_I830_GCC1_DEV2_ENABLED 0x00 192#define AGP_I830_GCC1_DEV2_DISABLED 0x08 193#define AGP_I830_GCC1_GMS 0x70 194#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 195#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 196#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 197#define AGP_I830_GCC1_GMASIZE 0x01 198#define AGP_I830_GCC1_GMASIZE_64 0x01 199#define AGP_I830_GCC1_GMASIZE_128 0x00 200 201 202/* 203 * Config registers for 852GM/855GM/865G device 0 204 */ 205#define AGP_I855_GCC1 0x52 206#define AGP_I855_GCC1_DEV2 0x08 207#define AGP_I855_GCC1_DEV2_ENABLED 0x00 208#define AGP_I855_GCC1_DEV2_DISABLED 0x08 209#define AGP_I855_GCC1_GMS 0x70 210#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 211#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 212#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 213#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 214#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 215#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 216 217#endif /* !_PCI_AGPREG_H_ */ 218