1/* $NetBSD: agpreg.h,v 1.24 2017/02/27 14:13:56 msaitoh Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Doug Rabson 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 29 */ 30 31#ifndef _PCI_AGPREG_H_ 32#define _PCI_AGPREG_H_ 33 34/* 35 * Offsets for various AGP configuration registers. 36 */ 37#define AGP_APBASE 0x10 38 39/* 40 * Config registers for Intel AGP chipsets. 41 */ 42/* i845/855PM */ 43#define AGP_I845_AGPMISC 0x51 44# define AGPMISC_AAGN (1U << 1) /* Aperture AccessEN */ 45 46/* i840/850/850E */ 47#define AGP_I840_MCHCFG 0x50 48# define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 49 50/* i82443LX/BX/GX */ 51#define AGP_INTEL_NBXCFG 0x50 52# define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 53# define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 54 55/* Error Status for i8XX Chipset */ 56#define AGP_INTEL_I8XX_ERRSTS 0xc8 57 58/* Common register */ 59#define AGP_INTEL_ERRSTS 0x90 /* bytes at 0x91 and 0x92, not i8XX */ 60#define AGP_INTEL_AGPCMD 0xa8 61# define AGPCMD_SBA (1U << 9) 62# define AGPCMD_AGPEN (1U << 8) 63# define AGPCMD_FWEN (1U << 4) 64# define AGPCMD_RATE_1X (1U << 1) 65# define AGPCMD_RATE_2X (1U << 2) 66# define AGPCMD_RATE_4X (1U << 3) 67 68#define AGP_INTEL_AGPCTRL 0xb0 69# define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 70# define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 71 72#define AGP_INTEL_APSIZE 0xb4 73# define APSIZE_MASK 0x3f 74 75#define AGP_INTEL_ATTBASE 0xb8 76 77/* 78 * Config offsets for VIA AGP 2.x chipsets. 79 */ 80#define AGP_VIA_GARTCTRL 0x80 81#define AGP_VIA_APSIZE 0x84 82#define AGP_VIA_ATTBASE 0x88 83 84/* 85 * Config offsets for VIA AGP 3.0 chipsets. 86 */ 87#define AGP3_VIA_GARTCTRL 0x90 88#define AGP3_VIA_APSIZE 0x94 89#define AGP3_VIA_ATTBASE 0x98 90#define AGP_VIA_AGPSEL 0xfc 91 92/* 93 * Config offsets for SiS AGP chipsets. 94 */ 95#define AGP_SIS_ATTBASE 0x90 96#define AGP_SIS_WINCTRL 0x94 97#define AGP_SIS_TLBCTRL 0x97 98#define AGP_SIS_TLBFLUSH 0x98 99 100/* 101 * Config offsets for Ali AGP chipsets. 102 */ 103#define AGP_ALI_AGPCTRL 0xb8 104#define AGP_ALI_ATTBASE 0xbc 105#define AGP_ALI_TLBCTRL 0xc0 106 107/* 108 * Config offsets for the AMD 751 chipset. 109 */ 110#define AGP_AMD751_REGISTERS 0x14 111#define AGP_AMD751_APCTRL 0xac 112#define AGP_AMD751_MODECTRL 0xb0 113#define AGP_AMD751_MODECTRL_SYNEN 0x80 114#define AGP_AMD751_MODECTRL2 0xb2 115#define AGP_AMD751_MODECTRL2_G1LM 0x01 116#define AGP_AMD751_MODECTRL2_GPDCE 0x02 117#define AGP_AMD751_MODECTRL2_NGSE 0x08 118 119/* 120 * Memory mapped register offsets for AMD 751 chipset. 121 */ 122#define AGP_AMD751_CAPS 0x00 123#define AGP_AMD751_CAPS_EHI 0x0800 124#define AGP_AMD751_CAPS_P2P 0x0400 125#define AGP_AMD751_CAPS_MPC 0x0200 126#define AGP_AMD751_CAPS_VBE 0x0100 127#define AGP_AMD751_CAPS_REV 0x00ff 128#define AGP_AMD751_STATUS 0x02 129#define AGP_AMD751_STATUS_P2PS 0x0800 130#define AGP_AMD751_STATUS_GCS 0x0400 131#define AGP_AMD751_STATUS_MPS 0x0200 132#define AGP_AMD751_STATUS_VBES 0x0100 133#define AGP_AMD751_STATUS_P2PE 0x0008 134#define AGP_AMD751_STATUS_GCE 0x0004 135#define AGP_AMD751_STATUS_VBEE 0x0001 136#define AGP_AMD751_ATTBASE 0x04 137#define AGP_AMD751_TLBCTRL 0x0c 138 139/* 140 * Config registers for i810 device 0 141 */ 142#define AGP_I810_SMRAM 0x70 143#define AGP_I810_SMRAM_GMS 0xc0 144#define AGP_I810_SMRAM_GMS_DISABLED 0x00 145#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 146#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 147#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 148#define AGP_I810_MISCC 0x72 149#define AGP_I810_MISCC_WINSIZE 0x0001 150#define AGP_I810_MISCC_WINSIZE_64 0x0000 151#define AGP_I810_MISCC_WINSIZE_32 0x0001 152#define AGP_I810_MISCC_PLCK 0x0008 153#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 154#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 155#define AGP_I810_MISCC_WPTC 0x0030 156#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 157#define AGP_I810_MISCC_WPTC_62 0x0010 158#define AGP_I810_MISCC_WPTC_50 0x0020 159#define AGP_I810_MISCC_WPTC_37 0x0030 160#define AGP_I810_MISCC_RPTC 0x00c0 161#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 162#define AGP_I810_MISCC_RPTC_62 0x0040 163#define AGP_I810_MISCC_RPTC_50 0x0080 164#define AGP_I810_MISCC_RPTC_37 0x00c0 165 166/* 167 * Config registers for i810 device 1 168 */ 169#define AGP_I810_GMADR 0x10 170#define AGP_I810_MMADR 0x14 171 172/* 173 * Memory mapped register offsets for i810 chipset. 174 */ 175#define AGP_I810_PGTBL_CTL 0x2020 176 177/** 178 * This field determines the actual size of the global GTT on the 965 179 * and G33 180 */ 181#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 182#define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 183#define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 184#define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 185#define AGP_I810_DRT 0x3000 186#define AGP_I810_DRT_UNPOPULATED 0x00 187#define AGP_I810_DRT_POPULATED 0x01 188#define AGP_I810_GTT 0x10000 189 190/* 191 * Config registers for i830MG device 0 192 */ 193#define AGP_I830_GCC0 0x50 194#define AGP_I830_GCC1 0x52 195#define AGP_I830_GCC1_DEV2 0x08 196#define AGP_I830_GCC1_DEV2_ENABLED 0x00 197#define AGP_I830_GCC1_DEV2_DISABLED 0x08 198#define AGP_I830_GCC1_GMS 0x70 199#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 200#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 201#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 202#define AGP_I830_GCC1_GMASIZE 0x01 203#define AGP_I830_GCC1_GMASIZE_64 0x01 204#define AGP_I830_GCC1_GMASIZE_128 0x00 205 206/* 207 * Memory mapped register offsets for i830 chipset. 208 */ 209#define AGP_I830_HIC 0x70 210 211/* 212 * Config registers for 852GM/855GM/865G device 0 213 */ 214#define AGP_I855_GCC1 0x50 /* upper word */ 215#define AGP_I855_GCC1_DEV2 0x08 216#define AGP_I855_GCC1_DEV2_ENABLED 0x00 217#define AGP_I855_GCC1_DEV2_DISABLED 0x08 218#define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 219#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 220#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 221#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 222#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 223#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 224#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 225 226/* 227 * Config registers for 915G/915GM 228 */ 229#define AGP_I915_MMADR 0x10 230#define AGP_I915_GMADR 0x18 231#define AGP_I915_GTTADR 0x1c 232#define AGP_I915_MSAC 0x60 /* upper word */ 233#define AGP_I915_MSAC_APER_128M 0x02 234 235/* 236 * Config registers for 915G/915GM device 0 237 */ 238#define AGP_I915_GCC1 0x52 239#define AGP_I915_GCC1_GMS 0x70 240#define AGP_I915_GCC1_GMS_STOLEN_0M 0x00 241#define AGP_I915_GCC1_GMS_STOLEN_1M 0x10 242#define AGP_I915_GCC1_GMS_STOLEN_8M 0x30 243#define AGP_I915_GCC1_GMS_STOLEN_16M 0x40 244#define AGP_I915_GCC1_GMS_STOLEN_32M 0x50 245#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 246#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 247#define AGP_I915_IFPADDR 0x60 248 249/* 250 * Config registers for 965G/965Q 251 */ 252#define AGP_I965_MMADR 0x10 253#define AGP_I965_GMADR 0x18 254 255#define AGP_I965_GTT (512*1024) 256 257#define AGP_I965_PGTBL_SIZE_1MB (3 << 1) 258#define AGP_I965_PGTBL_SIZE_2MB (4 << 1) 259#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1) 260 261/* 262 * Config registers for 965G/965Q device 0 263 */ 264#define AGP_I965_IFPADDR 0x70 265 266/* 267 * Config registers for G33 268 */ 269#define AGP_G33_PGTBL_SIZE_MASK (3U << 8) 270#define AGP_G33_PGTBL_SIZE_1M (1U << 8) 271#define AGP_G33_PGTBL_SIZE_2M (2U << 8) 272 273#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 274#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 275 276/* 277 * Config registers for G4X 278 */ 279#define AGP_G4X_MSAC 0x64 /* upper word */ 280#define AGP_G4X_MSAC_MASK 0xff 281#define AGP_G4X_MSAC_APER_256M 0x02 282#define AGP_G4X_MSAC_APER_512M 0x04 283 284#define AGP_G4X_GTT (2*1024*1024) 285 286#define AGP_G4X_PGTBL_SIZE_MASK 0x0000000e 287#define AGP_G4X_PGTBL_SIZE_512K (0 << 1) 288#define AGP_G4X_PGTBL_SIZE_256K (1 << 1) 289#define AGP_G4X_PGTBL_SIZE_128K (2 << 1) 290#define AGP_G4X_PGTBL_SIZE_1M (3 << 1) 291#define AGP_G4X_PGTBL_SIZE_2M (4 << 1) 292#define AGP_G4X_PGTBL_SIZE_1_5M (5 << 1) 293 294#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0 295#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0 296#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0 297#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0 298 299/* 300 * Config registers for Pineview 301 */ 302#define AGP_PINEVIEW_PGTBL_SIZE_MASK (3U << 8) 303#define AGP_PINEVIEW_PGTBL_SIZE_1M (1U << 8) 304 305/* 306 * AMD64 GART registers 307 */ 308#define AGP_AMD64_APCTRL 0x90 309#define AGP_AMD64_APBASE 0x94 310#define AGP_AMD64_ATTBASE 0x98 311#define AGP_AMD64_CACHECTRL 0x9c 312#define AGP_AMD64_APCTRL_GARTEN 0x00000001 313#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e 314#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 315#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 316#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 317#define AGP_AMD64_APBASE_MASK 0x00007fff 318#define AGP_AMD64_ATTBASE_MASK 0xfffffff0 319#define AGP_AMD64_CACHECTRL_INVGART 0x00000001 320#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002 321 322/* 323 * NVIDIA nForce3 registers 324 */ 325#define AGP_AMD64_NVIDIA_0_APBASE 0x10 326#define AGP_AMD64_NVIDIA_1_APBASE1 0x50 327#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54 328#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8 329#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8 330#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc 331 332/* 333 * ULi M1689 registers 334 */ 335#define AGP_AMD64_ULI_APBASE 0x10 336#define AGP_AMD64_ULI_HTT_FEATURE 0x50 337#define AGP_AMD64_ULI_ENU_SCR 0x54 338 339#endif /* !_PCI_AGPREG_H_ */ 340