1/*	$NetBSD: rcvbundl.h,v 1.5 2024/02/02 22:00:33 andvar Exp $	*/
2
3/*
4Copyright (c) 1999-2001, Intel Corporation
5
6All rights reserved.
7
8Redistribution and use in source and binary forms, with or without
9modification, are permitted provided that the following conditions are met:
10
11 1. Redistributions of source code must retain the above copyright notice,
12    this list of conditions and the following disclaimer.
13
14 2. Redistributions in binary form must reproduce the above copyright notice,
15    this list of conditions and the following disclaimer in the documentation
16    and/or other materials provided with the distribution.
17
18 3. Neither the name of Intel Corporation nor the names of its contributors
19    may be used to endorse or promote products derived from this software
20    without specific prior written permission.
21
22THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
23AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
28PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
29LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
30NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
31EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*/
33/*
34rcvbundl.h
35
36Author:  Patrick J Luhmann (PJL)
37Date:    05/30/2000
38Version: 3.28
39
40This file contains the loadable micro code arrays to implement receive bundling on the
41D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step,
42D102 B-step with TCO work around and D012 C-step.
43
44Each controller has its own specific micro code array.  The array for one controller
45is totally incompatible with any other controller, and if used will most likely
46cause the controller to lock up and stop responding to the driver.  Each micro
47code array has its own parameter offsets (described below), and they each have
48their own version number (which should not be confused with the version of the
49rcvbundl.h file given above).
50
51*/
52
53/*  Size of loadable micro code image for each supported chip.  */
54#ifndef D100_NUM_MICROCODE_DWORDS
55#define     D100_NUM_MICROCODE_DWORDS    66
56#endif
57#ifndef D101_NUM_MICROCODE_DWORDS
58#define     D101_NUM_MICROCODE_DWORDS    102
59#endif
60#ifndef D101M_NUM_MICROCODE_DWORDS
61#define     D101M_NUM_MICROCODE_DWORDS   134
62#endif
63#ifndef D101S_NUM_MICROCODE_DWORDS
64#define     D101S_NUM_MICROCODE_DWORDS   134
65#endif
66#ifndef D102_NUM_MICROCODE_DWORDS
67#define     D102_NUM_MICROCODE_DWORDS    134
68#endif
69#ifndef D102_NUM_TCO_MICROCODE_DWORDS
70#define     D102_NUM_TCO_MICROCODE_DWORDS    134
71#endif
72
73
74/*************************************************************************
75*  CPUSaver parameters
76*
77*  All CPUSaver parameters are 16-bit literals that are part of a
78*  "move immediate value" instruction.  By changing the value of
79*  the literal in the instruction before the code is loaded, the
80*  driver can change algorithm.
81*
82*  CPUSAVER_DWORD - This is the location of the instruction that loads
83*    the dead-man timer with its initial value.  By writing a 16-bit
84*    value to the low word of this instruction, the driver can change
85*    the timer value.  The current default is either x600 or x800;
86*    experiments show that the value probably should stay within the
87*    range of x200 - x1000.
88*
89*  CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction
90*    that sets the maximum number of frames that will be bundled.  In
91*    some situations, such as the TCP windowing algorithm, it may be
92*    better to limit the growth of the bundle size than let it go as
93*    high as it can, because that could cause too much added latency.
94*    The default is six, because this is the number of packets in the
95*    default TCP window size.  A value of 1 would make CPUSaver indicate
96*    an interrupt for every frame received.  If you do not want to put
97*    a limit on the bundle size, set this value to xFFFF.
98*
99*  CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction
100*    that contains a bit-mask describing the minimum size frame that
101*    will be bundled.  The default masks the lower 7 bits, which means
102*    that any frame less than 128 bytes in length will not be bundled,
103*    but will instead immediately generate an interrupt.  This does
104*    not affect the current bundle in any way.  Any frame that is 128
105*    bytes or large will be bundled normally.  This feature is meant
106*    to provide immediate indication of ACK frames in a TCP environment.
107*    Customers were seeing poor performance when a machine with CPUSaver
108*    enabled was sending but not receiving.  The delay introduced when
109*    the ACKs were received was enough to reduce total throughput, because
110*    the sender would sit idle until the ACK was finally seen.
111*
112*    The current default is 0xFF80, which masks out the lower 7 bits.
113*    This means that any frame which is x7F (127) bytes or smaller
114*    will cause an immediate interrupt.  Because this value must be a
115*    bit mask, there are only a few valid values that can be used.  To
116*    turn this feature off, the driver can write the value xFFFF to the
117*    lower word of this instruction (in the same way that the other
118*    parameters are used).  Likewise, a value of 0xF800 (2047) would
119*    cause an interrupt to be generated for every frame, because all
120*    standard Ethernet frames are <= 2047 bytes in length.
121*************************************************************************/
122
123
124
125/********************************************************/
126/*  CPUSaver micro code for the D101A                   */
127/********************************************************/
128
129/*  Version 2.0  */
130
131/*  This value is the same for both A and B step of 558.  */
132#define D101_CPUSAVER_DWORD         72
133
134
135#define     D101_A_RCVBUNDLE_UCODE \
136{\
1370x03B301BB, \
1380x0046FFFF, \
1390xFFFFFFFF, \
1400x051DFFFF, \
1410xFFFFFFFF, \
1420xFFFFFFFF, \
1430x000C0001, \
1440x00101212, \
1450x000C0008, \
1460x003801BC, \
1470x00000000, \
1480x00124818, \
1490x000C1000, \
1500x00220809, \
1510x00010200, \
1520x00124818, \
1530x000CFFFC, \
1540x003803B5, \
1550x00000000, \
1560x00000000, \
1570x00000000, \
1580x00000000, \
1590x0010009C, \
1600x0024B81D, \
1610x00130836, \
1620x000C0001, \
1630x0026081C, \
1640x0020C81B, \
1650x00130824, \
1660x00222819, \
1670x00101213, \
1680x00041000, \
1690x003A03B3, \
1700x00010200, \
1710x00101B13, \
1720x00238081, \
1730x00213049, \
1740x0038003B, \
1750x00000000, \
1760x00000000, \
1770x00000000, \
1780x00000000, \
1790x00000000, \
1800x00000000, \
1810x00000000, \
1820x00000000, \
1830x00000000, \
1840x00000000, \
1850x00000000, \
1860x00000000, \
1870x00000000, \
1880x00000000, \
1890x00000000, \
1900x00000000, \
1910x0010009C, \
1920x0024B83E, \
1930x00130826, \
1940x000C0001, \
1950x0026083B, \
1960x00010200, \
1970x00134824, \
1980x000C0001, \
1990x00101213, \
2000x00041000, \
2010x0038051E, \
2020x00101313, \
2030x00010400, \
2040x00380521, \
2050x00050600, \
2060x00100824, \
2070x00101310, \
2080x00041000, \
2090x00080600, \
2100x00101B10, \
2110x0038051E, \
2120x00000000, \
2130x00000000, \
2140x00000000, \
2150x00000000, \
2160x00000000, \
2170x00000000, \
2180x00000000, \
2190x00000000, \
2200x00000000, \
2210x00000000, \
2220x00000000, \
2230x00000000, \
2240x00000000, \
2250x00000000, \
2260x00000000, \
2270x00000000, \
2280x00000000, \
2290x00000000, \
2300x00000000, \
2310x00000000, \
2320x00000000, \
2330x00000000, \
2340x00000000, \
2350x00000000, \
2360x00000000, \
2370x00000000, \
2380x00000000, \
239}
240
241
242/********************************************************/
243/*  CPUSaver micro code for the D101B                   */
244/********************************************************/
245
246/*  Version 2.0  */
247
248#define     D101_B0_RCVBUNDLE_UCODE \
249{\
2500x03B401BC, \
2510x0047FFFF, \
2520xFFFFFFFF, \
2530x051EFFFF, \
2540xFFFFFFFF, \
2550xFFFFFFFF, \
2560x000C0001, \
2570x00101B92, \
2580x000C0008, \
2590x003801BD, \
2600x00000000, \
2610x00124818, \
2620x000C1000, \
2630x00220809, \
2640x00010200, \
2650x00124818, \
2660x000CFFFC, \
2670x003803B6, \
2680x00000000, \
2690x00000000, \
2700x00000000, \
2710x00000000, \
2720x0010009C, \
2730x0024B81D, \
2740x0013082F, \
2750x000C0001, \
2760x0026081C, \
2770x0020C81B, \
2780x00130837, \
2790x00222819, \
2800x00101B93, \
2810x00041000, \
2820x003A03B4, \
2830x00010200, \
2840x00101793, \
2850x00238082, \
2860x0021304A, \
2870x0038003C, \
2880x00000000, \
2890x00000000, \
2900x00000000, \
2910x00000000, \
2920x00000000, \
2930x00000000, \
2940x00000000, \
2950x00000000, \
2960x00000000, \
2970x00000000, \
2980x00000000, \
2990x00000000, \
3000x00000000, \
3010x00000000, \
3020x00000000, \
3030x00000000, \
3040x0010009C, \
3050x0024B83E, \
3060x00130826, \
3070x000C0001, \
3080x0026083B, \
3090x00010200, \
3100x00134837, \
3110x000C0001, \
3120x00101B93, \
3130x00041000, \
3140x0038051F, \
3150x00101313, \
3160x00010400, \
3170x00380522, \
3180x00050600, \
3190x00100837, \
3200x00101310, \
3210x00041000, \
3220x00080600, \
3230x00101790, \
3240x0038051F, \
3250x00000000, \
3260x00000000, \
3270x00000000, \
3280x00000000, \
3290x00000000, \
3300x00000000, \
3310x00000000, \
3320x00000000, \
3330x00000000, \
3340x00000000, \
3350x00000000, \
3360x00000000, \
3370x00000000, \
3380x00000000, \
3390x00000000, \
3400x00000000, \
3410x00000000, \
3420x00000000, \
3430x00000000, \
3440x00000000, \
3450x00000000, \
3460x00000000, \
3470x00000000, \
3480x00000000, \
3490x00000000, \
3500x00000000, \
3510x00000000, \
352}
353
354
355/********************************************************/
356/*  CPUSaver micro code for the D101M (B-step only)     */
357/********************************************************/
358
359/*  Version 2.10  */
360
361/*  Parameter values for the D101M B-step  */
362#define D101M_CPUSAVER_DWORD                78
363#define D101M_CPUSAVER_BUNDLE_MAX_DWORD     65
364#define D101M_CPUSAVER_MIN_SIZE_DWORD       126
365
366
367#define D101M_B_RCVBUNDLE_UCODE \
368{\
3690x00550215, \
3700xFFFF0437, \
3710xFFFFFFFF, \
3720x06A70789, \
3730xFFFFFFFF, \
3740x0558FFFF, \
3750x000C0001, \
3760x00101312, \
3770x000C0008, \
3780x00380216, \
3790x0010009C, \
3800x00204056, \
3810x002380CC, \
3820x00380056, \
3830x0010009C, \
3840x00244C0B, \
3850x00000800, \
3860x00124818, \
3870x00380438, \
3880x00000000, \
3890x00140000, \
3900x00380555, \
3910x00308000, \
3920x00100662, \
3930x00100561, \
3940x000E0408, \
3950x00134861, \
3960x000C0002, \
3970x00103093, \
3980x00308000, \
3990x00100624, \
4000x00100561, \
4010x000E0408, \
4020x00100861, \
4030x000C007E, \
4040x00222C21, \
4050x000C0002, \
4060x00103093, \
4070x00380C7A, \
4080x00080000, \
4090x00103090, \
4100x00380C7A, \
4110x00000000, \
4120x00000000, \
4130x00000000, \
4140x00000000, \
4150x0010009C, \
4160x00244C2D, \
4170x00010004, \
4180x00041000, \
4190x003A0437, \
4200x00044010, \
4210x0038078A, \
4220x00000000, \
4230x00100099, \
4240x00206C7A, \
4250x0010009C, \
4260x00244C48, \
4270x00130824, \
4280x000C0001, \
4290x00101213, \
4300x00260C75, \
4310x00041000, \
4320x00010004, \
4330x00130826, \
4340x000C0006, \
4350x002206A8, \
4360x0013C926, \
4370x00101313, \
4380x003806A8, \
4390x00000000, \
4400x00000000, \
4410x00000000, \
4420x00000000, \
4430x00000000, \
4440x00000000, \
4450x00000000, \
4460x00000000, \
4470x00080600, \
4480x00101B10, \
4490x00050004, \
4500x00100826, \
4510x00101210, \
4520x00380C34, \
4530x00000000, \
4540x00000000, \
4550x0021155B, \
4560x00100099, \
4570x00206559, \
4580x0010009C, \
4590x00244559, \
4600x00130836, \
4610x000C0000, \
4620x00220C62, \
4630x000C0001, \
4640x00101B13, \
4650x00229C0E, \
4660x00210C0E, \
4670x00226C0E, \
4680x00216C0E, \
4690x0022FC0E, \
4700x00215C0E, \
4710x00214C0E, \
4720x00380555, \
4730x00010004, \
4740x00041000, \
4750x00278C67, \
4760x00040800, \
4770x00018100, \
4780x003A0437, \
4790x00130826, \
4800x000C0001, \
4810x00220559, \
4820x00101313, \
4830x00380559, \
4840x00000000, \
4850x00000000, \
4860x00000000, \
4870x00000000, \
4880x00000000, \
4890x00000000, \
4900x00000000, \
4910x00000000, \
4920x00130831, \
4930x0010090B, \
4940x00124813, \
4950x000CFF80, \
4960x002606AB, \
4970x00041000, \
4980x003806A8, \
4990x00000000, \
5000x00000000, \
5010x00000000, \
5020x00000000, \
503}
504
505
506/********************************************************/
507/*  CPUSaver micro code for the D101S                   */
508/********************************************************/
509
510/*  Version 1.20  */
511
512/*  Parameter values for the D101S  */
513#define D101S_CPUSAVER_DWORD                78
514#define D101S_CPUSAVER_BUNDLE_MAX_DWORD     67
515#define D101S_CPUSAVER_MIN_SIZE_DWORD       129
516
517
518#define D101S_RCVBUNDLE_UCODE \
519{\
5200x00550242, \
5210xFFFF047E, \
5220xFFFFFFFF, \
5230x06FF0818, \
5240xFFFFFFFF, \
5250x05A6FFFF, \
5260x000C0001, \
5270x00101312, \
5280x000C0008, \
5290x00380243, \
5300x0010009C, \
5310x00204056, \
5320x002380D0, \
5330x00380056, \
5340x0010009C, \
5350x00244F8B, \
5360x00000800, \
5370x00124818, \
5380x0038047F, \
5390x00000000, \
5400x00140000, \
5410x003805A3, \
5420x00308000, \
5430x00100610, \
5440x00100561, \
5450x000E0408, \
5460x00134861, \
5470x000C0002, \
5480x00103093, \
5490x00308000, \
5500x00100624, \
5510x00100561, \
5520x000E0408, \
5530x00100861, \
5540x000C007E, \
5550x00222FA1, \
5560x000C0002, \
5570x00103093, \
5580x00380F90, \
5590x00080000, \
5600x00103090, \
5610x00380F90, \
5620x00000000, \
5630x00000000, \
5640x00000000, \
5650x00000000, \
5660x0010009C, \
5670x00244FAD, \
5680x00010004, \
5690x00041000, \
5700x003A047E, \
5710x00044010, \
5720x00380819, \
5730x00000000, \
5740x00100099, \
5750x00206FFD, \
5760x0010009A, \
5770x0020AFFD, \
5780x0010009C, \
5790x00244FC8, \
5800x00130824, \
5810x000C0001, \
5820x00101213, \
5830x00260FF8, \
5840x00041000, \
5850x00010004, \
5860x00130826, \
5870x000C0006, \
5880x00220700, \
5890x0013C926, \
5900x00101313, \
5910x00380700, \
5920x00000000, \
5930x00000000, \
5940x00000000, \
5950x00000000, \
5960x00000000, \
5970x00000000, \
5980x00080600, \
5990x00101B10, \
6000x00050004, \
6010x00100826, \
6020x00101210, \
6030x00380FB6, \
6040x00000000, \
6050x00000000, \
6060x002115A9, \
6070x00100099, \
6080x002065A7, \
6090x0010009A, \
6100x0020A5A7, \
6110x0010009C, \
6120x002445A7, \
6130x00130836, \
6140x000C0000, \
6150x00220FE4, \
6160x000C0001, \
6170x00101B13, \
6180x00229F8E, \
6190x00210F8E, \
6200x00226F8E, \
6210x00216F8E, \
6220x0022FF8E, \
6230x00215F8E, \
6240x00214F8E, \
6250x003805A3, \
6260x00010004, \
6270x00041000, \
6280x00278FE9, \
6290x00040800, \
6300x00018100, \
6310x003A047E, \
6320x00130826, \
6330x000C0001, \
6340x002205A7, \
6350x00101313, \
6360x003805A7, \
6370x00000000, \
6380x00000000, \
6390x00000000, \
6400x00000000, \
6410x00000000, \
6420x00000000, \
6430x00000000, \
6440x00000000, \
6450x00000000, \
6460x00130831, \
6470x0010090B, \
6480x00124813, \
6490x000CFF80, \
6500x00260703, \
6510x00041000, \
6520x00380700, \
6530x00000000, \
654}
655
656
657/********************************************************/
658/*  CPUSaver micro code for the D102 B-step             */
659/********************************************************/
660
661/*  Version 2.0  */
662
663/*
664    This version of CPUSaver is different from all others in
665    a different way.  It combines the CPUSaver algorithm with
666    fixes for bugs in the B-step hardware (specifically, bugs
667    with Inline Receive).
668    Thus, when CPUSaver is disabled, this micro code image will
669    still need to be loaded.  Before this happens, the hit addresses
670    for the CPUSaver algorithm must be set to 0x1FFFF.  The hit
671    addresses for CPUSaver are (starting with 0, and remember that
672
673*/
674
675/*  Parameter values for the D102 B-step  */
676#define D102_B_CPUSAVER_DWORD                91
677#define D102_B_CPUSAVER_BUNDLE_MAX_DWORD     115
678#define D102_B_CPUSAVER_MIN_SIZE_DWORD       70
679
680
681#define     D102_B_RCVBUNDLE_UCODE \
682{\
6830x006F0276, \
6840x02BF0E93, \
6850x1FFF0ED9, \
6860x0D2508FA, \
6870x04D21FFF, \
6880x0EA10892, \
6890x00300001, \
6900x0140D871, \
6910x00300008, \
6920x00E00277, \
6930x01406C57, \
6940x00816073, \
6950x008700FA, \
6960x00E00070, \
6970x00E00E94, \
6980x00200004, \
6990x01410000, \
7000x014B6F6F, \
7010x0030FFFF, \
7020x01486F72, \
7030x00E81F9B, \
7040x00E00EA3, \
7050x003C0040, \
7060x00380920, \
7070x00C02000, \
7080x0150ED38, \
7090x0150EE39, \
7100x0150EF3A, \
7110x003C0040, \
7120x01506F0D, \
7130x01600E72, \
7140x00380AE0, \
7150x00E002C0, \
7160x00300001, \
7170x014C0000, \
7180x008404DC, \
7190x014C6F72, \
7200x00E01F9D, \
7210x01406C51, \
7220x0080DFC2, \
7230x01406C52, \
7240x00815FC2, \
7250x01406C57, \
7260x00917FD5, \
7270x00E01FE6, \
7280x00000000, \
7290x01406C57, \
7300x00919FAD, \
7310x00038800, \
7320x00300000, \
7330x00E81FF2, \
7340x014D6FC4, \
7350x00E008FB, \
7360x00000000, \
7370x00822D30, \
7380x01406C51, \
7390x0080CD26, \
7400x01406C52, \
7410x00814D26, \
7420x01406C57, \
7430x00916D26, \
7440x014C6FD7, \
7450x00300000, \
7460x00841FDB, \
7470x00300001, \
7480x0140D772, \
7490x00E012B3, \
7500x014C6F91, \
7510x0150710B, \
7520x01496F72, \
7530x0030FF80, \
7540x00940EDD, \
7550x00102000, \
7560x00E00EDA, \
7570x01406C57, \
7580x00917FFD, \
7590x00001000, \
7600x00E01FFD, \
7610x00138800, \
7620x00300001, \
7630x00E81FF2, \
7640x00202500, \
7650x00E81F9B, \
7660x01600EC5, \
7670x00E00893, \
7680x00000000, \
7690x01406CD5, \
7700x0091EEA3, \
7710x00904EA3, \
7720x00901F89, \
7730x00E00EA3, \
7740x00200600, \
7750x0140D76F, \
7760x00138400, \
7770x01406FD8, \
7780x0140D96F, \
7790x00E01FE6, \
7800x00038400, \
7810x00102000, \
7820x00971FE0, \
7830x00101000, \
7840x00050200, \
7850x00E804D2, \
7860x014C6FD8, \
7870x00300001, \
7880x00840D26, \
7890x0140D872, \
7900x00E00D26, \
7910x014C6FD9, \
7920x00300001, \
7930x0140D972, \
7940x00941FBD, \
7950x00102000, \
7960x00038400, \
7970x014C6FD8, \
7980x00300006, \
7990x00840EDA, \
8000x014F71D8, \
8010x0140D872, \
8020x00E00EDA, \
8030x00340020, \
8040x014C6FED, \
8050x01603472, \
8060x016035EE, \
8070x016036EF, \
8080x00300004, \
8090x01611C71, \
8100x00300014, \
8110x00200A00, \
8120x00E810B9, \
8130x00600000, \
8140x01496F50, \
8150x00E004D3, \
8160x00000000, \
817}
818
819
820
821
822/********************************************************/
823/*  TCO micro code for the D102 B-step             */
824/********************************************************/
825
826/*  Version 2.0  */
827
828/*
829    This version is a fix to TCO bug. This version can be loaded instead
830    the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver"
831
832*/
833
834
835#define     D102_B_TCO_UCODE \
836{\
8370x1FFF0ED3, \
8380x02BF0E93, \
8390x1FFF1FFF, \
8400x1FFF08FA, \
8410x1FFF1FFF, \
8420x0EA10892, \
8430x00906ED8, \
8440x01406C55, \
8450x00E00ED4, \
8460x00000000, \
8470x00000000, \
8480x00000000, \
8490x00000000, \
8500x00000000, \
8510x00E00E94, \
8520x00200004, \
8530x01410000, \
8540x014B6F6F, \
8550x0030FFFF, \
8560x01486F72, \
8570x00E81F9B, \
8580x00E00EA3, \
8590x003C0040, \
8600x00380920, \
8610x00C02000, \
8620x0150ED38, \
8630x0150EE39, \
8640x0150EF3A, \
8650x003C0040, \
8660x01506F0D, \
8670x01600E72, \
8680x00380AE0, \
8690x00E002C0, \
8700x00300001, \
8710x014C0000, \
8720x008404DC, \
8730x014C6F72, \
8740x00E01F9D, \
8750x00000000, \
8760x00000000, \
8770x00000000, \
8780x00000000, \
8790x00000000, \
8800x00000000, \
8810x00000000, \
8820x00000000, \
8830x01406C57, \
8840x00919FAD, \
8850x00038800, \
8860x00300000, \
8870x00E81FD5, \
8880x014D6FC4, \
8890x00E008FB, \
8900x00000000, \
8910x00000000, \
8920x00000000, \
8930x00000000, \
8940x00000000, \
8950x00000000, \
8960x00000000, \
8970x00000000, \
8980x00000000, \
8990x00000000, \
9000x00000000, \
9010x00000000, \
9020x00000000, \
9030x00000000, \
9040x00000000, \
9050x00000000, \
9060x00000000, \
9070x00000000, \
9080x00000000, \
9090x00000000, \
9100x00000000, \
9110x00000000, \
9120x00000000, \
9130x00000000, \
9140x00000000, \
9150x00138800, \
9160x00300001, \
9170x00E81FD5, \
9180x00202500, \
9190x00E81F9B, \
9200x01600EC5, \
9210x00E00893, \
9220x00000000, \
9230x01406CD5, \
9240x0091EEA3, \
9250x00904EA3, \
9260x00901F89, \
9270x00E00EA3, \
9280x00340020, \
9290x014C6FED, \
9300x01603472, \
9310x016035EE, \
9320x016036EF, \
9330x00300004, \
9340x01611C71, \
9350x00300014, \
9360x00200A00, \
9370x00E810B9, \
9380x00600000, \
9390x00000000, \
9400x00000000, \
9410x00000000, \
9420x00000000, \
9430x00000000, \
9440x00000000, \
9450x00000000, \
9460x00000000, \
9470x00000000, \
9480x00000000, \
9490x00000000, \
9500x00000000, \
9510x00000000, \
9520x00000000, \
9530x00000000, \
9540x00000000, \
9550x00000000, \
9560x00000000, \
9570x00000000, \
9580x00000000, \
9590x00000000, \
9600x00000000, \
9610x00000000, \
9620x00000000, \
9630x00000000, \
9640x00000000, \
9650x00000000, \
9660x00000000, \
9670x00000000, \
9680x00000000, \
9690x00000000, \
9700x00000000, \
971}
972
973
974
975/********************************************************/
976/*  Micro code for the D102 C-step                      */
977/********************************************************/
978
979/*  Parameter values for the D102 C-step  */
980#define D102_C_CPUSAVER_DWORD                46
981#define D102_C_CPUSAVER_BUNDLE_MAX_DWORD     54
982#define D102_C_CPUSAVER_MIN_SIZE_DWORD      133 /* not implemented */
983
984
985
986
987
988#if 0
989// this uCode include the CPU Saver and the TCO work around
990//for IP fregments.
991#endif
992#define     D102_C_RCVBUNDLE_UCODE \
993{ \
9940x00700279, \
9950x0E6104E2, \
9960x02BF0CAE, \
9970x1519150C, \
9980x1FFF0E5B, \
9990x1FFF1FFF, \
10000x00E014D8, \
10010x00000000, \
10020x00000000, \
10030x00000000, \
10040x00E014DC, \
10050x00000000, \
10060x00000000, \
10070x00000000, \
10080x00E014F4, \
10090x00000000, \
10100x00000000, \
10110x00000000, \
10120x00000000, \
10130x00000000, \
10140x00000000, \
10150x00000000, \
10160x00E014E0, \
10170x00000000, \
10180x00000000, \
10190x00000000, \
10200x00000000, \
10210x00000000, \
10220x00000000, \
10230x00000000, \
10240x00000000, \
10250x00000000, \
10260x00000000, \
10270x00000000, \
10280x00000000, \
10290x00000000, \
10300x00000000, \
10310x00000000, \
10320x00E014E7, \
10330x00000000, \
10340x00000000, \
10350x00000000, \
10360x00141000, \
10370x015D6F0D, \
10380x00E002C0, \
10390x00000000, \
10400x00200600, \
10410x00E0150D, \
10420x00000000, \
10430x00000000, \
10440x00000000, \
10450x00000000, \
10460x00000000, \
10470x00000000, \
10480x00300006, \
10490x00E0151A, \
10500x00000000, \
10510x00000000, \
10520x00000000, \
10530x00000000, \
10540x00000000, \
10550x00000000, \
10560x00000000, \
10570x00000000, \
10580x00000000, \
10590x00000000, \
10600x00000000, \
10610x00000000, \
10620x00000000, \
10630x00000000, \
10640x00906E65, \
10650x00800E60, \
10660x00E00E5D, \
10670x00000000, \
10680x00000000, \
10690x00000000, \
10700x00000000, \
10710x00000000, \
10720x00000000, \
10730x00000000, \
10740x00000000, \
10750x00000000, \
10760x00000000, \
10770x00000000, \
10780x00000000, \
10790x00000000, \
10800x00000000, \
10810x00000000, \
10820x00000000, \
10830x00000000, \
10840x00000000, \
10850x00000000, \
10860x00000000, \
10870x00000000, \
10880x00000000, \
10890x00000000, \
10900x00000000, \
10910x00000000, \
10920x00000000, \
10930x00000000, \
10940x00000000, \
10950x00000000, \
10960x00000000, \
10970x00000000, \
10980x00000000, \
10990x00000000, \
11000x00000000, \
11010x00000000, \
11020x00000000, \
11030x00000000, \
11040x00000000, \
11050x00000000, \
11060x00000000, \
11070x00000000, \
11080x00000000, \
11090x00000000, \
11100x00000000, \
11110x00000000, \
11120x00000000, \
11130x00000000, \
11140x00000000, \
11150x00000000, \
11160x00000000, \
11170x00000000, \
11180x00000000, \
11190x00000000, \
11200x00000000, \
11210x00000000, \
11220x00000000, \
11230x00000000, \
11240x00000000, \
11250x00000000, \
11260x00000000, \
11270x00000000, \
1128}
1129
1130/********************************************************/
1131/*  Micro code for the D102 E-step                      */
1132/********************************************************/
1133
1134/*  Parameter values for the D102 E-step  */
1135#define D102_E_CPUSAVER_DWORD			42
1136#define D102_E_CPUSAVER_BUNDLE_MAX_DWORD	54
1137#define D102_E_CPUSAVER_MIN_SIZE_DWORD		46
1138
1139#define     D102_E_RCVBUNDLE_UCODE \
1140{\
11410x007D028F, \
11420x0E4204F9, \
11430x14ED0C85, \
11440x14FA14E9, \
11450x0EF70E36, \
11460x1FFF1FFF, \
11470x00E014B9, \
11480x00000000, \
11490x00000000, \
11500x00000000, \
11510x00E014BD, \
11520x00000000, \
11530x00000000, \
11540x00000000, \
11550x00E014D5, \
11560x00000000, \
11570x00000000, \
11580x00000000, \
11590x00000000, \
11600x00000000, \
11610x00000000, \
11620x00000000, \
11630x00E014C1, \
11640x00000000, \
11650x00000000, \
11660x00000000, \
11670x00000000, \
11680x00000000, \
11690x00000000, \
11700x00000000, \
11710x00000000, \
11720x00000000, \
11730x00000000, \
11740x00000000, \
11750x00000000, \
11760x00000000, \
11770x00000000, \
11780x00000000, \
11790x00E014C8, \
11800x00000000, \
11810x00000000, \
11820x00000000, \
11830x00200600, \
11840x00E014EE, \
11850x00000000, \
11860x00000000, \
11870x0030FF80, \
11880x00940E46, \
11890x00038200, \
11900x00102000, \
11910x00E00E43, \
11920x00000000, \
11930x00000000, \
11940x00000000, \
11950x00300006, \
11960x00E014FB, \
11970x00000000, \
11980x00000000, \
11990x00000000, \
12000x00000000, \
12010x00000000, \
12020x00000000, \
12030x00000000, \
12040x00000000, \
12050x00000000, \
12060x00000000, \
12070x00000000, \
12080x00000000, \
12090x00000000, \
12100x00000000, \
12110x00906E41, \
12120x00800E3C, \
12130x00E00E39, \
12140x00000000, \
12150x00906EFD, \
12160x00900EFD, \
12170x00E00EF8, \
12180x00000000, \
12190x00000000, \
12200x00000000, \
12210x00000000, \
12220x00000000, \
12230x00000000, \
12240x00000000, \
12250x00000000, \
12260x00000000, \
12270x00000000, \
12280x00000000, \
12290x00000000, \
12300x00000000, \
12310x00000000, \
12320x00000000, \
12330x00000000, \
12340x00000000, \
12350x00000000, \
12360x00000000, \
12370x00000000, \
12380x00000000, \
12390x00000000, \
12400x00000000, \
12410x00000000, \
12420x00000000, \
12430x00000000, \
12440x00000000, \
12450x00000000, \
12460x00000000, \
12470x00000000, \
12480x00000000, \
12490x00000000, \
12500x00000000, \
12510x00000000, \
12520x00000000, \
12530x00000000, \
12540x00000000, \
12550x00000000, \
12560x00000000, \
12570x00000000, \
12580x00000000, \
12590x00000000, \
12600x00000000, \
12610x00000000, \
12620x00000000, \
12630x00000000, \
12640x00000000, \
12650x00000000, \
12660x00000000, \
12670x00000000, \
12680x00000000, \
12690x00000000, \
12700x00000000, \
12710x00000000, \
12720x00000000, \
12730x00000000, \
12740x00000000, \
1275}
1276