if_mvxpe.c revision 1.6
1/* $NetBSD: if_mvxpe.c,v 1.6 2016/02/13 05:44:01 hikaru Exp $ */ 2/* 3 * Copyright (c) 2015 Internet Initiative Japan Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27#include <sys/cdefs.h> 28__KERNEL_RCSID(0, "$NetBSD: if_mvxpe.c,v 1.6 2016/02/13 05:44:01 hikaru Exp $"); 29 30#include "opt_multiprocessor.h" 31 32#include <sys/param.h> 33#include <sys/bus.h> 34#include <sys/callout.h> 35#include <sys/device.h> 36#include <sys/endian.h> 37#include <sys/errno.h> 38#include <sys/evcnt.h> 39#include <sys/kernel.h> 40#include <sys/kmem.h> 41#include <sys/mutex.h> 42#include <sys/sockio.h> 43#include <sys/sysctl.h> 44#include <sys/syslog.h> 45#include <sys/rndsource.h> 46 47#include <net/if.h> 48#include <net/if_ether.h> 49#include <net/if_media.h> 50#include <net/bpf.h> 51 52#include <netinet/in.h> 53#include <netinet/in_systm.h> 54#include <netinet/ip.h> 55 56#include <dev/mii/mii.h> 57#include <dev/mii/miivar.h> 58 59#include <dev/marvell/marvellreg.h> 60#include <dev/marvell/marvellvar.h> 61#include <dev/marvell/mvxpbmvar.h> 62#include <dev/marvell/if_mvxpereg.h> 63#include <dev/marvell/if_mvxpevar.h> 64 65#include "locators.h" 66 67#if BYTE_ORDER == BIG_ENDIAN 68#error "BIG ENDIAN not supported" 69#endif 70 71#ifdef MVXPE_DEBUG 72#define STATIC /* nothing */ 73#else 74#define STATIC static 75#endif 76 77/* autoconf(9) */ 78STATIC int mvxpe_match(device_t, struct cfdata *, void *); 79STATIC void mvxpe_attach(device_t, device_t, void *); 80STATIC int mvxpe_evcnt_attach(struct mvxpe_softc *); 81CFATTACH_DECL_NEW(mvxpe_mbus, sizeof(struct mvxpe_softc), 82 mvxpe_match, mvxpe_attach, NULL, NULL); 83STATIC void mvxpe_sc_lock(struct mvxpe_softc *); 84STATIC void mvxpe_sc_unlock(struct mvxpe_softc *); 85 86/* MII */ 87STATIC int mvxpe_miibus_readreg(device_t, int, int); 88STATIC void mvxpe_miibus_writereg(device_t, int, int, int); 89STATIC void mvxpe_miibus_statchg(struct ifnet *); 90 91/* Addres Decoding Window */ 92STATIC void mvxpe_wininit(struct mvxpe_softc *, enum marvell_tags *); 93 94/* Device Register Initialization */ 95STATIC int mvxpe_initreg(struct ifnet *); 96 97/* Descriptor Ring Control for each of queues */ 98STATIC void *mvxpe_dma_memalloc(struct mvxpe_softc *, bus_dmamap_t *, size_t); 99STATIC int mvxpe_ring_alloc_queue(struct mvxpe_softc *, int); 100STATIC void mvxpe_ring_dealloc_queue(struct mvxpe_softc *, int); 101STATIC void mvxpe_ring_init_queue(struct mvxpe_softc *, int); 102STATIC void mvxpe_ring_flush_queue(struct mvxpe_softc *, int); 103STATIC void mvxpe_ring_sync_rx(struct mvxpe_softc *, int, int, int, int); 104STATIC void mvxpe_ring_sync_tx(struct mvxpe_softc *, int, int, int, int); 105 106/* Rx/Tx Queue Control */ 107STATIC int mvxpe_rx_queue_init(struct ifnet *, int); 108STATIC int mvxpe_tx_queue_init(struct ifnet *, int); 109STATIC int mvxpe_rx_queue_enable(struct ifnet *, int); 110STATIC int mvxpe_tx_queue_enable(struct ifnet *, int); 111STATIC void mvxpe_rx_lockq(struct mvxpe_softc *, int); 112STATIC void mvxpe_rx_unlockq(struct mvxpe_softc *, int); 113STATIC void mvxpe_tx_lockq(struct mvxpe_softc *, int); 114STATIC void mvxpe_tx_unlockq(struct mvxpe_softc *, int); 115 116/* Interrupt Handlers */ 117STATIC void mvxpe_disable_intr(struct mvxpe_softc *); 118STATIC void mvxpe_enable_intr(struct mvxpe_softc *); 119STATIC int mvxpe_rxtxth_intr(void *); 120STATIC int mvxpe_misc_intr(void *); 121STATIC int mvxpe_rxtx_intr(void *); 122STATIC void mvxpe_tick(void *); 123 124/* struct ifnet and mii callbacks*/ 125STATIC void mvxpe_start(struct ifnet *); 126STATIC int mvxpe_ioctl(struct ifnet *, u_long, void *); 127STATIC int mvxpe_init(struct ifnet *); 128STATIC void mvxpe_stop(struct ifnet *, int); 129STATIC void mvxpe_watchdog(struct ifnet *); 130STATIC int mvxpe_ifflags_cb(struct ethercom *); 131STATIC int mvxpe_mediachange(struct ifnet *); 132STATIC void mvxpe_mediastatus(struct ifnet *, struct ifmediareq *); 133 134/* Link State Notify */ 135STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc); 136STATIC void mvxpe_linkup(struct mvxpe_softc *); 137STATIC void mvxpe_linkdown(struct mvxpe_softc *); 138STATIC void mvxpe_linkreset(struct mvxpe_softc *); 139 140/* Tx Subroutines */ 141STATIC int mvxpe_tx_queue_select(struct mvxpe_softc *, struct mbuf *); 142STATIC int mvxpe_tx_queue(struct mvxpe_softc *, struct mbuf *, int); 143STATIC void mvxpe_tx_set_csumflag(struct ifnet *, 144 struct mvxpe_tx_desc *, struct mbuf *); 145STATIC void mvxpe_tx_complete(struct mvxpe_softc *, uint32_t); 146STATIC void mvxpe_tx_queue_complete(struct mvxpe_softc *, int); 147 148/* Rx Subroutines */ 149STATIC void mvxpe_rx(struct mvxpe_softc *, uint32_t); 150STATIC void mvxpe_rx_queue(struct mvxpe_softc *, int, int); 151STATIC int mvxpe_rx_queue_select(struct mvxpe_softc *, uint32_t, int *); 152STATIC void mvxpe_rx_refill(struct mvxpe_softc *, uint32_t); 153STATIC void mvxpe_rx_queue_refill(struct mvxpe_softc *, int); 154STATIC int mvxpe_rx_queue_add(struct mvxpe_softc *, int); 155STATIC void mvxpe_rx_set_csumflag(struct ifnet *, 156 struct mvxpe_rx_desc *, struct mbuf *); 157 158/* MAC address filter */ 159STATIC uint8_t mvxpe_crc8(const uint8_t *, size_t); 160STATIC void mvxpe_filter_setup(struct mvxpe_softc *); 161 162/* sysctl(9) */ 163STATIC int sysctl_read_mib(SYSCTLFN_PROTO); 164STATIC int sysctl_clear_mib(SYSCTLFN_PROTO); 165STATIC int sysctl_set_queue_length(SYSCTLFN_PROTO); 166STATIC int sysctl_set_queue_rxthtime(SYSCTLFN_PROTO); 167STATIC void sysctl_mvxpe_init(struct mvxpe_softc *); 168 169/* MIB */ 170STATIC void mvxpe_clear_mib(struct mvxpe_softc *); 171STATIC void mvxpe_update_mib(struct mvxpe_softc *); 172 173/* for Debug */ 174STATIC void mvxpe_dump_txdesc(struct mvxpe_tx_desc *, int) __attribute__((__unused__)); 175STATIC void mvxpe_dump_rxdesc(struct mvxpe_rx_desc *, int) __attribute__((__unused__)); 176 177STATIC int mvxpe_root_num; 178STATIC kmutex_t mii_mutex; 179STATIC int mii_init = 0; 180#ifdef MVXPE_DEBUG 181STATIC int mvxpe_debug = MVXPE_DEBUG; 182#endif 183 184/* 185 * List of MIB register and names 186 */ 187STATIC struct mvxpe_mib_def { 188 uint32_t regnum; 189 int reg64; 190 const char *sysctl_name; 191 const char *desc; 192} mvxpe_mib_list[] = { 193 {MVXPE_MIB_RX_GOOD_OCT, 1, "rx_good_oct", 194 "Good Octets Rx"}, 195 {MVXPE_MIB_RX_BAD_OCT, 0, "rx_bad_oct", 196 "Bad Octets Rx"}, 197 {MVXPE_MIB_RX_MAC_TRNS_ERR, 0, "rx_mac_err", 198 "MAC Transmit Error"}, 199 {MVXPE_MIB_RX_GOOD_FRAME, 0, "rx_good_frame", 200 "Good Frames Rx"}, 201 {MVXPE_MIB_RX_BAD_FRAME, 0, "rx_bad_frame", 202 "Bad Frames Rx"}, 203 {MVXPE_MIB_RX_BCAST_FRAME, 0, "rx_bcast_frame", 204 "Broadcast Frames Rx"}, 205 {MVXPE_MIB_RX_MCAST_FRAME, 0, "rx_mcast_frame", 206 "Multicast Frames Rx"}, 207 {MVXPE_MIB_RX_FRAME64_OCT, 0, "rx_frame_1_64", 208 "Frame Size 1 - 64"}, 209 {MVXPE_MIB_RX_FRAME127_OCT, 0, "rx_frame_65_127", 210 "Frame Size 65 - 127"}, 211 {MVXPE_MIB_RX_FRAME255_OCT, 0, "rx_frame_128_255", 212 "Frame Size 128 - 255"}, 213 {MVXPE_MIB_RX_FRAME511_OCT, 0, "rx_frame_256_511", 214 "Frame Size 256 - 511"}, 215 {MVXPE_MIB_RX_FRAME1023_OCT, 0, "rx_frame_512_1023", 216 "Frame Size 512 - 1023"}, 217 {MVXPE_MIB_RX_FRAMEMAX_OCT, 0, "rx_fame_1024_max", 218 "Frame Size 1024 - Max"}, 219 {MVXPE_MIB_TX_GOOD_OCT, 1, "tx_good_oct", 220 "Good Octets Tx"}, 221 {MVXPE_MIB_TX_GOOD_FRAME, 0, "tx_good_frame", 222 "Good Frames Tx"}, 223 {MVXPE_MIB_TX_EXCES_COL, 0, "tx_exces_collision", 224 "Excessive Collision"}, 225 {MVXPE_MIB_TX_MCAST_FRAME, 0, "tx_mcast_frame", 226 "Multicast Frames Tx"}, 227 {MVXPE_MIB_TX_BCAST_FRAME, 0, "tx_bcast_frame", 228 "Broadcast Frames Tx"}, 229 {MVXPE_MIB_TX_MAC_CTL_ERR, 0, "tx_mac_err", 230 "Unknown MAC Control"}, 231 {MVXPE_MIB_FC_SENT, 0, "fc_tx", 232 "Flow Control Tx"}, 233 {MVXPE_MIB_FC_GOOD, 0, "fc_rx_good", 234 "Good Flow Control Rx"}, 235 {MVXPE_MIB_FC_BAD, 0, "fc_rx_bad", 236 "Bad Flow Control Rx"}, 237 {MVXPE_MIB_PKT_UNDERSIZE, 0, "pkt_undersize", 238 "Undersized Packets Rx"}, 239 {MVXPE_MIB_PKT_FRAGMENT, 0, "pkt_fragment", 240 "Fragmented Packets Rx"}, 241 {MVXPE_MIB_PKT_OVERSIZE, 0, "pkt_oversize", 242 "Oversized Packets Rx"}, 243 {MVXPE_MIB_PKT_JABBER, 0, "pkt_jabber", 244 "Jabber Packets Rx"}, 245 {MVXPE_MIB_MAC_RX_ERR, 0, "mac_rx_err", 246 "MAC Rx Errors"}, 247 {MVXPE_MIB_MAC_CRC_ERR, 0, "mac_crc_err", 248 "MAC CRC Errors"}, 249 {MVXPE_MIB_MAC_COL, 0, "mac_collision", 250 "MAC Collision"}, 251 {MVXPE_MIB_MAC_LATE_COL, 0, "mac_late_collision", 252 "MAC Late Collision"}, 253}; 254 255/* 256 * autoconf(9) 257 */ 258/* ARGSUSED */ 259STATIC int 260mvxpe_match(device_t parent, cfdata_t match, void *aux) 261{ 262 struct marvell_attach_args *mva = aux; 263 bus_size_t pv_off; 264 uint32_t pv; 265 266 if (strcmp(mva->mva_name, match->cf_name) != 0) 267 return 0; 268 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 269 return 0; 270 271 /* check port version */ 272 pv_off = mva->mva_offset + MVXPE_PV; 273 pv = bus_space_read_4(mva->mva_iot, mva->mva_ioh, pv_off); 274 if (MVXPE_PV_GET_VERSION(pv) < 0x10) 275 return 0; /* old version is not supported */ 276 277 return 1; 278} 279 280/* ARGSUSED */ 281STATIC void 282mvxpe_attach(device_t parent, device_t self, void *aux) 283{ 284 struct mvxpe_softc *sc = device_private(self); 285 struct mii_softc *mii; 286 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 287 struct marvell_attach_args *mva = aux; 288 prop_dictionary_t dict; 289 prop_data_t enaddrp = NULL; 290 uint32_t phyaddr, maddrh, maddrl; 291 uint8_t enaddr[ETHER_ADDR_LEN]; 292 int q; 293 294 aprint_naive("\n"); 295 aprint_normal(": Marvell ARMADA GbE Controller\n"); 296 memset(sc, 0, sizeof(*sc)); 297 sc->sc_dev = self; 298 sc->sc_port = mva->mva_unit; 299 sc->sc_iot = mva->mva_iot; 300 sc->sc_dmat = mva->mva_dmat; 301 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 302 callout_init(&sc->sc_tick_ch, 0); 303 callout_setfunc(&sc->sc_tick_ch, mvxpe_tick, sc); 304 305 /* 306 * BUS space 307 */ 308 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 309 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) { 310 aprint_error_dev(self, "Cannot map registers\n"); 311 goto fail; 312 } 313 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 314 mva->mva_offset + MVXPE_PORTMIB_BASE, MVXPE_PORTMIB_SIZE, 315 &sc->sc_mibh)) { 316 aprint_error_dev(self, 317 "Cannot map destination address filter registers\n"); 318 goto fail; 319 } 320 sc->sc_version = MVXPE_READ(sc, MVXPE_PV); 321 aprint_normal_dev(self, "Port Version %#x\n", sc->sc_version); 322 323 /* 324 * Buffer Manager(BM) subsystem. 325 */ 326 sc->sc_bm = mvxpbm_device(mva); 327 if (sc->sc_bm == NULL) { 328 aprint_error_dev(self, "no Buffer Manager.\n"); 329 goto fail; 330 } 331 aprint_normal_dev(self, 332 "Using Buffer Manager: %s\n", mvxpbm_xname(sc->sc_bm)); 333 aprint_normal_dev(sc->sc_dev, 334 "%zu kbytes managed buffer, %zu bytes * %u entries allocated.\n", 335 mvxpbm_buf_size(sc->sc_bm) / 1024, 336 mvxpbm_chunk_size(sc->sc_bm), mvxpbm_chunk_count(sc->sc_bm)); 337 338 /* 339 * make sure DMA engines are in reset state 340 */ 341 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 342 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 343 344 /* 345 * Address decoding window 346 */ 347 mvxpe_wininit(sc, mva->mva_tags); 348 349 /* 350 * MAC address 351 */ 352 dict = device_properties(self); 353 if (dict) 354 enaddrp = prop_dictionary_get(dict, "mac-address"); 355 if (enaddrp) { 356 memcpy(enaddr, prop_data_data_nocopy(enaddrp), ETHER_ADDR_LEN); 357 maddrh = enaddr[0] << 24; 358 maddrh |= enaddr[1] << 16; 359 maddrh |= enaddr[2] << 8; 360 maddrh |= enaddr[3]; 361 maddrl = enaddr[4] << 8; 362 maddrl |= enaddr[5]; 363 MVXPE_WRITE(sc, MVXPE_MACAH, maddrh); 364 MVXPE_WRITE(sc, MVXPE_MACAL, maddrl); 365 } 366 else { 367 /* 368 * even if enaddr is not found in dictionary, 369 * the port may be initialized by IPL program such as U-BOOT. 370 */ 371 maddrh = MVXPE_READ(sc, MVXPE_MACAH); 372 maddrl = MVXPE_READ(sc, MVXPE_MACAL); 373 if ((maddrh | maddrl) == 0) { 374 aprint_error_dev(self, "No Ethernet address\n"); 375 return; 376 } 377 } 378 sc->sc_enaddr[0] = maddrh >> 24; 379 sc->sc_enaddr[1] = maddrh >> 16; 380 sc->sc_enaddr[2] = maddrh >> 8; 381 sc->sc_enaddr[3] = maddrh >> 0; 382 sc->sc_enaddr[4] = maddrl >> 8; 383 sc->sc_enaddr[5] = maddrl >> 0; 384 aprint_normal_dev(self, "Ethernet address %s\n", 385 ether_sprintf(sc->sc_enaddr)); 386 387 /* 388 * Register interrupt handlers 389 * XXX: handle Ethernet unit intr. and Error intr. 390 */ 391 mvxpe_disable_intr(sc); 392 marvell_intr_establish(mva->mva_irq, IPL_NET, mvxpe_rxtxth_intr, sc); 393 394 /* 395 * MIB buffer allocation 396 */ 397 sc->sc_sysctl_mib_size = 398 __arraycount(mvxpe_mib_list) * sizeof(struct mvxpe_sysctl_mib); 399 sc->sc_sysctl_mib = kmem_alloc(sc->sc_sysctl_mib_size, KM_NOSLEEP); 400 if (sc->sc_sysctl_mib == NULL) 401 goto fail; 402 memset(sc->sc_sysctl_mib, 0, sc->sc_sysctl_mib_size); 403 404 /* 405 * Device DMA Buffer allocation 406 */ 407 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 408 if (mvxpe_ring_alloc_queue(sc, q) != 0) 409 goto fail; 410 mvxpe_ring_init_queue(sc, q); 411 } 412 413 /* 414 * We can support 802.1Q VLAN-sized frames and jumbo 415 * Ethernet frames. 416 */ 417 sc->sc_ethercom.ec_capabilities |= 418 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 419 ifp->if_softc = sc; 420 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 421 ifp->if_start = mvxpe_start; 422 ifp->if_ioctl = mvxpe_ioctl; 423 ifp->if_init = mvxpe_init; 424 ifp->if_stop = mvxpe_stop; 425 ifp->if_watchdog = mvxpe_watchdog; 426 427 /* 428 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 429 */ 430 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx; 431 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx; 432 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 433 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 434 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Tx; 435 ifp->if_capabilities |= IFCAP_CSUM_UDPv4_Rx; 436 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx; 437 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Rx; 438 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Tx; 439 ifp->if_capabilities |= IFCAP_CSUM_UDPv6_Rx; 440 441 /* 442 * Initialize struct ifnet 443 */ 444 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVXPE_TX_RING_CNT - 1, IFQ_MAXLEN)); 445 IFQ_SET_READY(&ifp->if_snd); 446 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), sizeof(ifp->if_xname)); 447 448 /* 449 * Enable DMA engines and Initiazlie Device Regisers. 450 */ 451 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 452 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 453 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 454 mvxpe_sc_lock(sc); /* XXX */ 455 mvxpe_filter_setup(sc); 456 mvxpe_sc_unlock(sc); 457 mvxpe_initreg(ifp); 458 459 /* 460 * Now MAC is working, setup MII. 461 */ 462 if (mii_init == 0) { 463 /* 464 * MII bus is shared by all MACs and all PHYs in SoC. 465 * serializing the bus access should be safe. 466 */ 467 mutex_init(&mii_mutex, MUTEX_DEFAULT, IPL_NET); 468 mii_init = 1; 469 } 470 sc->sc_mii.mii_ifp = ifp; 471 sc->sc_mii.mii_readreg = mvxpe_miibus_readreg; 472 sc->sc_mii.mii_writereg = mvxpe_miibus_writereg; 473 sc->sc_mii.mii_statchg = mvxpe_miibus_statchg; 474 475 sc->sc_ethercom.ec_mii = &sc->sc_mii; 476 ifmedia_init(&sc->sc_mii.mii_media, 0, 477 mvxpe_mediachange, mvxpe_mediastatus); 478 /* 479 * XXX: phy addressing highly depends on Board Design. 480 * we assume phyaddress == MAC unit number here, 481 * but some boards may not. 482 */ 483 mii_attach(self, &sc->sc_mii, 0xffffffff, 484 MII_PHY_ANY, sc->sc_dev->dv_unit, 0); 485 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 486 if (mii == NULL) { 487 aprint_error_dev(self, "no PHY found!\n"); 488 ifmedia_add(&sc->sc_mii.mii_media, 489 IFM_ETHER|IFM_MANUAL, 0, NULL); 490 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 491 } else { 492 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 493 phyaddr = MVXPE_PHYADDR_PHYAD(mii->mii_phy); 494 MVXPE_WRITE(sc, MVXPE_PHYADDR, phyaddr); 495 DPRINTSC(sc, 1, "PHYADDR: %#x\n", MVXPE_READ(sc, MVXPE_PHYADDR)); 496 } 497 498 /* 499 * Call MI attach routines. 500 */ 501 if_attach(ifp); 502 503 ether_ifattach(ifp, sc->sc_enaddr); 504 ether_set_ifflags_cb(&sc->sc_ethercom, mvxpe_ifflags_cb); 505 506 sysctl_mvxpe_init(sc); 507 mvxpe_evcnt_attach(sc); 508 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 509 RND_TYPE_NET, RND_FLAG_DEFAULT); 510 511 return; 512 513fail: 514 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) 515 mvxpe_ring_dealloc_queue(sc, q); 516 if (sc->sc_sysctl_mib) 517 kmem_free(sc->sc_sysctl_mib, sc->sc_sysctl_mib_size); 518 519 return; 520} 521 522STATIC int 523mvxpe_evcnt_attach(struct mvxpe_softc *sc) 524{ 525#ifdef MVXPE_EVENT_COUNTERS 526 int q; 527 528 /* Master Interrupt Handler */ 529 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtxth, EVCNT_TYPE_INTR, 530 NULL, device_xname(sc->sc_dev), "RxTxTH Intr."); 531 evcnt_attach_dynamic(&sc->sc_ev.ev_i_rxtx, EVCNT_TYPE_INTR, 532 NULL, device_xname(sc->sc_dev), "RxTx Intr."); 533 evcnt_attach_dynamic(&sc->sc_ev.ev_i_misc, EVCNT_TYPE_INTR, 534 NULL, device_xname(sc->sc_dev), "MISC Intr."); 535 536 /* RXTXTH Interrupt */ 537 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtxth_txerr, EVCNT_TYPE_INTR, 538 NULL, device_xname(sc->sc_dev), "RxTxTH Tx error summary"); 539 540 /* MISC Interrupt */ 541 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_phystatuschng, EVCNT_TYPE_INTR, 542 NULL, device_xname(sc->sc_dev), "MISC phy status changed"); 543 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_linkchange, EVCNT_TYPE_INTR, 544 NULL, device_xname(sc->sc_dev), "MISC link status changed"); 545 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_iae, EVCNT_TYPE_INTR, 546 NULL, device_xname(sc->sc_dev), "MISC internal address error"); 547 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxoverrun, EVCNT_TYPE_INTR, 548 NULL, device_xname(sc->sc_dev), "MISC Rx FIFO overrun"); 549 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxcrc, EVCNT_TYPE_INTR, 550 NULL, device_xname(sc->sc_dev), "MISC Rx CRC error"); 551 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_rxlargepacket, EVCNT_TYPE_INTR, 552 NULL, device_xname(sc->sc_dev), "MISC Rx too large frame"); 553 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txunderrun, EVCNT_TYPE_INTR, 554 NULL, device_xname(sc->sc_dev), "MISC Tx FIFO underrun"); 555 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_prbserr, EVCNT_TYPE_INTR, 556 NULL, device_xname(sc->sc_dev), "MISC SERDES loopback test err"); 557 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_srse, EVCNT_TYPE_INTR, 558 NULL, device_xname(sc->sc_dev), "MISC SERDES sync error"); 559 evcnt_attach_dynamic(&sc->sc_ev.ev_misc_txreq, EVCNT_TYPE_INTR, 560 NULL, device_xname(sc->sc_dev), "MISC Tx resource erorr"); 561 562 /* RxTx Interrupt */ 563 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rreq, EVCNT_TYPE_INTR, 564 NULL, device_xname(sc->sc_dev), "RxTx Rx resource erorr"); 565 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rpq, EVCNT_TYPE_INTR, 566 NULL, device_xname(sc->sc_dev), "RxTx Rx pakcet"); 567 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_tbrq, EVCNT_TYPE_INTR, 568 NULL, device_xname(sc->sc_dev), "RxTx Tx complete"); 569 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_rxtxth, EVCNT_TYPE_INTR, 570 NULL, device_xname(sc->sc_dev), "RxTx RxTxTH summary"); 571 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_txerr, EVCNT_TYPE_INTR, 572 NULL, device_xname(sc->sc_dev), "RxTx Tx error summary"); 573 evcnt_attach_dynamic(&sc->sc_ev.ev_rxtx_misc, EVCNT_TYPE_INTR, 574 NULL, device_xname(sc->sc_dev), "RxTx MISC summary"); 575 576 /* Link */ 577 evcnt_attach_dynamic(&sc->sc_ev.ev_link_up, EVCNT_TYPE_MISC, 578 NULL, device_xname(sc->sc_dev), "link up"); 579 evcnt_attach_dynamic(&sc->sc_ev.ev_link_down, EVCNT_TYPE_MISC, 580 NULL, device_xname(sc->sc_dev), "link down"); 581 582 /* Rx Descriptor */ 583 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_ce, EVCNT_TYPE_MISC, 584 NULL, device_xname(sc->sc_dev), "Rx CRC error counter"); 585 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_or, EVCNT_TYPE_MISC, 586 NULL, device_xname(sc->sc_dev), "Rx FIFO overrun counter"); 587 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_mf, EVCNT_TYPE_MISC, 588 NULL, device_xname(sc->sc_dev), "Rx too large frame counter"); 589 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_re, EVCNT_TYPE_MISC, 590 NULL, device_xname(sc->sc_dev), "Rx resource error counter"); 591 evcnt_attach_dynamic(&sc->sc_ev.ev_rxd_scat, EVCNT_TYPE_MISC, 592 NULL, device_xname(sc->sc_dev), "Rx unexpected scatter bufs"); 593 594 /* Tx Descriptor */ 595 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_lc, EVCNT_TYPE_MISC, 596 NULL, device_xname(sc->sc_dev), "Tx late collision counter"); 597 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_rl, EVCNT_TYPE_MISC, 598 NULL, device_xname(sc->sc_dev), "Tx excess. collision counter"); 599 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_ur, EVCNT_TYPE_MISC, 600 NULL, device_xname(sc->sc_dev), "Tx FIFO underrun counter"); 601 evcnt_attach_dynamic(&sc->sc_ev.ev_txd_oth, EVCNT_TYPE_MISC, 602 NULL, device_xname(sc->sc_dev), "Tx unkonwn erorr counter"); 603 604 /* Status Registers */ 605 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pdfc, EVCNT_TYPE_MISC, 606 NULL, device_xname(sc->sc_dev), "Rx discard counter"); 607 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_pofc, EVCNT_TYPE_MISC, 608 NULL, device_xname(sc->sc_dev), "Rx overrun counter"); 609 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txbadfcs, EVCNT_TYPE_MISC, 610 NULL, device_xname(sc->sc_dev), "Tx bad FCS counter"); 611 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_txdropped, EVCNT_TYPE_MISC, 612 NULL, device_xname(sc->sc_dev), "Tx dorpped counter"); 613 evcnt_attach_dynamic(&sc->sc_ev.ev_reg_lpic, EVCNT_TYPE_MISC, 614 NULL, device_xname(sc->sc_dev), "LP_IDLE counter"); 615 616 /* Device Driver Errors */ 617 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_wdogsoft, EVCNT_TYPE_MISC, 618 NULL, device_xname(sc->sc_dev), "watchdog timer expired"); 619 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txerr, EVCNT_TYPE_MISC, 620 NULL, device_xname(sc->sc_dev), "Tx descriptor alloc failed"); 621#define MVXPE_QUEUE_DESC(q) "Rx success in queue " # q 622 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 623 static const char *rxq_desc[] = { 624 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 625 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 626 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 627 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 628 }; 629 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxq[q], EVCNT_TYPE_MISC, 630 NULL, device_xname(sc->sc_dev), rxq_desc[q]); 631 } 632#undef MVXPE_QUEUE_DESC 633#define MVXPE_QUEUE_DESC(q) "Tx success in queue " # q 634 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 635 static const char *txq_desc[] = { 636 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 637 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 638 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 639 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 640 }; 641 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txq[q], EVCNT_TYPE_MISC, 642 NULL, device_xname(sc->sc_dev), txq_desc[q]); 643 } 644#undef MVXPE_QUEUE_DESC 645#define MVXPE_QUEUE_DESC(q) "Rx error in queue " # q 646 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 647 static const char *rxqe_desc[] = { 648 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 649 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 650 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 651 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 652 }; 653 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_rxqe[q], EVCNT_TYPE_MISC, 654 NULL, device_xname(sc->sc_dev), rxqe_desc[q]); 655 } 656#undef MVXPE_QUEUE_DESC 657#define MVXPE_QUEUE_DESC(q) "Tx error in queue " # q 658 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 659 static const char *txqe_desc[] = { 660 MVXPE_QUEUE_DESC(0), MVXPE_QUEUE_DESC(1), 661 MVXPE_QUEUE_DESC(2), MVXPE_QUEUE_DESC(3), 662 MVXPE_QUEUE_DESC(4), MVXPE_QUEUE_DESC(5), 663 MVXPE_QUEUE_DESC(6), MVXPE_QUEUE_DESC(7), 664 }; 665 evcnt_attach_dynamic(&sc->sc_ev.ev_drv_txqe[q], EVCNT_TYPE_MISC, 666 NULL, device_xname(sc->sc_dev), txqe_desc[q]); 667 } 668#undef MVXPE_QUEUE_DESC 669 670#endif /* MVXPE_EVENT_COUNTERS */ 671 return 0; 672} 673 674STATIC void 675mvxpe_sc_lock(struct mvxpe_softc *sc) 676{ 677 mutex_enter(&sc->sc_mtx); 678} 679 680STATIC void 681mvxpe_sc_unlock(struct mvxpe_softc *sc) 682{ 683 mutex_exit(&sc->sc_mtx); 684} 685 686/* 687 * MII 688 */ 689STATIC int 690mvxpe_miibus_readreg(device_t dev, int phy, int reg) 691{ 692 struct mvxpe_softc *sc = device_private(dev); 693 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 694 uint32_t smi, val; 695 int i; 696 697 mutex_enter(&mii_mutex); 698 699 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 700 DELAY(1); 701 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 702 break; 703 } 704 if (i == MVXPE_PHY_TIMEOUT) { 705 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 706 mutex_exit(&mii_mutex); 707 return -1; 708 } 709 710 smi = 711 MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | MVXPE_SMI_OPCODE_READ; 712 MVXPE_WRITE(sc, MVXPE_SMI, smi); 713 714 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 715 DELAY(1); 716 smi = MVXPE_READ(sc, MVXPE_SMI); 717 if (smi & MVXPE_SMI_READVALID) 718 break; 719 } 720 721 mutex_exit(&mii_mutex); 722 723 DPRINTDEV(dev, 9, "i=%d, timeout=%d\n", i, MVXPE_PHY_TIMEOUT); 724 725 val = smi & MVXPE_SMI_DATA_MASK; 726 727 DPRINTDEV(dev, 9, "phy=%d, reg=%#x, val=%#x\n", phy, reg, val); 728 729 return val; 730} 731 732STATIC void 733mvxpe_miibus_writereg(device_t dev, int phy, int reg, int val) 734{ 735 struct mvxpe_softc *sc = device_private(dev); 736 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 737 uint32_t smi; 738 int i; 739 740 DPRINTDEV(dev, 9, "phy=%d reg=%#x val=%#x\n", phy, reg, val); 741 742 mutex_enter(&mii_mutex); 743 744 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 745 DELAY(1); 746 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 747 break; 748 } 749 if (i == MVXPE_PHY_TIMEOUT) { 750 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 751 mutex_exit(&mii_mutex); 752 return; 753 } 754 755 smi = MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | 756 MVXPE_SMI_OPCODE_WRITE | (val & MVXPE_SMI_DATA_MASK); 757 MVXPE_WRITE(sc, MVXPE_SMI, smi); 758 759 for (i = 0; i < MVXPE_PHY_TIMEOUT; i++) { 760 DELAY(1); 761 if (!(MVXPE_READ(sc, MVXPE_SMI) & MVXPE_SMI_BUSY)) 762 break; 763 } 764 765 mutex_exit(&mii_mutex); 766 767 if (i == MVXPE_PHY_TIMEOUT) 768 aprint_error_ifnet(ifp, "phy write timed out\n"); 769} 770 771STATIC void 772mvxpe_miibus_statchg(struct ifnet *ifp) 773{ 774 775 /* nothing to do */ 776} 777 778/* 779 * Address Decoding Window 780 */ 781STATIC void 782mvxpe_wininit(struct mvxpe_softc *sc, enum marvell_tags *tags) 783{ 784 device_t pdev = device_parent(sc->sc_dev); 785 uint64_t base; 786 uint32_t en, ac, size; 787 int window, target, attr, rv, i; 788 789 /* First disable all address decode windows */ 790 en = MVXPE_BARE_EN_MASK; 791 MVXPE_WRITE(sc, MVXPE_BARE, en); 792 793 ac = 0; 794 for (window = 0, i = 0; 795 tags[i] != MARVELL_TAG_UNDEFINED && window < MVXPE_NWINDOW; i++) { 796 rv = marvell_winparams_by_tag(pdev, tags[i], 797 &target, &attr, &base, &size); 798 if (rv != 0 || size == 0) 799 continue; 800 801 if (base > 0xffffffffULL) { 802 if (window >= MVXPE_NREMAP) { 803 aprint_error_dev(sc->sc_dev, 804 "can't remap window %d\n", window); 805 continue; 806 } 807 MVXPE_WRITE(sc, MVXPE_HA(window), 808 (base >> 32) & 0xffffffff); 809 } 810 811 MVXPE_WRITE(sc, MVXPE_BASEADDR(window), 812 MVXPE_BASEADDR_TARGET(target) | 813 MVXPE_BASEADDR_ATTR(attr) | 814 MVXPE_BASEADDR_BASE(base)); 815 MVXPE_WRITE(sc, MVXPE_S(window), MVXPE_S_SIZE(size)); 816 817 DPRINTSC(sc, 1, "Window %d Base 0x%016llx: Size 0x%08x\n", 818 window, base, size); 819 820 en &= ~(1 << window); 821 /* set full access (r/w) */ 822 ac |= MVXPE_EPAP_EPAR(window, MVXPE_EPAP_AC_FA); 823 window++; 824 } 825 /* allow to access decode window */ 826 MVXPE_WRITE(sc, MVXPE_EPAP, ac); 827 828 MVXPE_WRITE(sc, MVXPE_BARE, en); 829} 830 831/* 832 * Device Register Initialization 833 * reset device registers to device driver default value. 834 * the device is not enabled here. 835 */ 836STATIC int 837mvxpe_initreg(struct ifnet *ifp) 838{ 839 struct mvxpe_softc *sc = ifp->if_softc; 840 int serdes = 0; 841 uint32_t reg; 842 int q, i; 843 844 DPRINTIFNET(ifp, 1, "initializing device register\n"); 845 846 /* Init TX/RX Queue Registers */ 847 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 848 mvxpe_rx_lockq(sc, q); 849 if (mvxpe_rx_queue_init(ifp, q) != 0) { 850 aprint_error_ifnet(ifp, 851 "initialization failed: cannot initialize queue\n"); 852 mvxpe_rx_unlockq(sc, q); 853 return ENOBUFS; 854 } 855 mvxpe_rx_unlockq(sc, q); 856 857 mvxpe_tx_lockq(sc, q); 858 if (mvxpe_tx_queue_init(ifp, q) != 0) { 859 aprint_error_ifnet(ifp, 860 "initialization failed: cannot initialize queue\n"); 861 mvxpe_tx_unlockq(sc, q); 862 return ENOBUFS; 863 } 864 mvxpe_tx_unlockq(sc, q); 865 } 866 867 /* Tx MTU Limit */ 868 MVXPE_WRITE(sc, MVXPE_TXMTU, MVXPE_MTU); 869 870 /* Check SGMII or SERDES(asume IPL/U-BOOT initialize this) */ 871 reg = MVXPE_READ(sc, MVXPE_PMACC0); 872 if ((reg & MVXPE_PMACC0_PORTTYPE) != 0) 873 serdes = 1; 874 875 /* Ethernet Unit Control */ 876 reg = MVXPE_READ(sc, MVXPE_EUC); 877 reg |= MVXPE_EUC_POLLING; 878 MVXPE_WRITE(sc, MVXPE_EUC, reg); 879 880 /* Auto Negotiation */ 881 reg = MVXPE_PANC_MUSTSET; /* must write 0x1 */ 882 reg |= MVXPE_PANC_FORCELINKFAIL;/* force link state down */ 883 reg |= MVXPE_PANC_ANSPEEDEN; /* interface speed negotiation */ 884 reg |= MVXPE_PANC_ANDUPLEXEN; /* negotiate duplex mode */ 885 if (serdes) { 886 reg |= MVXPE_PANC_INBANDANEN; /* In Band negotiation */ 887 reg |= MVXPE_PANC_INBANDANBYPASSEN; /* bypass negotiation */ 888 reg |= MVXPE_PANC_SETFULLDX; /* set full-duplex on failure */ 889 } 890 MVXPE_WRITE(sc, MVXPE_PANC, reg); 891 892 /* EEE: Low Power Idle */ 893 reg = MVXPE_LPIC0_LILIMIT(MVXPE_LPI_LI); 894 reg |= MVXPE_LPIC0_TSLIMIT(MVXPE_LPI_TS); 895 MVXPE_WRITE(sc, MVXPE_LPIC0, reg); 896 897 reg = MVXPE_LPIC1_TWLIMIT(MVXPE_LPI_TS); 898 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 899 900 reg = MVXPE_LPIC2_MUSTSET; 901 MVXPE_WRITE(sc, MVXPE_LPIC2, reg); 902 903 /* Port MAC Control set 0 */ 904 reg = MVXPE_PMACC0_MUSTSET; /* must write 0x1 */ 905 reg &= ~MVXPE_PMACC0_PORTEN; /* port is still disabled */ 906 reg |= MVXPE_PMACC0_FRAMESIZELIMIT(MVXPE_MRU); 907 if (serdes) 908 reg |= MVXPE_PMACC0_PORTTYPE; 909 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 910 911 /* Port MAC Control set 1 is only used for loop-back test */ 912 913 /* Port MAC Control set 2 */ 914 reg = MVXPE_READ(sc, MVXPE_PMACC2); 915 reg &= (MVXPE_PMACC2_PCSEN | MVXPE_PMACC2_RGMIIEN); 916 reg |= MVXPE_PMACC2_MUSTSET; 917 MVXPE_WRITE(sc, MVXPE_PMACC2, reg); 918 919 /* Port MAC Control set 3 is used for IPG tune */ 920 921 /* Port MAC Control set 4 is not used */ 922 923 /* Port Configuration Extended: enable Tx CRC generation */ 924 reg = MVXPE_READ(sc, MVXPE_PXCX); 925 reg &= ~MVXPE_PXCX_TXCRCDIS; 926 MVXPE_WRITE(sc, MVXPE_PXCX, reg); 927 928 /* clear MIB counter registers(clear by read) */ 929 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) 930 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum)); 931 932 /* Set SDC register except IPGINT bits */ 933 reg = MVXPE_SDC_RXBSZ_16_64BITWORDS; 934 reg |= MVXPE_SDC_TXBSZ_16_64BITWORDS; 935 reg |= MVXPE_SDC_BLMR; 936 reg |= MVXPE_SDC_BLMT; 937 MVXPE_WRITE(sc, MVXPE_SDC, reg); 938 939 return 0; 940} 941 942/* 943 * Descriptor Ring Controls for each of queues 944 */ 945STATIC void * 946mvxpe_dma_memalloc(struct mvxpe_softc *sc, bus_dmamap_t *map, size_t size) 947{ 948 bus_dma_segment_t segs; 949 void *kva = NULL; 950 int nsegs; 951 952 /* 953 * Allocate the descriptor queues. 954 * struct mvxpe_ring_data contians array of descriptor per queue. 955 */ 956 if (bus_dmamem_alloc(sc->sc_dmat, 957 size, PAGE_SIZE, 0, &segs, 1, &nsegs, BUS_DMA_NOWAIT)) { 958 aprint_error_dev(sc->sc_dev, 959 "can't alloc device memory (%zu bytes)\n", size); 960 return NULL; 961 } 962 if (bus_dmamem_map(sc->sc_dmat, 963 &segs, nsegs, size, &kva, BUS_DMA_NOWAIT)) { 964 aprint_error_dev(sc->sc_dev, 965 "can't map dma buffers (%zu bytes)\n", size); 966 goto fail1; 967 } 968 969 if (bus_dmamap_create(sc->sc_dmat, 970 size, 1, size, 0, BUS_DMA_NOWAIT, map)) { 971 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 972 goto fail2; 973 } 974 if (bus_dmamap_load(sc->sc_dmat, 975 *map, kva, size, NULL, BUS_DMA_NOWAIT)) { 976 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 977 goto fail3; 978 } 979 memset(kva, 0, size); 980 return kva; 981 982fail3: 983 bus_dmamap_destroy(sc->sc_dmat, *map); 984 memset(map, 0, sizeof(*map)); 985fail2: 986 bus_dmamem_unmap(sc->sc_dmat, kva, size); 987fail1: 988 bus_dmamem_free(sc->sc_dmat, &segs, nsegs); 989 return NULL; 990} 991 992STATIC int 993mvxpe_ring_alloc_queue(struct mvxpe_softc *sc, int q) 994{ 995 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 996 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 997 998 /* 999 * MVXPE_RX_RING_CNT and MVXPE_TX_RING_CNT is a hard limit of 1000 * queue length. real queue length is limited by 1001 * sc->sc_rx_ring[q].rx_queue_len and sc->sc_tx_ring[q].tx_queue_len. 1002 * 1003 * because descriptor ring reallocation needs reprogramming of 1004 * DMA registers, we allocate enough descriptor for hard limit 1005 * of queue length. 1006 */ 1007 rx->rx_descriptors = 1008 mvxpe_dma_memalloc(sc, &rx->rx_descriptors_map, 1009 (sizeof(struct mvxpe_rx_desc) * MVXPE_RX_RING_CNT)); 1010 if (rx->rx_descriptors == NULL) 1011 goto fail; 1012 1013 tx->tx_descriptors = 1014 mvxpe_dma_memalloc(sc, &tx->tx_descriptors_map, 1015 (sizeof(struct mvxpe_tx_desc) * MVXPE_TX_RING_CNT)); 1016 if (tx->tx_descriptors == NULL) 1017 goto fail; 1018 1019 return 0; 1020fail: 1021 mvxpe_ring_dealloc_queue(sc, q); 1022 aprint_error_dev(sc->sc_dev, "DMA Ring buffer allocation failure.\n"); 1023 return ENOMEM; 1024} 1025 1026STATIC void 1027mvxpe_ring_dealloc_queue(struct mvxpe_softc *sc, int q) 1028{ 1029 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1030 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1031 bus_dma_segment_t *segs; 1032 bus_size_t size; 1033 void *kva; 1034 int nsegs; 1035 1036 /* Rx */ 1037 kva = (void *)MVXPE_RX_RING_MEM_VA(sc, q); 1038 if (kva) { 1039 segs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_segs; 1040 nsegs = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_nsegs; 1041 size = MVXPE_RX_RING_MEM_MAP(sc, q)->dm_mapsize; 1042 1043 bus_dmamap_unload(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1044 bus_dmamap_destroy(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q)); 1045 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1046 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1047 } 1048 1049 /* Tx */ 1050 kva = (void *)MVXPE_TX_RING_MEM_VA(sc, q); 1051 if (kva) { 1052 segs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_segs; 1053 nsegs = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_nsegs; 1054 size = MVXPE_TX_RING_MEM_MAP(sc, q)->dm_mapsize; 1055 1056 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1057 bus_dmamap_destroy(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q)); 1058 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1059 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1060 } 1061 1062 /* Clear doungling pointers all */ 1063 memset(rx, 0, sizeof(*rx)); 1064 memset(tx, 0, sizeof(*tx)); 1065} 1066 1067STATIC void 1068mvxpe_ring_init_queue(struct mvxpe_softc *sc, int q) 1069{ 1070 struct mvxpe_rx_desc *rxd = MVXPE_RX_RING_MEM_VA(sc, q); 1071 struct mvxpe_tx_desc *txd = MVXPE_TX_RING_MEM_VA(sc, q); 1072 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1073 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1074 static const int rx_default_queue_len[] = { 1075 MVXPE_RX_QUEUE_LIMIT_0, MVXPE_RX_QUEUE_LIMIT_1, 1076 MVXPE_RX_QUEUE_LIMIT_2, MVXPE_RX_QUEUE_LIMIT_3, 1077 MVXPE_RX_QUEUE_LIMIT_4, MVXPE_RX_QUEUE_LIMIT_5, 1078 MVXPE_RX_QUEUE_LIMIT_6, MVXPE_RX_QUEUE_LIMIT_7, 1079 }; 1080 static const int tx_default_queue_len[] = { 1081 MVXPE_TX_QUEUE_LIMIT_0, MVXPE_TX_QUEUE_LIMIT_1, 1082 MVXPE_TX_QUEUE_LIMIT_2, MVXPE_TX_QUEUE_LIMIT_3, 1083 MVXPE_TX_QUEUE_LIMIT_4, MVXPE_TX_QUEUE_LIMIT_5, 1084 MVXPE_TX_QUEUE_LIMIT_6, MVXPE_TX_QUEUE_LIMIT_7, 1085 }; 1086 extern uint32_t mvTclk; 1087 int i; 1088 1089 /* Rx handle */ 1090 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1091 MVXPE_RX_DESC(sc, q, i) = &rxd[i]; 1092 MVXPE_RX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_rx_desc) * i; 1093 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1094 } 1095 mutex_init(&rx->rx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1096 rx->rx_dma = rx->rx_cpu = 0; 1097 rx->rx_queue_len = rx_default_queue_len[q]; 1098 if (rx->rx_queue_len > MVXPE_RX_RING_CNT) 1099 rx->rx_queue_len = MVXPE_RX_RING_CNT; 1100 rx->rx_queue_th_received = rx->rx_queue_len / MVXPE_RXTH_RATIO; 1101 rx->rx_queue_th_free = rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 1102 rx->rx_queue_th_time = (mvTclk / 1000) / 2; /* 0.5 [ms] */ 1103 1104 /* Tx handle */ 1105 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1106 MVXPE_TX_DESC(sc, q, i) = &txd[i]; 1107 MVXPE_TX_DESC_OFF(sc, q, i) = sizeof(struct mvxpe_tx_desc) * i; 1108 MVXPE_TX_MBUF(sc, q, i) = NULL; 1109 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1110 if (bus_dmamap_create(sc->sc_dmat, 1111 mvxpbm_chunk_size(sc->sc_bm), 1112 MVXPE_TX_SEGLIMIT, mvxpbm_chunk_size(sc->sc_bm), 0, 1113 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 1114 &MVXPE_TX_MAP(sc, q, i))) { 1115 aprint_error_dev(sc->sc_dev, 1116 "can't create dma map (tx ring %d)\n", i); 1117 } 1118 } 1119 mutex_init(&tx->tx_ring_mtx, MUTEX_DEFAULT, IPL_NET); 1120 tx->tx_dma = tx->tx_cpu = 0; 1121 tx->tx_queue_len = tx_default_queue_len[q]; 1122 if (tx->tx_queue_len > MVXPE_TX_RING_CNT) 1123 tx->tx_queue_len = MVXPE_TX_RING_CNT; 1124 tx->tx_used = 0; 1125 tx->tx_queue_th_free = tx->tx_queue_len / MVXPE_TXTH_RATIO; 1126} 1127 1128STATIC void 1129mvxpe_ring_flush_queue(struct mvxpe_softc *sc, int q) 1130{ 1131 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1132 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1133 int i; 1134 1135 KASSERT_RX_MTX(sc, q); 1136 KASSERT_TX_MTX(sc, q); 1137 1138 /* Rx handle */ 1139 for (i = 0; i < MVXPE_RX_RING_CNT; i++) { 1140 if (MVXPE_RX_PKTBUF(sc, q, i) == NULL) 1141 continue; 1142 mvxpbm_free_chunk(MVXPE_RX_PKTBUF(sc, q, i)); 1143 MVXPE_RX_PKTBUF(sc, q, i) = NULL; 1144 } 1145 rx->rx_dma = rx->rx_cpu = 0; 1146 1147 /* Tx handle */ 1148 for (i = 0; i < MVXPE_TX_RING_CNT; i++) { 1149 if (MVXPE_TX_MBUF(sc, q, i) == NULL) 1150 continue; 1151 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, i)); 1152 m_freem(MVXPE_TX_MBUF(sc, q, i)); 1153 MVXPE_TX_MBUF(sc, q, i) = NULL; 1154 } 1155 tx->tx_dma = tx->tx_cpu = 0; 1156 tx->tx_used = 0; 1157} 1158 1159STATIC void 1160mvxpe_ring_sync_rx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1161{ 1162 int wrap; 1163 1164 KASSERT_RX_MTX(sc, q); 1165 KASSERT(count > 0 && count <= MVXPE_RX_RING_CNT); 1166 KASSERT(idx >= 0 && idx < MVXPE_RX_RING_CNT); 1167 1168 wrap = (idx + count) - MVXPE_RX_RING_CNT; 1169 if (wrap > 0) { 1170 count -= wrap; 1171 KASSERT(count > 0); 1172 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1173 0, sizeof(struct mvxpe_rx_desc) * wrap, ops); 1174 } 1175 bus_dmamap_sync(sc->sc_dmat, MVXPE_RX_RING_MEM_MAP(sc, q), 1176 MVXPE_RX_DESC_OFF(sc, q, idx), 1177 sizeof(struct mvxpe_rx_desc) * count, ops); 1178} 1179 1180STATIC void 1181mvxpe_ring_sync_tx(struct mvxpe_softc *sc, int q, int idx, int count, int ops) 1182{ 1183 int wrap = 0; 1184 1185 KASSERT_TX_MTX(sc, q); 1186 KASSERT(count > 0 && count <= MVXPE_TX_RING_CNT); 1187 KASSERT(idx >= 0 && idx < MVXPE_TX_RING_CNT); 1188 1189 wrap = (idx + count) - MVXPE_TX_RING_CNT; 1190 if (wrap > 0) { 1191 count -= wrap; 1192 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1193 0, sizeof(struct mvxpe_tx_desc) * wrap, ops); 1194 } 1195 bus_dmamap_sync(sc->sc_dmat, MVXPE_TX_RING_MEM_MAP(sc, q), 1196 MVXPE_TX_DESC_OFF(sc, q, idx), 1197 sizeof(struct mvxpe_tx_desc) * count, ops); 1198} 1199 1200/* 1201 * Rx/Tx Queue Control 1202 */ 1203STATIC int 1204mvxpe_rx_queue_init(struct ifnet *ifp, int q) 1205{ 1206 struct mvxpe_softc *sc = ifp->if_softc; 1207 uint32_t reg; 1208 1209 KASSERT_RX_MTX(sc, q); 1210 KASSERT(MVXPE_RX_RING_MEM_PA(sc, q) != 0); 1211 1212 /* descriptor address */ 1213 MVXPE_WRITE(sc, MVXPE_PRXDQA(q), MVXPE_RX_RING_MEM_PA(sc, q)); 1214 1215 /* Rx buffer size and descriptor ring size */ 1216 reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3); 1217 reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT); 1218 MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg); 1219 DPRINTIFNET(ifp, 1, "PRXDQS(%d): %#x\n", 1220 q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 1221 1222 /* Rx packet offset address */ 1223 reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3); 1224 MVXPE_WRITE(sc, MVXPE_PRXC(q), reg); 1225 DPRINTIFNET(ifp, 1, "PRXC(%d): %#x\n", 1226 q, MVXPE_READ(sc, MVXPE_PRXC(q))); 1227 1228 /* Rx DMA SNOOP */ 1229 reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU); 1230 reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU); 1231 MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg); 1232 1233 /* if DMA is not working, register is not updated */ 1234 KASSERT(MVXPE_READ(sc, MVXPE_PRXDQA(q)) == MVXPE_RX_RING_MEM_PA(sc, q)); 1235 return 0; 1236} 1237 1238STATIC int 1239mvxpe_tx_queue_init(struct ifnet *ifp, int q) 1240{ 1241 struct mvxpe_softc *sc = ifp->if_softc; 1242 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1243 uint32_t reg; 1244 1245 KASSERT_TX_MTX(sc, q); 1246 KASSERT(MVXPE_TX_RING_MEM_PA(sc, q) != 0); 1247 1248 /* descriptor address */ 1249 MVXPE_WRITE(sc, MVXPE_PTXDQA(q), MVXPE_TX_RING_MEM_PA(sc, q)); 1250 1251 /* Tx threshold, and descriptor ring size */ 1252 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1253 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 1254 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1255 DPRINTIFNET(ifp, 1, "PTXDQS(%d): %#x\n", 1256 q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 1257 1258 /* if DMA is not working, register is not updated */ 1259 KASSERT(MVXPE_READ(sc, MVXPE_PTXDQA(q)) == MVXPE_TX_RING_MEM_PA(sc, q)); 1260 return 0; 1261} 1262 1263STATIC int 1264mvxpe_rx_queue_enable(struct ifnet *ifp, int q) 1265{ 1266 struct mvxpe_softc *sc = ifp->if_softc; 1267 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1268 uint32_t reg; 1269 1270 KASSERT_RX_MTX(sc, q); 1271 1272 /* Set Rx interrupt threshold */ 1273 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1274 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 1275 MVXPE_WRITE(sc, MVXPE_PRXDQTH(q), reg); 1276 1277 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 1278 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1279 1280 /* Unmask RXTX_TH Intr. */ 1281 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1282 reg |= MVXPE_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1283 reg |= MVXPE_PRXTXTI_RDTAQ(q); /* Rx Descriptor Alart */ 1284 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1285 1286 /* Enable Rx queue */ 1287 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1288 reg |= MVXPE_RQC_ENQ(q); 1289 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1290 1291 return 0; 1292} 1293 1294STATIC int 1295mvxpe_tx_queue_enable(struct ifnet *ifp, int q) 1296{ 1297 struct mvxpe_softc *sc = ifp->if_softc; 1298 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1299 uint32_t reg; 1300 1301 KASSERT_TX_MTX(sc, q); 1302 1303 /* Set Tx interrupt threshold */ 1304 reg = MVXPE_READ(sc, MVXPE_PTXDQS(q)); 1305 reg &= ~MVXPE_PTXDQS_TBT_MASK; /* keep queue size */ 1306 reg |= MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 1307 MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg); 1308 1309 /* Unmask RXTX_TH Intr. */ 1310 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1311 reg |= MVXPE_PRXTXTI_TBTCQ(q); /* Tx Threshold cross */ 1312 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1313 1314 /* Don't update MVXPE_TQC here, there is no packet yet. */ 1315 return 0; 1316} 1317 1318STATIC void 1319mvxpe_rx_lockq(struct mvxpe_softc *sc, int q) 1320{ 1321 KASSERT(q >= 0); 1322 KASSERT(q < MVXPE_QUEUE_SIZE); 1323 mutex_enter(&sc->sc_rx_ring[q].rx_ring_mtx); 1324} 1325 1326STATIC void 1327mvxpe_rx_unlockq(struct mvxpe_softc *sc, int q) 1328{ 1329 KASSERT(q >= 0); 1330 KASSERT(q < MVXPE_QUEUE_SIZE); 1331 mutex_exit(&sc->sc_rx_ring[q].rx_ring_mtx); 1332} 1333 1334STATIC void 1335mvxpe_tx_lockq(struct mvxpe_softc *sc, int q) 1336{ 1337 KASSERT(q >= 0); 1338 KASSERT(q < MVXPE_QUEUE_SIZE); 1339 mutex_enter(&sc->sc_tx_ring[q].tx_ring_mtx); 1340} 1341 1342STATIC void 1343mvxpe_tx_unlockq(struct mvxpe_softc *sc, int q) 1344{ 1345 KASSERT(q >= 0); 1346 KASSERT(q < MVXPE_QUEUE_SIZE); 1347 mutex_exit(&sc->sc_tx_ring[q].tx_ring_mtx); 1348} 1349 1350/* 1351 * Interrupt Handlers 1352 */ 1353STATIC void 1354mvxpe_disable_intr(struct mvxpe_softc *sc) 1355{ 1356 MVXPE_WRITE(sc, MVXPE_EUIM, 0); 1357 MVXPE_WRITE(sc, MVXPE_EUIC, 0); 1358 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, 0); 1359 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, 0); 1360 MVXPE_WRITE(sc, MVXPE_PRXTXIM, 0); 1361 MVXPE_WRITE(sc, MVXPE_PRXTXIC, 0); 1362 MVXPE_WRITE(sc, MVXPE_PMIM, 0); 1363 MVXPE_WRITE(sc, MVXPE_PMIC, 0); 1364 MVXPE_WRITE(sc, MVXPE_PIE, 0); 1365} 1366 1367STATIC void 1368mvxpe_enable_intr(struct mvxpe_softc *sc) 1369{ 1370 uint32_t reg; 1371 1372 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1373 reg = MVXPE_READ(sc, MVXPE_PMIM); 1374 reg |= MVXPE_PMI_PHYSTATUSCHNG; 1375 reg |= MVXPE_PMI_LINKCHANGE; 1376 reg |= MVXPE_PMI_IAE; 1377 reg |= MVXPE_PMI_RXOVERRUN; 1378 reg |= MVXPE_PMI_RXCRCERROR; 1379 reg |= MVXPE_PMI_RXLARGEPACKET; 1380 reg |= MVXPE_PMI_TXUNDRN; 1381 reg |= MVXPE_PMI_PRBSERROR; 1382 reg |= MVXPE_PMI_SRSE; 1383#if 0 1384 /* 1385 * The device may raise false interrupts for SERDES even if the device 1386 * is not configured to use SERDES connection. 1387 */ 1388 reg |= MVXPE_PMI_PRBSERROR; 1389 reg |= MVXPE_PMI_SRSE; 1390#else 1391 reg &= ~MVXPE_PMI_PRBSERROR; 1392 reg &= ~MVXPE_PMI_SRSE; 1393#endif 1394 reg |= MVXPE_PMI_TREQ_MASK; 1395 MVXPE_WRITE(sc, MVXPE_PMIM, reg); 1396 1397 /* Enable Summary Bit to check all interrupt cause. */ 1398 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1399 reg |= MVXPE_PRXTXTI_PMISCICSUMMARY; 1400 reg |= MVXPE_PRXTXTI_PTXERRORSUMMARY; 1401 reg |= MVXPE_PRXTXTI_PRXTXICSUMMARY; 1402 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1403 1404 /* Enable All Queue Interrupt */ 1405 reg = MVXPE_READ(sc, MVXPE_PIE); 1406 reg |= MVXPE_PIE_RXPKTINTRPTENB_MASK; 1407 reg |= MVXPE_PIE_TXPKTINTRPTENB_MASK; 1408 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1409} 1410 1411STATIC int 1412mvxpe_rxtxth_intr(void *arg) 1413{ 1414 struct mvxpe_softc *sc = arg; 1415 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1416 uint32_t ic, queues, datum = 0; 1417 1418 DPRINTSC(sc, 2, "got RXTX_TH_Intr\n"); 1419 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtxth); 1420 1421 mvxpe_sc_lock(sc); 1422 ic = MVXPE_READ(sc, MVXPE_PRXTXTIC); 1423 if (ic == 0) { 1424 mvxpe_sc_unlock(sc); 1425 return 0; 1426 } 1427 MVXPE_WRITE(sc, MVXPE_PRXTXTIC, ~ic); 1428 datum = datum ^ ic; 1429 1430 DPRINTIFNET(ifp, 2, "PRXTXTIC: %#x\n", ic); 1431 1432 /* ack maintance interrupt first */ 1433 if (ic & MVXPE_PRXTXTI_PTXERRORSUMMARY) { 1434 DPRINTIFNET(ifp, 1, "PRXTXTIC: +PTXERRORSUMMARY\n"); 1435 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtxth_txerr); 1436 } 1437 if ((ic & MVXPE_PRXTXTI_PMISCICSUMMARY)) { 1438 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PMISCICSUMMARY\n"); 1439 mvxpe_misc_intr(sc); 1440 } 1441 if (ic & MVXPE_PRXTXTI_PRXTXICSUMMARY) { 1442 DPRINTIFNET(ifp, 2, "PTXTXTIC: +PRXTXICSUMMARY\n"); 1443 mvxpe_rxtx_intr(sc); 1444 } 1445 if (!(ifp->if_flags & IFF_RUNNING)) { 1446 mvxpe_sc_unlock(sc); 1447 return 1; 1448 } 1449 1450 /* RxTxTH interrupt */ 1451 queues = MVXPE_PRXTXTI_GET_RBICTAPQ(ic); 1452 if (queues) { 1453 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RXEOF\n"); 1454 mvxpe_rx(sc, queues); 1455 } 1456 queues = MVXPE_PRXTXTI_GET_TBTCQ(ic); 1457 if (queues) { 1458 DPRINTIFNET(ifp, 2, "PRXTXTIC: +TBTCQ\n"); 1459 mvxpe_tx_complete(sc, queues); 1460 } 1461 queues = MVXPE_PRXTXTI_GET_RDTAQ(ic); 1462 if (queues) { 1463 DPRINTIFNET(ifp, 2, "PRXTXTIC: +RDTAQ\n"); 1464 mvxpe_rx_refill(sc, queues); 1465 } 1466 mvxpe_sc_unlock(sc); 1467 1468 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1469 mvxpe_start(ifp); 1470 1471 rnd_add_uint32(&sc->sc_rnd_source, datum); 1472 1473 return 1; 1474} 1475 1476STATIC int 1477mvxpe_misc_intr(void *arg) 1478{ 1479 struct mvxpe_softc *sc = arg; 1480#ifdef MVXPE_DEBUG 1481 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1482#endif 1483 uint32_t ic; 1484 uint32_t datum = 0; 1485 int claimed = 0; 1486 1487 DPRINTSC(sc, 2, "got MISC_INTR\n"); 1488 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_misc); 1489 1490 KASSERT_SC_MTX(sc); 1491 1492 for (;;) { 1493 ic = MVXPE_READ(sc, MVXPE_PMIC); 1494 ic &= MVXPE_READ(sc, MVXPE_PMIM); 1495 if (ic == 0) 1496 break; 1497 MVXPE_WRITE(sc, MVXPE_PMIC, ~ic); 1498 datum = datum ^ ic; 1499 claimed = 1; 1500 1501 DPRINTIFNET(ifp, 2, "PMIC=%#x\n", ic); 1502 if (ic & MVXPE_PMI_PHYSTATUSCHNG) { 1503 DPRINTIFNET(ifp, 2, "+PHYSTATUSCHNG\n"); 1504 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_phystatuschng); 1505 } 1506 if (ic & MVXPE_PMI_LINKCHANGE) { 1507 DPRINTIFNET(ifp, 2, "+LINKCHANGE\n"); 1508 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_linkchange); 1509 mvxpe_linkupdate(sc); 1510 } 1511 if (ic & MVXPE_PMI_IAE) { 1512 DPRINTIFNET(ifp, 2, "+IAE\n"); 1513 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_iae); 1514 } 1515 if (ic & MVXPE_PMI_RXOVERRUN) { 1516 DPRINTIFNET(ifp, 2, "+RXOVERRUN\n"); 1517 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxoverrun); 1518 } 1519 if (ic & MVXPE_PMI_RXCRCERROR) { 1520 DPRINTIFNET(ifp, 2, "+RXCRCERROR\n"); 1521 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxcrc); 1522 } 1523 if (ic & MVXPE_PMI_RXLARGEPACKET) { 1524 DPRINTIFNET(ifp, 2, "+RXLARGEPACKET\n"); 1525 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_rxlargepacket); 1526 } 1527 if (ic & MVXPE_PMI_TXUNDRN) { 1528 DPRINTIFNET(ifp, 2, "+TXUNDRN\n"); 1529 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txunderrun); 1530 } 1531 if (ic & MVXPE_PMI_PRBSERROR) { 1532 DPRINTIFNET(ifp, 2, "+PRBSERROR\n"); 1533 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_prbserr); 1534 } 1535 if (ic & MVXPE_PMI_TREQ_MASK) { 1536 DPRINTIFNET(ifp, 2, "+TREQ\n"); 1537 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_misc_txreq); 1538 } 1539 } 1540 if (datum) 1541 rnd_add_uint32(&sc->sc_rnd_source, datum); 1542 1543 return claimed; 1544} 1545 1546STATIC int 1547mvxpe_rxtx_intr(void *arg) 1548{ 1549 struct mvxpe_softc *sc = arg; 1550#ifdef MVXPE_DEBUG 1551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1552#endif 1553 uint32_t datum = 0; 1554 uint32_t prxtxic; 1555 int claimed = 0; 1556 1557 DPRINTSC(sc, 2, "got RXTX_Intr\n"); 1558 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_i_rxtx); 1559 1560 KASSERT_SC_MTX(sc); 1561 1562 for (;;) { 1563 prxtxic = MVXPE_READ(sc, MVXPE_PRXTXIC); 1564 prxtxic &= MVXPE_READ(sc, MVXPE_PRXTXIM); 1565 if (prxtxic == 0) 1566 break; 1567 MVXPE_WRITE(sc, MVXPE_PRXTXIC, ~prxtxic); 1568 datum = datum ^ prxtxic; 1569 claimed = 1; 1570 1571 DPRINTSC(sc, 2, "PRXTXIC: %#x\n", prxtxic); 1572 1573 if (prxtxic & MVXPE_PRXTXI_RREQ_MASK) { 1574 DPRINTIFNET(ifp, 1, "Rx Resource Error.\n"); 1575 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rreq); 1576 } 1577 if (prxtxic & MVXPE_PRXTXI_RPQ_MASK) { 1578 DPRINTIFNET(ifp, 1, "Rx Packet in Queue.\n"); 1579 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rpq); 1580 } 1581 if (prxtxic & MVXPE_PRXTXI_TBRQ_MASK) { 1582 DPRINTIFNET(ifp, 1, "Tx Buffer Return.\n"); 1583 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_tbrq); 1584 } 1585 if (prxtxic & MVXPE_PRXTXI_PRXTXTHICSUMMARY) { 1586 DPRINTIFNET(ifp, 1, "PRXTXTHIC Sumary\n"); 1587 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_rxtxth); 1588 } 1589 if (prxtxic & MVXPE_PRXTXI_PTXERRORSUMMARY) { 1590 DPRINTIFNET(ifp, 1, "PTXERROR Sumary\n"); 1591 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_txerr); 1592 } 1593 if (prxtxic & MVXPE_PRXTXI_PMISCICSUMMARY) { 1594 DPRINTIFNET(ifp, 1, "PMISCIC Sumary\n"); 1595 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxtx_misc); 1596 } 1597 } 1598 if (datum) 1599 rnd_add_uint32(&sc->sc_rnd_source, datum); 1600 1601 return claimed; 1602} 1603 1604STATIC void 1605mvxpe_tick(void *arg) 1606{ 1607 struct mvxpe_softc *sc = arg; 1608 struct mii_data *mii = &sc->sc_mii; 1609 1610 mvxpe_sc_lock(sc); 1611 1612 mii_tick(mii); 1613 mii_pollstat(&sc->sc_mii); 1614 1615 /* read mib regisers(clear by read) */ 1616 mvxpe_update_mib(sc); 1617 1618 /* read counter registers(clear by read) */ 1619 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pdfc, 1620 MVXPE_READ(sc, MVXPE_PDFC)); 1621 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_pofc, 1622 MVXPE_READ(sc, MVXPE_POFC)); 1623 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txbadfcs, 1624 MVXPE_READ(sc, MVXPE_TXBADFCS)); 1625 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_txdropped, 1626 MVXPE_READ(sc, MVXPE_TXDROPPED)); 1627 MVXPE_EVCNT_ADD(&sc->sc_ev.ev_reg_lpic, 1628 MVXPE_READ(sc, MVXPE_LPIC)); 1629 1630 mvxpe_sc_unlock(sc); 1631 1632 callout_schedule(&sc->sc_tick_ch, hz); 1633} 1634 1635 1636/* 1637 * struct ifnet and mii callbacks 1638 */ 1639STATIC void 1640mvxpe_start(struct ifnet *ifp) 1641{ 1642 struct mvxpe_softc *sc = ifp->if_softc; 1643 struct mbuf *m; 1644 int q; 1645 1646 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1647 DPRINTIFNET(ifp, 1, "not running\n"); 1648 return; 1649 } 1650 1651 mvxpe_sc_lock(sc); 1652 if (!MVXPE_IS_LINKUP(sc)) { 1653 /* If Link is DOWN, can't start TX */ 1654 DPRINTIFNET(ifp, 1, "link fail\n"); 1655 for (;;) { 1656 /* 1657 * discard stale packets all. 1658 * these may confuse DAD, ARP or timer based protocols. 1659 */ 1660 IFQ_DEQUEUE(&ifp->if_snd, m); 1661 if (m == NULL) 1662 break; 1663 m_freem(m); 1664 } 1665 mvxpe_sc_unlock(sc); 1666 return; 1667 } 1668 for (;;) { 1669 /* 1670 * don't use IFQ_POLL(). 1671 * there is lock problem between IFQ_POLL and IFQ_DEQUEUE 1672 * on SMP enabled networking stack. 1673 */ 1674 IFQ_DEQUEUE(&ifp->if_snd, m); 1675 if (m == NULL) 1676 break; 1677 1678 q = mvxpe_tx_queue_select(sc, m); 1679 if (q < 0) 1680 break; 1681 /* mutex is held in mvxpe_tx_queue_select() */ 1682 1683 if (mvxpe_tx_queue(sc, m, q) != 0) { 1684 DPRINTIFNET(ifp, 1, "cannot add packet to tx ring\n"); 1685 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txerr); 1686 mvxpe_tx_unlockq(sc, q); 1687 break; 1688 } 1689 mvxpe_tx_unlockq(sc, q); 1690 KASSERT(sc->sc_tx_ring[q].tx_used >= 0); 1691 KASSERT(sc->sc_tx_ring[q].tx_used <= 1692 sc->sc_tx_ring[q].tx_queue_len); 1693 DPRINTIFNET(ifp, 1, "a packet is added to tx ring\n"); 1694 sc->sc_tx_pending++; 1695 ifp->if_timer = 1; 1696 sc->sc_wdogsoft = 1; 1697 bpf_mtap(ifp, m); 1698 } 1699 mvxpe_sc_unlock(sc); 1700 1701 return; 1702} 1703 1704STATIC int 1705mvxpe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1706{ 1707 struct mvxpe_softc *sc = ifp->if_softc; 1708 struct ifreq *ifr = data; 1709 int error = 0; 1710 int s; 1711 1712 switch (cmd) { 1713 case SIOCGIFMEDIA: 1714 case SIOCSIFMEDIA: 1715 DPRINTIFNET(ifp, 2, "mvxpe_ioctl MEDIA\n"); 1716 s = splnet(); /* XXX: is there suitable mutex? */ 1717 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1718 splx(s); 1719 break; 1720 default: 1721 DPRINTIFNET(ifp, 2, "mvxpe_ioctl ETHER\n"); 1722 error = ether_ioctl(ifp, cmd, data); 1723 if (error == ENETRESET) { 1724 if (ifp->if_flags & IFF_RUNNING) { 1725 mvxpe_sc_lock(sc); 1726 mvxpe_filter_setup(sc); 1727 mvxpe_sc_unlock(sc); 1728 } 1729 error = 0; 1730 } 1731 break; 1732 } 1733 1734 return error; 1735} 1736 1737STATIC int 1738mvxpe_init(struct ifnet *ifp) 1739{ 1740 struct mvxpe_softc *sc = ifp->if_softc; 1741 struct mii_data *mii = &sc->sc_mii; 1742 uint32_t reg; 1743 int q; 1744 1745 mvxpe_sc_lock(sc); 1746 1747 /* Start DMA Engine */ 1748 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000000); 1749 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000000); 1750 MVXPE_WRITE(sc, MVXPE_PACC, MVXPE_PACC_ACCELERATIONMODE_EDM); 1751 1752 /* Enable port */ 1753 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1754 reg |= MVXPE_PMACC0_PORTEN; 1755 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1756 1757 /* Link up */ 1758 mvxpe_linkup(sc); 1759 1760 /* Enable All Queue and interrupt of each Queue */ 1761 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1762 mvxpe_rx_lockq(sc, q); 1763 mvxpe_rx_queue_enable(ifp, q); 1764 mvxpe_rx_queue_refill(sc, q); 1765 mvxpe_rx_unlockq(sc, q); 1766 1767 mvxpe_tx_lockq(sc, q); 1768 mvxpe_tx_queue_enable(ifp, q); 1769 mvxpe_tx_unlockq(sc, q); 1770 } 1771 1772 /* Enable interrupt */ 1773 mvxpe_enable_intr(sc); 1774 1775 /* Set Counter */ 1776 callout_schedule(&sc->sc_tick_ch, hz); 1777 1778 /* Media check */ 1779 mii_mediachg(mii); 1780 1781 ifp->if_flags |= IFF_RUNNING; 1782 ifp->if_flags &= ~IFF_OACTIVE; 1783 1784 mvxpe_sc_unlock(sc); 1785 return 0; 1786} 1787 1788/* ARGSUSED */ 1789STATIC void 1790mvxpe_stop(struct ifnet *ifp, int disable) 1791{ 1792 struct mvxpe_softc *sc = ifp->if_softc; 1793 uint32_t reg; 1794 int q, cnt; 1795 1796 DPRINTIFNET(ifp, 1, "stop device dma and interrupts.\n"); 1797 1798 mvxpe_sc_lock(sc); 1799 1800 callout_stop(&sc->sc_tick_ch); 1801 1802 /* Link down */ 1803 mvxpe_linkdown(sc); 1804 1805 /* Disable Rx interrupt */ 1806 reg = MVXPE_READ(sc, MVXPE_PIE); 1807 reg &= ~MVXPE_PIE_RXPKTINTRPTENB_MASK; 1808 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1809 1810 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1811 reg &= ~MVXPE_PRXTXTI_RBICTAPQ_MASK; 1812 reg &= ~MVXPE_PRXTXTI_RDTAQ_MASK; 1813 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1814 1815 /* Wait for all Rx activity to terminate. */ 1816 reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK; 1817 reg = MVXPE_RQC_DIS(reg); 1818 MVXPE_WRITE(sc, MVXPE_RQC, reg); 1819 cnt = 0; 1820 do { 1821 if (cnt >= RX_DISABLE_TIMEOUT) { 1822 aprint_error_ifnet(ifp, 1823 "timeout for RX stopped. rqc 0x%x\n", reg); 1824 break; 1825 } 1826 cnt++; 1827 reg = MVXPE_READ(sc, MVXPE_RQC); 1828 } while (reg & MVXPE_RQC_EN_MASK); 1829 1830 /* Wait for all Tx activety to terminate. */ 1831 reg = MVXPE_READ(sc, MVXPE_PIE); 1832 reg &= ~MVXPE_PIE_TXPKTINTRPTENB_MASK; 1833 MVXPE_WRITE(sc, MVXPE_PIE, reg); 1834 1835 reg = MVXPE_READ(sc, MVXPE_PRXTXTIM); 1836 reg &= ~MVXPE_PRXTXTI_TBTCQ_MASK; 1837 MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg); 1838 1839 reg = MVXPE_READ(sc, MVXPE_TQC) & MVXPE_TQC_EN_MASK; 1840 reg = MVXPE_TQC_DIS(reg); 1841 MVXPE_WRITE(sc, MVXPE_TQC, reg); 1842 cnt = 0; 1843 do { 1844 if (cnt >= TX_DISABLE_TIMEOUT) { 1845 aprint_error_ifnet(ifp, 1846 "timeout for TX stopped. tqc 0x%x\n", reg); 1847 break; 1848 } 1849 cnt++; 1850 reg = MVXPE_READ(sc, MVXPE_TQC); 1851 } while (reg & MVXPE_TQC_EN_MASK); 1852 1853 /* Wait for all Tx FIFO is empty */ 1854 cnt = 0; 1855 do { 1856 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1857 aprint_error_ifnet(ifp, 1858 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1859 break; 1860 } 1861 cnt++; 1862 reg = MVXPE_READ(sc, MVXPE_PS0); 1863 } while (!(reg & MVXPE_PS0_TXFIFOEMP) && (reg & MVXPE_PS0_TXINPROG)); 1864 1865 /* Reset the MAC Port Enable bit */ 1866 reg = MVXPE_READ(sc, MVXPE_PMACC0); 1867 reg &= ~MVXPE_PMACC0_PORTEN; 1868 MVXPE_WRITE(sc, MVXPE_PMACC0, reg); 1869 1870 /* Disable each of queue */ 1871 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1872 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 1873 1874 mvxpe_rx_lockq(sc, q); 1875 mvxpe_tx_lockq(sc, q); 1876 1877 /* Disable Rx packet buffer refill request */ 1878 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 1879 reg |= MVXPE_PRXDQTH_NODT(0); 1880 MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg); 1881 1882 if (disable) { 1883 /* 1884 * Hold Reset state of DMA Engine 1885 * (must write 0x0 to restart it) 1886 */ 1887 MVXPE_WRITE(sc, MVXPE_PRXINIT, 0x00000001); 1888 MVXPE_WRITE(sc, MVXPE_PTXINIT, 0x00000001); 1889 mvxpe_ring_flush_queue(sc, q); 1890 } 1891 1892 mvxpe_tx_unlockq(sc, q); 1893 mvxpe_rx_unlockq(sc, q); 1894 } 1895 1896 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1897 1898 mvxpe_sc_unlock(sc); 1899} 1900 1901STATIC void 1902mvxpe_watchdog(struct ifnet *ifp) 1903{ 1904 struct mvxpe_softc *sc = ifp->if_softc; 1905 int q; 1906 1907 mvxpe_sc_lock(sc); 1908 1909 /* 1910 * Reclaim first as there is a possibility of losing Tx completion 1911 * interrupts. 1912 */ 1913 mvxpe_tx_complete(sc, 0xff); 1914 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 1915 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 1916 1917 if (tx->tx_dma != tx->tx_cpu) { 1918 if (sc->sc_wdogsoft) { 1919 /* 1920 * There is race condition between CPU and DMA 1921 * engine. When DMA engine encounters queue end, 1922 * it clears MVXPE_TQC_ENQ bit. 1923 * XXX: how about enhanced mode? 1924 */ 1925 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 1926 ifp->if_timer = 5; 1927 sc->sc_wdogsoft = 0; 1928 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_wdogsoft); 1929 } else { 1930 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1931 ifp->if_oerrors++; 1932 mvxpe_linkreset(sc); 1933 mvxpe_sc_unlock(sc); 1934 1935 /* trigger reinitialize sequence */ 1936 mvxpe_stop(ifp, 1); 1937 mvxpe_init(ifp); 1938 1939 mvxpe_sc_lock(sc); 1940 } 1941 } 1942 } 1943 mvxpe_sc_unlock(sc); 1944} 1945 1946STATIC int 1947mvxpe_ifflags_cb(struct ethercom *ec) 1948{ 1949 struct ifnet *ifp = &ec->ec_if; 1950 struct mvxpe_softc *sc = ifp->if_softc; 1951 int change = ifp->if_flags ^ sc->sc_if_flags; 1952 1953 mvxpe_sc_lock(sc); 1954 1955 if (change != 0) 1956 sc->sc_if_flags = ifp->if_flags; 1957 1958 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) { 1959 mvxpe_sc_unlock(sc); 1960 return ENETRESET; 1961 } 1962 1963 if ((change & IFF_PROMISC) != 0) 1964 mvxpe_filter_setup(sc); 1965 1966 if ((change & IFF_UP) != 0) 1967 mvxpe_linkreset(sc); 1968 1969 mvxpe_sc_unlock(sc); 1970 return 0; 1971} 1972 1973STATIC int 1974mvxpe_mediachange(struct ifnet *ifp) 1975{ 1976 return ether_mediachange(ifp); 1977} 1978 1979STATIC void 1980mvxpe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1981{ 1982 ether_mediastatus(ifp, ifmr); 1983} 1984 1985/* 1986 * Link State Notify 1987 */ 1988STATIC void mvxpe_linkupdate(struct mvxpe_softc *sc) 1989{ 1990 int linkup; /* bool */ 1991 1992 KASSERT_SC_MTX(sc); 1993 1994 /* tell miibus */ 1995 mii_pollstat(&sc->sc_mii); 1996 1997 /* syslog */ 1998 linkup = MVXPE_IS_LINKUP(sc); 1999 if (sc->sc_linkstate == linkup) 2000 return; 2001 2002#ifdef DEBUG 2003 log(LOG_DEBUG, 2004 "%s: link %s\n", device_xname(sc->sc_dev), linkup ? "up" : "down"); 2005#endif 2006 if (linkup) 2007 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_up); 2008 else 2009 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_link_down); 2010 2011 sc->sc_linkstate = linkup; 2012} 2013 2014STATIC void 2015mvxpe_linkup(struct mvxpe_softc *sc) 2016{ 2017 uint32_t reg; 2018 2019 KASSERT_SC_MTX(sc); 2020 2021 /* set EEE parameters */ 2022 reg = MVXPE_READ(sc, MVXPE_LPIC1); 2023 if (sc->sc_cf.cf_lpi) 2024 reg |= MVXPE_LPIC1_LPIRE; 2025 else 2026 reg &= ~MVXPE_LPIC1_LPIRE; 2027 MVXPE_WRITE(sc, MVXPE_LPIC1, reg); 2028 2029 /* set auto-negotiation parameters */ 2030 reg = MVXPE_READ(sc, MVXPE_PANC); 2031 if (sc->sc_cf.cf_fc) { 2032 /* flow control negotiation */ 2033 reg |= MVXPE_PANC_PAUSEADV; 2034 reg |= MVXPE_PANC_ANFCEN; 2035 } 2036 else { 2037 reg &= ~MVXPE_PANC_PAUSEADV; 2038 reg &= ~MVXPE_PANC_ANFCEN; 2039 } 2040 reg &= ~MVXPE_PANC_FORCELINKFAIL; 2041 reg &= ~MVXPE_PANC_FORCELINKPASS; 2042 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2043 2044 mii_mediachg(&sc->sc_mii); 2045} 2046 2047STATIC void 2048mvxpe_linkdown(struct mvxpe_softc *sc) 2049{ 2050 struct mii_softc *mii; 2051 uint32_t reg; 2052 2053 KASSERT_SC_MTX(sc); 2054 return; 2055 2056 reg = MVXPE_READ(sc, MVXPE_PANC); 2057 reg |= MVXPE_PANC_FORCELINKFAIL; 2058 reg &= MVXPE_PANC_FORCELINKPASS; 2059 MVXPE_WRITE(sc, MVXPE_PANC, reg); 2060 2061 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2062 if (mii) 2063 mii_phy_down(mii); 2064} 2065 2066STATIC void 2067mvxpe_linkreset(struct mvxpe_softc *sc) 2068{ 2069 struct mii_softc *mii; 2070 2071 KASSERT_SC_MTX(sc); 2072 2073 /* force reset PHY first */ 2074 mii = LIST_FIRST(&sc->sc_mii.mii_phys); 2075 if (mii) 2076 mii_phy_reset(mii); 2077 2078 /* reinit MAC and PHY */ 2079 mvxpe_linkdown(sc); 2080 if ((sc->sc_if_flags & IFF_UP) != 0) 2081 mvxpe_linkup(sc); 2082} 2083 2084/* 2085 * Tx Subroutines 2086 */ 2087STATIC int 2088mvxpe_tx_queue_select(struct mvxpe_softc *sc, struct mbuf *m) 2089{ 2090 int q = 0; 2091 2092 /* XXX: get attribute from ALTQ framework? */ 2093 mvxpe_tx_lockq(sc, q); 2094 return 0; 2095} 2096 2097STATIC int 2098mvxpe_tx_queue(struct mvxpe_softc *sc, struct mbuf *m, int q) 2099{ 2100 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2101 bus_dma_segment_t *txsegs; 2102 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2103 struct mvxpe_tx_desc *t = NULL; 2104 uint32_t ptxsu; 2105 int txnsegs; 2106 int start, used; 2107 int i; 2108 2109 KASSERT_TX_MTX(sc, q); 2110 KASSERT(tx->tx_used >= 0); 2111 KASSERT(tx->tx_used <= tx->tx_queue_len); 2112 2113 /* load mbuf using dmamap of 1st descriptor */ 2114 if (bus_dmamap_load_mbuf(sc->sc_dmat, 2115 MVXPE_TX_MAP(sc, q, tx->tx_cpu), m, BUS_DMA_NOWAIT) != 0) { 2116 m_freem(m); 2117 return ENOBUFS; 2118 } 2119 txsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_segs; 2120 txnsegs = MVXPE_TX_MAP(sc, q, tx->tx_cpu)->dm_nsegs; 2121 if (txnsegs <= 0 || (txnsegs + tx->tx_used) > tx->tx_queue_len) { 2122 /* we have no enough descriptors or mbuf is broken */ 2123 bus_dmamap_unload(sc->sc_dmat, MVXPE_TX_MAP(sc, q, tx->tx_cpu)); 2124 m_freem(m); 2125 return ENOBUFS; 2126 } 2127 DPRINTSC(sc, 2, "send packet %p descriptor %d\n", m, tx->tx_cpu); 2128 KASSERT(MVXPE_TX_MBUF(sc, q, tx->tx_cpu) == NULL); 2129 2130 /* remember mbuf using 1st descriptor */ 2131 MVXPE_TX_MBUF(sc, q, tx->tx_cpu) = m; 2132 bus_dmamap_sync(sc->sc_dmat, 2133 MVXPE_TX_MAP(sc, q, tx->tx_cpu), 0, m->m_pkthdr.len, 2134 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2135 2136 /* load to tx descriptors */ 2137 start = tx->tx_cpu; 2138 used = 0; 2139 for (i = 0; i < txnsegs; i++) { 2140 if (__predict_false(txsegs[i].ds_len == 0)) 2141 continue; 2142 t = MVXPE_TX_DESC(sc, q, tx->tx_cpu); 2143 t->command = 0; 2144 t->l4ichk = 0; 2145 t->flags = 0; 2146 if (i == 0) { 2147 /* 1st descriptor */ 2148 t->command |= MVXPE_TX_CMD_W_PACKET_OFFSET(0); 2149 t->command |= MVXPE_TX_CMD_PADDING; 2150 t->command |= MVXPE_TX_CMD_F; 2151 mvxpe_tx_set_csumflag(ifp, t, m); 2152 } 2153 t->bufptr = txsegs[i].ds_addr; 2154 t->bytecnt = txsegs[i].ds_len; 2155 tx->tx_cpu = tx_counter_adv(tx->tx_cpu, 1); 2156 tx->tx_used++; 2157 used++; 2158 } 2159 /* t is last descriptor here */ 2160 KASSERT(t != NULL); 2161 t->command |= MVXPE_TX_CMD_L; 2162 2163 DPRINTSC(sc, 2, "queue %d, %d descriptors used\n", q, used); 2164#ifdef MVXPE_DEBUG 2165 if (mvxpe_debug > 2) 2166 for (i = start; i <= tx->tx_cpu; i++) { 2167 t = MVXPE_TX_DESC(sc, q, i); 2168 mvxpe_dump_txdesc(t, i); 2169 } 2170#endif 2171 mvxpe_ring_sync_tx(sc, q, start, used, 2172 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2173 2174 while (used > 255) { 2175 ptxsu = MVXPE_PTXSU_NOWD(255); 2176 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2177 used -= 255; 2178 } 2179 if (used > 0) { 2180 ptxsu = MVXPE_PTXSU_NOWD(used); 2181 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2182 } 2183 MVXPE_WRITE(sc, MVXPE_TQC, MVXPE_TQC_ENQ(q)); 2184 2185 DPRINTSC(sc, 2, 2186 "PTXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQA(q))); 2187 DPRINTSC(sc, 2, 2188 "PTXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXDQS(q))); 2189 DPRINTSC(sc, 2, 2190 "PTXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PTXS(q))); 2191 DPRINTSC(sc, 2, 2192 "PTXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PTXDI(q))); 2193 DPRINTSC(sc, 2, "TQC: %#x\n", MVXPE_READ(sc, MVXPE_TQC)); 2194 DPRINTIFNET(ifp, 2, 2195 "Tx: tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2196 tx->tx_cpu, tx->tx_dma, tx->tx_used); 2197 return 0; 2198} 2199 2200STATIC void 2201mvxpe_tx_set_csumflag(struct ifnet *ifp, 2202 struct mvxpe_tx_desc *t, struct mbuf *m) 2203{ 2204 struct ether_header *eh; 2205 int csum_flags; 2206 uint32_t iphl = 0, ipoff = 0; 2207 2208 2209 csum_flags = ifp->if_csum_flags_tx & m->m_pkthdr.csum_flags; 2210 2211 eh = mtod(m, struct ether_header *); 2212 switch (htons(eh->ether_type)) { 2213 case ETHERTYPE_IP: 2214 case ETHERTYPE_IPV6: 2215 ipoff = ETHER_HDR_LEN; 2216 break; 2217 case ETHERTYPE_VLAN: 2218 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2219 break; 2220 } 2221 2222 if (csum_flags & (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 2223 iphl = M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 2224 t->command |= MVXPE_TX_CMD_L3_IP4; 2225 } 2226 else if (csum_flags & (M_CSUM_TCPv6|M_CSUM_UDPv6)) { 2227 iphl = M_CSUM_DATA_IPv6_HL(m->m_pkthdr.csum_data); 2228 t->command |= MVXPE_TX_CMD_L3_IP6; 2229 } 2230 else { 2231 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2232 return; 2233 } 2234 2235 2236 /* L3 */ 2237 if (csum_flags & M_CSUM_IPv4) { 2238 t->command |= MVXPE_TX_CMD_IP4_CHECKSUM; 2239 } 2240 2241 /* L4 */ 2242 if ((csum_flags & 2243 (M_CSUM_TCPv4|M_CSUM_UDPv4|M_CSUM_TCPv6|M_CSUM_UDPv6)) == 0) { 2244 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NONE; 2245 } 2246 else if (csum_flags & M_CSUM_TCPv4) { 2247 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2248 t->command |= MVXPE_TX_CMD_L4_TCP; 2249 } 2250 else if (csum_flags & M_CSUM_UDPv4) { 2251 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2252 t->command |= MVXPE_TX_CMD_L4_UDP; 2253 } 2254 else if (csum_flags & M_CSUM_TCPv6) { 2255 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2256 t->command |= MVXPE_TX_CMD_L4_TCP; 2257 } 2258 else if (csum_flags & M_CSUM_UDPv6) { 2259 t->command |= MVXPE_TX_CMD_L4_CHECKSUM_NOFRAG; 2260 t->command |= MVXPE_TX_CMD_L4_UDP; 2261 } 2262 2263 t->l4ichk = 0; 2264 t->command |= MVXPE_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2265 t->command |= MVXPE_TX_CMD_L3_OFFSET(ipoff); 2266} 2267 2268STATIC void 2269mvxpe_tx_complete(struct mvxpe_softc *sc, uint32_t queues) 2270{ 2271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2272 int q; 2273 2274 DPRINTSC(sc, 2, "tx completed.\n"); 2275 2276 KASSERT_SC_MTX(sc); 2277 2278 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2279 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2280 continue; 2281 mvxpe_tx_lockq(sc, q); 2282 mvxpe_tx_queue_complete(sc, q); 2283 mvxpe_tx_unlockq(sc, q); 2284 } 2285 KASSERT(sc->sc_tx_pending >= 0); 2286 if (sc->sc_tx_pending == 0) 2287 ifp->if_timer = 0; 2288} 2289 2290STATIC void 2291mvxpe_tx_queue_complete(struct mvxpe_softc *sc, int q) 2292{ 2293 struct mvxpe_tx_ring *tx = MVXPE_TX_RING(sc, q); 2294 struct mvxpe_tx_desc *t; 2295 uint32_t ptxs, ptxsu, ndesc; 2296 int i; 2297 2298 KASSERT_TX_MTX(sc, q); 2299 2300 ptxs = MVXPE_READ(sc, MVXPE_PTXS(q)); 2301 ndesc = MVXPE_PTXS_GET_TBC(ptxs); 2302 if (ndesc == 0) 2303 return; 2304 2305 DPRINTSC(sc, 2, 2306 "tx complete queue %d, %d descriptors.\n", q, ndesc); 2307 2308 mvxpe_ring_sync_tx(sc, q, tx->tx_dma, ndesc, 2309 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2310 2311 for (i = 0; i < ndesc; i++) { 2312 int error = 0; 2313 2314 t = MVXPE_TX_DESC(sc, q, tx->tx_dma); 2315 if (t->flags & MVXPE_TX_F_ES) { 2316 DPRINTSC(sc, 1, 2317 "tx error queue %d desc %d\n", 2318 q, tx->tx_dma); 2319 switch (t->flags & MVXPE_TX_F_EC_MASK) { 2320 case MVXPE_TX_F_EC_LC: 2321 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_lc); 2322 break; 2323 case MVXPE_TX_F_EC_UR: 2324 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_ur); 2325 break; 2326 case MVXPE_TX_F_EC_RL: 2327 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_rl); 2328 break; 2329 default: 2330 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_txd_oth); 2331 break; 2332 } 2333 error = 1; 2334 } 2335 if (MVXPE_TX_MBUF(sc, q, tx->tx_dma) != NULL) { 2336 KASSERT((t->command & MVXPE_TX_CMD_F) != 0); 2337 bus_dmamap_unload(sc->sc_dmat, 2338 MVXPE_TX_MAP(sc, q, tx->tx_dma)); 2339 m_freem(MVXPE_TX_MBUF(sc, q, tx->tx_dma)); 2340 MVXPE_TX_MBUF(sc, q, tx->tx_dma) = NULL; 2341 sc->sc_tx_pending--; 2342 } 2343 else 2344 KASSERT((t->flags & MVXPE_TX_CMD_F) == 0); 2345 tx->tx_dma = tx_counter_adv(tx->tx_dma, 1); 2346 tx->tx_used--; 2347 if (error) 2348 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txqe[q]); 2349 else 2350 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_txq[q]); 2351 } 2352 KASSERT(tx->tx_used >= 0); 2353 KASSERT(tx->tx_used <= tx->tx_queue_len); 2354 while (ndesc > 255) { 2355 ptxsu = MVXPE_PTXSU_NORB(255); 2356 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2357 ndesc -= 255; 2358 } 2359 if (ndesc > 0) { 2360 ptxsu = MVXPE_PTXSU_NORB(ndesc); 2361 MVXPE_WRITE(sc, MVXPE_PTXSU(q), ptxsu); 2362 } 2363 DPRINTSC(sc, 2, 2364 "Tx complete q %d, tx_cpu = %d, tx_dma = %d, tx_used = %d\n", 2365 q, tx->tx_cpu, tx->tx_dma, tx->tx_used); 2366} 2367 2368/* 2369 * Rx Subroutines 2370 */ 2371STATIC void 2372mvxpe_rx(struct mvxpe_softc *sc, uint32_t queues) 2373{ 2374 int q, npkt; 2375 2376 KASSERT_SC_MTX(sc); 2377 2378 while ( (npkt = mvxpe_rx_queue_select(sc, queues, &q))) { 2379 /* mutex is held by rx_queue_select */ 2380 mvxpe_rx_queue(sc, q, npkt); 2381 mvxpe_rx_unlockq(sc, q); 2382 } 2383} 2384 2385STATIC void 2386mvxpe_rx_queue(struct mvxpe_softc *sc, int q, int npkt) 2387{ 2388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2389 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2390 struct mvxpe_rx_desc *r; 2391 struct mvxpbm_chunk *chunk; 2392 struct mbuf *m; 2393 uint32_t prxsu; 2394 int error = 0; 2395 int i; 2396 2397 KASSERT_RX_MTX(sc, q); 2398 2399 mvxpe_ring_sync_rx(sc, q, rx->rx_dma, npkt, 2400 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2401 2402 for (i = 0; i < npkt; i++) { 2403 /* get descriptor and packet */ 2404 chunk = MVXPE_RX_PKTBUF(sc, q, rx->rx_dma); 2405 MVXPE_RX_PKTBUF(sc, q, rx->rx_dma) = NULL; 2406 r = MVXPE_RX_DESC(sc, q, rx->rx_dma); 2407 mvxpbm_dmamap_sync(chunk, r->bytecnt, BUS_DMASYNC_POSTREAD); 2408 2409 /* check errors */ 2410 if (r->status & MVXPE_RX_ES) { 2411 switch (r->status & MVXPE_RX_EC_MASK) { 2412 case MVXPE_RX_EC_CE: 2413 DPRINTIFNET(ifp, 1, "CRC error\n"); 2414 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_ce); 2415 break; 2416 case MVXPE_RX_EC_OR: 2417 DPRINTIFNET(ifp, 1, "Rx FIFO overrun\n"); 2418 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_or); 2419 break; 2420 case MVXPE_RX_EC_MF: 2421 DPRINTIFNET(ifp, 1, "Rx too large frame\n"); 2422 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_mf); 2423 break; 2424 case MVXPE_RX_EC_RE: 2425 DPRINTIFNET(ifp, 1, "Rx resource error\n"); 2426 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_re); 2427 break; 2428 } 2429 error = 1; 2430 goto rx_done; 2431 } 2432 if (!(r->status & MVXPE_RX_F) || !(r->status & MVXPE_RX_L)) { 2433 DPRINTIFNET(ifp, 1, "not support scatter buf\n"); 2434 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_rxd_scat); 2435 error = 1; 2436 goto rx_done; 2437 } 2438 2439 if (chunk == NULL) { 2440 device_printf(sc->sc_dev, 2441 "got rx interrupt, but no chunk\n"); 2442 error = 1; 2443 goto rx_done; 2444 } 2445 2446 /* extract packet buffer */ 2447 if (mvxpbm_init_mbuf_hdr(chunk) != 0) { 2448 error = 1; 2449 goto rx_done; 2450 } 2451 m = chunk->m; 2452 m->m_pkthdr.rcvif = ifp; 2453 m->m_pkthdr.len = m->m_len = r->bytecnt - ETHER_CRC_LEN; 2454 m_adj(m, MVXPE_HWHEADER_SIZE); /* strip MH */ 2455 mvxpe_rx_set_csumflag(ifp, r, m); 2456 ifp->if_ipackets++; 2457 bpf_mtap(ifp, m); 2458 if_percpuq_enqueue(ifp->if_percpuq, m); 2459 chunk = NULL; /* the BM chunk goes to networking stack now */ 2460rx_done: 2461 if (chunk) { 2462 /* rx error. just return the chunk to BM. */ 2463 mvxpbm_free_chunk(chunk); 2464 } 2465 if (error) 2466 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxqe[q]); 2467 else 2468 MVXPE_EVCNT_INCR(&sc->sc_ev.ev_drv_rxq[q]); 2469 rx->rx_dma = rx_counter_adv(rx->rx_dma, 1); 2470 } 2471 /* DMA status update */ 2472 DPRINTSC(sc, 2, "%d packets received from queue %d\n", npkt, q); 2473 while (npkt > 255) { 2474 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2475 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2476 npkt -= 255; 2477 } 2478 if (npkt > 0) { 2479 prxsu = MVXPE_PRXSU_NOOFPROCESSEDDESCRIPTORS(npkt); 2480 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2481 } 2482 2483 DPRINTSC(sc, 2, 2484 "PRXDQA: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQA(q))); 2485 DPRINTSC(sc, 2, 2486 "PRXDQS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXDQS(q))); 2487 DPRINTSC(sc, 2, 2488 "PRXS: queue %d, %#x\n", q, MVXPE_READ(sc, MVXPE_PRXS(q))); 2489 DPRINTSC(sc, 2, 2490 "PRXDI: queue %d, %d\n", q, MVXPE_READ(sc, MVXPE_PRXDI(q))); 2491 DPRINTSC(sc, 2, "RQC: %#x\n", MVXPE_READ(sc, MVXPE_RQC)); 2492 DPRINTIFNET(ifp, 2, "Rx: rx_cpu = %d, rx_dma = %d\n", 2493 rx->rx_cpu, rx->rx_dma); 2494} 2495 2496STATIC int 2497mvxpe_rx_queue_select(struct mvxpe_softc *sc, uint32_t queues, int *queue) 2498{ 2499 uint32_t prxs, npkt; 2500 int q; 2501 2502 KASSERT_SC_MTX(sc); 2503 KASSERT(queue != NULL); 2504 DPRINTSC(sc, 2, "selecting rx queue\n"); 2505 2506 for (q = MVXPE_QUEUE_SIZE - 1; q >= 0; q--) { 2507 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2508 continue; 2509 2510 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2511 npkt = MVXPE_PRXS_GET_ODC(prxs); 2512 if (npkt == 0) 2513 continue; 2514 2515 DPRINTSC(sc, 2, 2516 "queue %d selected: prxs=%#x, %u pakcet received.\n", 2517 q, prxs, npkt); 2518 *queue = q; 2519 mvxpe_rx_lockq(sc, q); 2520 return npkt; 2521 } 2522 2523 return 0; 2524} 2525 2526STATIC void 2527mvxpe_rx_refill(struct mvxpe_softc *sc, uint32_t queues) 2528{ 2529 int q; 2530 2531 KASSERT_SC_MTX(sc); 2532 2533 /* XXX: check rx bit array */ 2534 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 2535 if (!MVXPE_IS_QUEUE_BUSY(queues, q)) 2536 continue; 2537 2538 mvxpe_rx_lockq(sc, q); 2539 mvxpe_rx_queue_refill(sc, q); 2540 mvxpe_rx_unlockq(sc, q); 2541 } 2542} 2543 2544STATIC void 2545mvxpe_rx_queue_refill(struct mvxpe_softc *sc, int q) 2546{ 2547 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2548 uint32_t prxs, prxsu, ndesc; 2549 int idx, refill = 0; 2550 int npkt; 2551 2552 KASSERT_RX_MTX(sc, q); 2553 2554 prxs = MVXPE_READ(sc, MVXPE_PRXS(q)); 2555 ndesc = MVXPE_PRXS_GET_NODC(prxs) + MVXPE_PRXS_GET_ODC(prxs); 2556 refill = rx->rx_queue_len - ndesc; 2557 if (refill <= 0) 2558 return; 2559 DPRINTPRXS(2, q); 2560 DPRINTSC(sc, 2, "%d buffers to refill.\n", refill); 2561 2562 idx = rx->rx_cpu; 2563 for (npkt = 0; npkt < refill; npkt++) 2564 if (mvxpe_rx_queue_add(sc, q) != 0) 2565 break; 2566 DPRINTSC(sc, 2, "queue %d, %d buffer refilled.\n", q, npkt); 2567 if (npkt == 0) 2568 return; 2569 2570 mvxpe_ring_sync_rx(sc, q, idx, npkt, 2571 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2572 2573 while (npkt > 255) { 2574 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(255); 2575 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2576 npkt -= 255; 2577 } 2578 if (npkt > 0) { 2579 prxsu = MVXPE_PRXSU_NOOFNEWDESCRIPTORS(npkt); 2580 MVXPE_WRITE(sc, MVXPE_PRXSU(q), prxsu); 2581 } 2582 DPRINTPRXS(2, q); 2583 return; 2584} 2585 2586STATIC int 2587mvxpe_rx_queue_add(struct mvxpe_softc *sc, int q) 2588{ 2589 struct mvxpe_rx_ring *rx = MVXPE_RX_RING(sc, q); 2590 struct mvxpe_rx_desc *r; 2591 struct mvxpbm_chunk *chunk = NULL; 2592 2593 KASSERT_RX_MTX(sc, q); 2594 2595 /* Allocate the packet buffer */ 2596 chunk = mvxpbm_alloc(sc->sc_bm); 2597 if (chunk == NULL) { 2598 DPRINTSC(sc, 1, "BM chunk allocation failed.\n"); 2599 return ENOBUFS; 2600 } 2601 2602 /* Add the packet to descritor */ 2603 KASSERT(MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) == NULL); 2604 MVXPE_RX_PKTBUF(sc, q, rx->rx_cpu) = chunk; 2605 mvxpbm_dmamap_sync(chunk, BM_SYNC_ALL, BUS_DMASYNC_PREREAD); 2606 2607 r = MVXPE_RX_DESC(sc, q, rx->rx_cpu); 2608 r->bufptr = chunk->buf_pa; 2609 DPRINTSC(sc, 9, "chunk added to index %d\n", rx->rx_cpu); 2610 rx->rx_cpu = rx_counter_adv(rx->rx_cpu, 1); 2611 return 0; 2612} 2613 2614STATIC void 2615mvxpe_rx_set_csumflag(struct ifnet *ifp, 2616 struct mvxpe_rx_desc *r, struct mbuf *m0) 2617{ 2618 uint32_t csum_flags = 0; 2619 2620 if ((r->status & (MVXPE_RX_IP_HEADER_OK|MVXPE_RX_L3_IP)) == 0) 2621 return; /* not a IP packet */ 2622 2623 /* L3 */ 2624 if (r->status & MVXPE_RX_L3_IP) { 2625 csum_flags |= M_CSUM_IPv4; 2626 if ((r->status & MVXPE_RX_IP_HEADER_OK) == 0) { 2627 csum_flags |= M_CSUM_IPv4_BAD; 2628 goto finish; 2629 } 2630 else if (r->status & MVXPE_RX_IPV4_FRAGMENT) { 2631 /* 2632 * r->l4chk has partial checksum of each framgment. 2633 * but there is no way to use it in NetBSD. 2634 */ 2635 return; 2636 } 2637 } 2638 2639 /* L4 */ 2640 switch (r->status & MVXPE_RX_L4_MASK) { 2641 case MVXPE_RX_L4_TCP: 2642 if (r->status & MVXPE_RX_L3_IP) 2643 csum_flags |= M_CSUM_TCPv4; 2644 else 2645 csum_flags |= M_CSUM_TCPv6; 2646 if ((r->status & MVXPE_RX_L4_CHECKSUM_OK) == 0) 2647 csum_flags |= M_CSUM_TCP_UDP_BAD; 2648 break; 2649 case MVXPE_RX_L4_UDP: 2650 if (r->status & MVXPE_RX_L3_IP) 2651 csum_flags |= M_CSUM_UDPv4; 2652 else 2653 csum_flags |= M_CSUM_UDPv6; 2654 if ((r->status & MVXPE_RX_L4_CHECKSUM_OK) == 0) 2655 csum_flags |= M_CSUM_TCP_UDP_BAD; 2656 break; 2657 case MVXPE_RX_L4_OTH: 2658 default: 2659 break; 2660 } 2661finish: 2662 m0->m_pkthdr.csum_flags |= (csum_flags & ifp->if_csum_flags_rx); 2663} 2664 2665/* 2666 * MAC address filter 2667 */ 2668STATIC uint8_t 2669mvxpe_crc8(const uint8_t *data, size_t size) 2670{ 2671 int bit; 2672 uint8_t byte; 2673 uint8_t crc = 0; 2674 const uint8_t poly = 0x07; 2675 2676 while(size--) 2677 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 2678 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 2679 2680 return crc; 2681} 2682 2683CTASSERT(MVXPE_NDFSMT == MVXPE_NDFOMT); 2684 2685STATIC void 2686mvxpe_filter_setup(struct mvxpe_softc *sc) 2687{ 2688 struct ethercom *ec = &sc->sc_ethercom; 2689 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 2690 struct ether_multi *enm; 2691 struct ether_multistep step; 2692 uint32_t dfut[MVXPE_NDFUT], dfsmt[MVXPE_NDFSMT], dfomt[MVXPE_NDFOMT]; 2693 uint32_t pxc; 2694 int i; 2695 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 2696 2697 KASSERT_SC_MTX(sc); 2698 2699 memset(dfut, 0, sizeof(dfut)); 2700 memset(dfsmt, 0, sizeof(dfsmt)); 2701 memset(dfomt, 0, sizeof(dfomt)); 2702 2703 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2704 goto allmulti; 2705 } 2706 2707 ETHER_FIRST_MULTI(step, ec, enm); 2708 while (enm != NULL) { 2709 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2710 /* ranges are complex and somewhat rare */ 2711 goto allmulti; 2712 } 2713 /* chip handles some IPv4 multicast specially */ 2714 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 2715 i = enm->enm_addrlo[5]; 2716 dfsmt[i>>2] |= 2717 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2718 } else { 2719 i = mvxpe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 2720 dfomt[i>>2] |= 2721 MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2722 } 2723 2724 ETHER_NEXT_MULTI(step, enm); 2725 } 2726 goto set; 2727 2728allmulti: 2729 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 2730 for (i = 0; i < MVXPE_NDFSMT; i++) { 2731 dfsmt[i] = dfomt[i] = 2732 MVXPE_DF(0, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2733 MVXPE_DF(1, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2734 MVXPE_DF(2, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS) | 2735 MVXPE_DF(3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2736 } 2737 } 2738 2739set: 2740 pxc = MVXPE_READ(sc, MVXPE_PXC); 2741 pxc &= ~MVXPE_PXC_UPM; 2742 pxc |= MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP; 2743 if (ifp->if_flags & IFF_BROADCAST) { 2744 pxc &= ~(MVXPE_PXC_RB | MVXPE_PXC_RBIP | MVXPE_PXC_RBARP); 2745 } 2746 if (ifp->if_flags & IFF_PROMISC) { 2747 pxc |= MVXPE_PXC_UPM; 2748 } 2749 MVXPE_WRITE(sc, MVXPE_PXC, pxc); 2750 2751 /* Set Destination Address Filter Unicast Table */ 2752 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2753 dfut[i>>2] = MVXPE_DF(i&3, MVXPE_DF_QUEUE_ALL | MVXPE_DF_PASS); 2754 MVXPE_WRITE_REGION(sc, MVXPE_DFUT(0), dfut, MVXPE_NDFUT); 2755 2756 /* Set Destination Address Filter Multicast Tables */ 2757 MVXPE_WRITE_REGION(sc, MVXPE_DFSMT(0), dfsmt, MVXPE_NDFSMT); 2758 MVXPE_WRITE_REGION(sc, MVXPE_DFOMT(0), dfomt, MVXPE_NDFOMT); 2759} 2760 2761/* 2762 * sysctl(9) 2763 */ 2764SYSCTL_SETUP(sysctl_mvxpe, "sysctl mvxpe subtree setup") 2765{ 2766 int rc; 2767 const struct sysctlnode *node; 2768 2769 if ((rc = sysctl_createv(clog, 0, NULL, &node, 2770 0, CTLTYPE_NODE, "mvxpe", 2771 SYSCTL_DESCR("mvxpe interface controls"), 2772 NULL, 0, NULL, 0, 2773 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 2774 goto err; 2775 } 2776 2777 mvxpe_root_num = node->sysctl_num; 2778 return; 2779 2780err: 2781 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 2782} 2783 2784STATIC int 2785sysctl_read_mib(SYSCTLFN_ARGS) 2786{ 2787 struct mvxpe_sysctl_mib *arg; 2788 struct mvxpe_softc *sc; 2789 struct sysctlnode node; 2790 uint64_t val; 2791 int err; 2792 2793 node = *rnode; 2794 arg = (struct mvxpe_sysctl_mib *)rnode->sysctl_data; 2795 if (arg == NULL) 2796 return EINVAL; 2797 2798 sc = arg->sc; 2799 if (sc == NULL) 2800 return EINVAL; 2801 if (arg->index < 0 || arg->index > __arraycount(mvxpe_mib_list)) 2802 return EINVAL; 2803 2804 mvxpe_sc_lock(sc); 2805 val = arg->counter; 2806 mvxpe_sc_unlock(sc); 2807 2808 node.sysctl_data = &val; 2809 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2810 if (err) 2811 return err; 2812 if (newp) 2813 return EINVAL; 2814 2815 return 0; 2816} 2817 2818 2819STATIC int 2820sysctl_clear_mib(SYSCTLFN_ARGS) 2821{ 2822 struct mvxpe_softc *sc; 2823 struct sysctlnode node; 2824 int val; 2825 int err; 2826 2827 node = *rnode; 2828 sc = (struct mvxpe_softc *)rnode->sysctl_data; 2829 if (sc == NULL) 2830 return EINVAL; 2831 2832 val = 0; 2833 node.sysctl_data = &val; 2834 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2835 if (err || newp == NULL) 2836 return err; 2837 if (val < 0 || val > 1) 2838 return EINVAL; 2839 if (val == 1) { 2840 mvxpe_sc_lock(sc); 2841 mvxpe_clear_mib(sc); 2842 mvxpe_sc_unlock(sc); 2843 } 2844 2845 return 0; 2846} 2847 2848STATIC int 2849sysctl_set_queue_length(SYSCTLFN_ARGS) 2850{ 2851 struct mvxpe_sysctl_queue *arg; 2852 struct mvxpe_rx_ring *rx = NULL; 2853 struct mvxpe_tx_ring *tx = NULL; 2854 struct mvxpe_softc *sc; 2855 struct sysctlnode node; 2856 uint32_t reg; 2857 int val; 2858 int err; 2859 2860 node = *rnode; 2861 2862 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2863 if (arg == NULL) 2864 return EINVAL; 2865 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2866 return EINVAL; 2867 if (arg->rxtx != MVXPE_SYSCTL_RX && arg->rxtx != MVXPE_SYSCTL_TX) 2868 return EINVAL; 2869 2870 sc = arg->sc; 2871 if (sc == NULL) 2872 return EINVAL; 2873 2874 /* read queue length */ 2875 mvxpe_sc_lock(sc); 2876 switch (arg->rxtx) { 2877 case MVXPE_SYSCTL_RX: 2878 mvxpe_rx_lockq(sc, arg->queue); 2879 rx = MVXPE_RX_RING(sc, arg->queue); 2880 val = rx->rx_queue_len; 2881 mvxpe_rx_unlockq(sc, arg->queue); 2882 break; 2883 case MVXPE_SYSCTL_TX: 2884 mvxpe_tx_lockq(sc, arg->queue); 2885 tx = MVXPE_TX_RING(sc, arg->queue); 2886 val = tx->tx_queue_len; 2887 mvxpe_tx_unlockq(sc, arg->queue); 2888 break; 2889 } 2890 2891 node.sysctl_data = &val; 2892 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2893 if (err || newp == NULL) { 2894 mvxpe_sc_unlock(sc); 2895 return err; 2896 } 2897 2898 /* update queue length */ 2899 if (val < 8 || val > MVXPE_RX_RING_CNT) { 2900 mvxpe_sc_unlock(sc); 2901 return EINVAL; 2902 } 2903 switch (arg->rxtx) { 2904 case MVXPE_SYSCTL_RX: 2905 mvxpe_rx_lockq(sc, arg->queue); 2906 rx->rx_queue_len = val; 2907 rx->rx_queue_th_received = 2908 rx->rx_queue_len / MVXPE_RXTH_RATIO; 2909 rx->rx_queue_th_free = 2910 rx->rx_queue_len / MVXPE_RXTH_REFILL_RATIO; 2911 2912 reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received); 2913 reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free); 2914 MVXPE_WRITE(sc, MVXPE_PRXDQTH(arg->queue), reg); 2915 2916 mvxpe_rx_unlockq(sc, arg->queue); 2917 break; 2918 case MVXPE_SYSCTL_TX: 2919 mvxpe_tx_lockq(sc, arg->queue); 2920 tx->tx_queue_len = val; 2921 tx->tx_queue_th_free = 2922 tx->tx_queue_len / MVXPE_TXTH_RATIO; 2923 2924 reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free); 2925 reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT); 2926 MVXPE_WRITE(sc, MVXPE_PTXDQS(arg->queue), reg); 2927 2928 mvxpe_tx_unlockq(sc, arg->queue); 2929 break; 2930 } 2931 mvxpe_sc_unlock(sc); 2932 2933 return 0; 2934} 2935 2936STATIC int 2937sysctl_set_queue_rxthtime(SYSCTLFN_ARGS) 2938{ 2939 struct mvxpe_sysctl_queue *arg; 2940 struct mvxpe_rx_ring *rx = NULL; 2941 struct mvxpe_softc *sc; 2942 struct sysctlnode node; 2943 extern uint32_t mvTclk; 2944 uint32_t reg, time_mvtclk; 2945 int time_us; 2946 int err; 2947 2948 node = *rnode; 2949 2950 arg = (struct mvxpe_sysctl_queue *)rnode->sysctl_data; 2951 if (arg == NULL) 2952 return EINVAL; 2953 if (arg->queue < 0 || arg->queue > MVXPE_RX_RING_CNT) 2954 return EINVAL; 2955 if (arg->rxtx != MVXPE_SYSCTL_RX) 2956 return EINVAL; 2957 2958 sc = arg->sc; 2959 if (sc == NULL) 2960 return EINVAL; 2961 2962 /* read queue length */ 2963 mvxpe_sc_lock(sc); 2964 mvxpe_rx_lockq(sc, arg->queue); 2965 rx = MVXPE_RX_RING(sc, arg->queue); 2966 time_mvtclk = rx->rx_queue_th_time; 2967 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvTclk; 2968 node.sysctl_data = &time_us; 2969 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", 2970 arg->queue, MVXPE_READ(sc, MVXPE_PRXITTH(arg->queue))); 2971 err = sysctl_lookup(SYSCTLFN_CALL(&node)); 2972 if (err || newp == NULL) { 2973 mvxpe_rx_unlockq(sc, arg->queue); 2974 mvxpe_sc_unlock(sc); 2975 return err; 2976 } 2977 2978 /* update queue length (0[sec] - 1[sec]) */ 2979 if (time_us < 0 || time_us > (1000 * 1000)) { 2980 mvxpe_rx_unlockq(sc, arg->queue); 2981 mvxpe_sc_unlock(sc); 2982 return EINVAL; 2983 } 2984 time_mvtclk = 2985 (uint64_t)mvTclk * (uint64_t)time_us / (1000ULL * 1000ULL); 2986 rx->rx_queue_th_time = time_mvtclk; 2987 reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time); 2988 MVXPE_WRITE(sc, MVXPE_PRXITTH(arg->queue), reg); 2989 DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", arg->queue, reg); 2990 mvxpe_rx_unlockq(sc, arg->queue); 2991 mvxpe_sc_unlock(sc); 2992 2993 return 0; 2994} 2995 2996 2997STATIC void 2998sysctl_mvxpe_init(struct mvxpe_softc *sc) 2999{ 3000 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3001 const struct sysctlnode *node; 3002 int mvxpe_nodenum; 3003 int mvxpe_mibnum; 3004 int mvxpe_rxqueuenum; 3005 int mvxpe_txqueuenum; 3006 int q, i; 3007 3008 /* hw.mvxpe.mvxpe[unit] */ 3009 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3010 0, CTLTYPE_NODE, ifp->if_xname, 3011 SYSCTL_DESCR("mvxpe per-controller controls"), 3012 NULL, 0, NULL, 0, 3013 CTL_HW, mvxpe_root_num, CTL_CREATE, 3014 CTL_EOL) != 0) { 3015 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3016 return; 3017 } 3018 mvxpe_nodenum = node->sysctl_num; 3019 3020 /* hw.mvxpe.mvxpe[unit].mib */ 3021 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3022 0, CTLTYPE_NODE, "mib", 3023 SYSCTL_DESCR("mvxpe per-controller MIB counters"), 3024 NULL, 0, NULL, 0, 3025 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3026 CTL_EOL) != 0) { 3027 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3028 return; 3029 } 3030 mvxpe_mibnum = node->sysctl_num; 3031 3032 /* hw.mvxpe.mvxpe[unit].rx */ 3033 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3034 0, CTLTYPE_NODE, "rx", 3035 SYSCTL_DESCR("Rx Queues"), 3036 NULL, 0, NULL, 0, 3037 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3038 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3039 return; 3040 } 3041 mvxpe_rxqueuenum = node->sysctl_num; 3042 3043 /* hw.mvxpe.mvxpe[unit].tx */ 3044 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3045 0, CTLTYPE_NODE, "tx", 3046 SYSCTL_DESCR("Tx Queues"), 3047 NULL, 0, NULL, 0, 3048 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, CTL_EOL) != 0) { 3049 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3050 return; 3051 } 3052 mvxpe_txqueuenum = node->sysctl_num; 3053 3054#ifdef MVXPE_DEBUG 3055 /* hw.mvxpe.debug */ 3056 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3057 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 3058 SYSCTL_DESCR("mvgbe device driver debug control"), 3059 NULL, 0, &mvxpe_debug, 0, 3060 CTL_HW, mvxpe_root_num, CTL_CREATE, CTL_EOL) != 0) { 3061 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3062 return; 3063 } 3064#endif 3065 /* 3066 * MIB access 3067 */ 3068 /* hw.mvxpe.mvxpe[unit].mib.<mibs> */ 3069 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3070 const char *name = mvxpe_mib_list[i].sysctl_name; 3071 const char *desc = mvxpe_mib_list[i].desc; 3072 struct mvxpe_sysctl_mib *mib_arg = &sc->sc_sysctl_mib[i]; 3073 3074 mib_arg->sc = sc; 3075 mib_arg->index = i; 3076 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3077 CTLFLAG_READONLY, CTLTYPE_QUAD, name, desc, 3078 sysctl_read_mib, 0, (void *)mib_arg, 0, 3079 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_mibnum, 3080 CTL_CREATE, CTL_EOL) != 0) { 3081 aprint_normal_dev(sc->sc_dev, 3082 "couldn't create sysctl node\n"); 3083 break; 3084 } 3085 } 3086 3087 for (q = 0; q < MVXPE_QUEUE_SIZE; q++) { 3088 struct mvxpe_sysctl_queue *rxarg = &sc->sc_sysctl_rx_queue[q]; 3089 struct mvxpe_sysctl_queue *txarg = &sc->sc_sysctl_tx_queue[q]; 3090#define MVXPE_SYSCTL_NAME(num) "queue" # num 3091 static const char *sysctl_queue_names[] = { 3092 MVXPE_SYSCTL_NAME(0), MVXPE_SYSCTL_NAME(1), 3093 MVXPE_SYSCTL_NAME(2), MVXPE_SYSCTL_NAME(3), 3094 MVXPE_SYSCTL_NAME(4), MVXPE_SYSCTL_NAME(5), 3095 MVXPE_SYSCTL_NAME(6), MVXPE_SYSCTL_NAME(7), 3096 }; 3097#undef MVXPE_SYSCTL_NAME 3098#ifdef SYSCTL_INCLUDE_DESCR 3099#define MVXPE_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3100 static const char *sysctl_queue_descrs[] = { 3101 MVXPE_SYSCTL_DESC(0), MVXPE_SYSCTL_DESC(1), 3102 MVXPE_SYSCTL_DESC(2), MVXPE_SYSCTL_DESC(3), 3103 MVXPE_SYSCTL_DESC(4), MVXPE_SYSCTL_DESC(5), 3104 MVXPE_SYSCTL_DESC(6), MVXPE_SYSCTL_DESC(7), 3105 }; 3106#undef MVXPE_SYSCTL_DESCR 3107#endif /* SYSCTL_INCLUDE_DESCR */ 3108 int mvxpe_curnum; 3109 3110 rxarg->sc = txarg->sc = sc; 3111 rxarg->queue = txarg->queue = q; 3112 rxarg->rxtx = MVXPE_SYSCTL_RX; 3113 txarg->rxtx = MVXPE_SYSCTL_TX; 3114 3115 /* hw.mvxpe.mvxpe[unit].rx.[queue] */ 3116 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3117 0, CTLTYPE_NODE, 3118 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descrs[q]), 3119 NULL, 0, NULL, 0, 3120 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3121 CTL_CREATE, CTL_EOL) != 0) { 3122 aprint_normal_dev(sc->sc_dev, 3123 "couldn't create sysctl node\n"); 3124 break; 3125 } 3126 mvxpe_curnum = node->sysctl_num; 3127 3128 /* hw.mvxpe.mvxpe[unit].rx.[queue].length */ 3129 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3130 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3131 SYSCTL_DESCR("maximum length of the queue"), 3132 sysctl_set_queue_length, 0, (void *)rxarg, 0, 3133 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3134 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3135 aprint_normal_dev(sc->sc_dev, 3136 "couldn't create sysctl node\n"); 3137 break; 3138 } 3139 3140 /* hw.mvxpe.mvxpe[unit].rx.[queue].threshold_timer_us */ 3141 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3142 CTLFLAG_READWRITE, CTLTYPE_INT, "threshold_timer_us", 3143 SYSCTL_DESCR("interrupt coalescing threshold timer [us]"), 3144 sysctl_set_queue_rxthtime, 0, (void *)rxarg, 0, 3145 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_rxqueuenum, 3146 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3147 aprint_normal_dev(sc->sc_dev, 3148 "couldn't create sysctl node\n"); 3149 break; 3150 } 3151 3152 /* hw.mvxpe.mvxpe[unit].tx.[queue] */ 3153 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3154 0, CTLTYPE_NODE, 3155 sysctl_queue_names[q], SYSCTL_DESCR(sysctl_queue_descs[q]), 3156 NULL, 0, NULL, 0, 3157 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3158 CTL_CREATE, CTL_EOL) != 0) { 3159 aprint_normal_dev(sc->sc_dev, 3160 "couldn't create sysctl node\n"); 3161 break; 3162 } 3163 mvxpe_curnum = node->sysctl_num; 3164 3165 /* hw.mvxpe.mvxpe[unit].tx.length[queue] */ 3166 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3167 CTLFLAG_READWRITE, CTLTYPE_INT, "length", 3168 SYSCTL_DESCR("maximum length of the queue"), 3169 sysctl_set_queue_length, 0, (void *)txarg, 0, 3170 CTL_HW, mvxpe_root_num, mvxpe_nodenum, mvxpe_txqueuenum, 3171 mvxpe_curnum, CTL_CREATE, CTL_EOL) != 0) { 3172 aprint_normal_dev(sc->sc_dev, 3173 "couldn't create sysctl node\n"); 3174 break; 3175 } 3176 } 3177 3178 /* hw.mvxpe.mvxpe[unit].clear_mib */ 3179 if (sysctl_createv(&sc->sc_mvxpe_clog, 0, NULL, &node, 3180 CTLFLAG_READWRITE, CTLTYPE_INT, "clear_mib", 3181 SYSCTL_DESCR("mvgbe device driver debug control"), 3182 sysctl_clear_mib, 0, (void *)sc, 0, 3183 CTL_HW, mvxpe_root_num, mvxpe_nodenum, CTL_CREATE, 3184 CTL_EOL) != 0) { 3185 aprint_normal_dev(sc->sc_dev, "couldn't create sysctl node\n"); 3186 return; 3187 } 3188 3189} 3190 3191/* 3192 * MIB 3193 */ 3194STATIC void 3195mvxpe_clear_mib(struct mvxpe_softc *sc) 3196{ 3197 int i; 3198 3199 KASSERT_SC_MTX(sc); 3200 3201 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3202 if (mvxpe_mib_list[i].reg64) 3203 MVXPE_READ_MIB(sc, (mvxpe_mib_list[i].regnum + 4)); 3204 MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3205 sc->sc_sysctl_mib[i].counter = 0; 3206 } 3207} 3208 3209STATIC void 3210mvxpe_update_mib(struct mvxpe_softc *sc) 3211{ 3212 int i; 3213 3214 KASSERT_SC_MTX(sc); 3215 3216 for (i = 0; i < __arraycount(mvxpe_mib_list); i++) { 3217 uint32_t val_hi; 3218 uint32_t val_lo; 3219 3220 if (mvxpe_mib_list[i].reg64) { 3221 /* XXX: implement bus_space_read_8() */ 3222 val_lo = MVXPE_READ_MIB(sc, 3223 (mvxpe_mib_list[i].regnum + 4)); 3224 val_hi = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3225 } 3226 else { 3227 val_lo = MVXPE_READ_MIB(sc, mvxpe_mib_list[i].regnum); 3228 val_hi = 0; 3229 } 3230 3231 if ((val_lo | val_hi) == 0) 3232 continue; 3233 3234 sc->sc_sysctl_mib[i].counter += 3235 ((uint64_t)val_hi << 32) | (uint64_t)val_lo; 3236 } 3237} 3238 3239/* 3240 * for Debug 3241 */ 3242STATIC void 3243mvxpe_dump_txdesc(struct mvxpe_tx_desc *desc, int idx) 3244{ 3245#define DESC_PRINT(X) \ 3246 if (X) \ 3247 printf("txdesc[%d]." #X "=%#x\n", idx, X); 3248 3249 DESC_PRINT(desc->command); 3250 DESC_PRINT(desc->l4ichk); 3251 DESC_PRINT(desc->bytecnt); 3252 DESC_PRINT(desc->bufptr); 3253 DESC_PRINT(desc->flags); 3254#undef DESC_PRINT 3255} 3256 3257STATIC void 3258mvxpe_dump_rxdesc(struct mvxpe_rx_desc *desc, int idx) 3259{ 3260#define DESC_PRINT(X) \ 3261 if (X) \ 3262 printf("rxdesc[%d]." #X "=%#x\n", idx, X); 3263 3264 DESC_PRINT(desc->status); 3265 DESC_PRINT(desc->bytecnt); 3266 DESC_PRINT(desc->bufptr); 3267 DESC_PRINT(desc->l4chk); 3268#undef DESC_PRINT 3269} 3270