1/* $NetBSD: gtethreg.h,v 1.6 2021/11/10 17:19:30 msaitoh Exp $ */ 2 3/* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#ifndef _DEV_GTETHREG_H_ 41#define _DEV_GTETHREG_H_ 42 43#define ETH__BIT(bit) (1U << (bit)) 44#define ETH__LLBIT(bit) (1LLU << (bit)) 45#define ETH__MASK(bit) (ETH__BIT(bit) - 1) 46#define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) 47#define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) 48#define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) 49#define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) 50#define ETH__INS(new, bit) ((new) << (bit)) 51#define ETH__LLINS(new, bit) ((uint64_t)(new) << (bit)) 52 53/* 54 * Descriptors used for both receive & transmit data. Note that the descriptor 55 * must start on a 4LW boundary. Since the GT accesses the descriptor as 56 * two 64-bit quantities, we must present them 32bit quantities in the right 57 * order based on endianness. 58 */ 59 60struct gt_eth_desc { 61#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 62 u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ 63 u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ 64 u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ 65 u_int32_t ed_bufptr; /* pointer to packet buffer */ 66#endif 67#if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN 68 u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ 69 u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ 70 u_int32_t ed_bufptr; /* pointer to packet buffer */ 71 u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ 72#endif 73}; 74 75/* Table 578: Ethernet TX Descriptor - Command/Status word 76 * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, 77 * otherwise should be 0 (tx). 78 */ 79#define TX_STS_LC ETH__BIT(5) /* Late Collision */ 80#define TX_STS_UR ETH__BIT(6) /* Underrun error */ 81#define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ 82#define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ 83#define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ 84#define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ 85#define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ 86#define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ 87#define TX_CMD_P ETH__BIT(18) /* Pad Packet */ 88#define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ 89#define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ 90#define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ 91#define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ 92 93#define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) 94#define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) 95 96/* Table 582: Ethernet RX Descriptor - Command/Status Word 97 * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, 98 * otherwise should be ignored (rx). 99 */ 100#define RX_STS_CE ETH__BIT(0) /* CRC Error */ 101#define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ 102#define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ 103#define RX_STS_OR ETH__BIT(6) /* Overrun Error */ 104#define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ 105#define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ 106#define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ 107#define RX_STS_M ETH__BIT(12) /* Missed Frame */ 108#define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ 109#define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ 110#define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ 111#define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ 112#define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ 113#define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ 114#define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ 115#define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ 116 117/* Table 586: Hash Table Entry Fields 118 */ 119#define HSH_V ETH__LLBIT(0) /* Entry is valid */ 120#define HSH_S ETH__LLBIT(1) /* Skip this entry */ 121#define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ 122#define HSH_R ETH__LLBIT(2) /* Receive(1) */ 123#define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) 124#define HSH_PRIO_INS(v) ETH__LLINS(v, 51) 125#define HSH_ADDR_MASK 0x7fffff8LLU 126#define HSH_LIMIT 12 127 128 129#define ETHC_SIZE 0x4000 /* Register Space */ 130 131#define ETH_EPAR 0x2000 /* PHY Address Register */ 132#define ETH_ESMIR 0x2010 /* SMI Register */ 133 134#define ETH_BASE(u) (ETH0_BASE + ((u) << 10)) /* Ethernet Register Base */ 135#define ETH_NUM 3 136#define ETH_SIZE 0x0400 /* Register Space */ 137 138#define ETH_EBASE 0x0000 /* Base of Registers */ 139#define ETH_EPCR 0x0000 /* Port Config. Register */ 140#define ETH_EPCXR 0x0008 /* Port Config. Extend Reg */ 141#define ETH_EPCMR 0x0010 /* Port Command Register */ 142#define ETH_EPSR 0x0018 /* Port Status Register */ 143#define ETH_ESPR 0x0020 /* Port Serial Parameters Reg */ 144#define ETH_EHTPR 0x0028 /* Port Hash Table Pointer Reg*/ 145#define ETH_EFCSAL 0x0030 /* Flow Control Src Addr Low */ 146#define ETH_EFCSAH 0x0038 /* Flow Control Src Addr High */ 147#define ETH_ESDCR 0x0040 /* SDMA Configuration Reg */ 148#define ETH_ESDCMR 0x0048 /* SDMA Command Register */ 149#define ETH_EICR 0x0050 /* Interrupt Cause Register */ 150#define ETH_EIMR 0x0058 /* Interrupt Mask Register */ 151#define ETH_EFRDP0 0x0080 /* First Rx Desc Pointer 0 */ 152#define ETH_EFRDP1 0x0084 /* First Rx Desc Pointer 1 */ 153#define ETH_EFRDP2 0x0088 /* First Rx Desc Pointer 2 */ 154#define ETH_EFRDP3 0x008c /* First Rx Desc Pointer 3 */ 155#define ETH_ECRDP0 0x00a0 /* Current Rx Desc Pointer 0 */ 156#define ETH_ECRDP1 0x00a4 /* Current Rx Desc Pointer 1 */ 157#define ETH_ECRDP2 0x00a8 /* Current Rx Desc Pointer 2 */ 158#define ETH_ECRDP3 0x00ac /* Current Rx Desc Pointer 3 */ 159#define ETH_ECTDP0 0x00e0 /* Current Tx Desc Pointer 0 */ 160#define ETH_ECTDP1 0x00e4 /* Current Tx Desc Pointer 1 */ 161#define ETH_EDSCP2P0L 0x0060 /* IP Differentiated Services 162 CodePoint to Priority0 low */ 163#define ETH_EDSCP2P0H 0x0064 /* IP Differentiated Services 164 CodePoint to Priority0 high*/ 165#define ETH_EDSCP2P1L 0x0068 /* IP Differentiated Services 166 CodePoint to Priority1 low */ 167#define ETH_EDSCP2P1H 0x006c /* IP Differentiated Services 168 CodePoint to Priority1 high*/ 169#define ETH_EVPT2P 0x0068 /* VLAN Prio. Tag to Priority */ 170#define ETH_EMIBCTRS 0x0100 /* MIB Counters */ 171 172 173#define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) 174 175#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ 176 ETH__INS(reg, 21)|\ 177 ETH_ESMIR_ReadOpcode) 178#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ 179 ETH__INS(reg, 21)|\ 180 ETH__INS(val, 0)|\ 181 ETH_ESMIR_WriteOpcode) 182#define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) 183#define ETH_ESMIR_WriteOpcode 0 184#define ETH_ESMIR_ReadOpcode ETH__BIT(26) 185#define ETH_ESMIR_ReadValid ETH__BIT(27) 186#define ETH_ESMIR_Busy ETH__BIT(28) 187 188/* 189 * Table 597: Port Configuration Register (PCR) 190 * 00:00 PM Promiscuous mode 191 * 0: Normal mode (Frames are only received if the 192 * destination address is found in the hash 193 * table) 194 * 1: Promiscuous mode (Frames are received 195 * regardless of their destination address. 196 * Errored frames are discarded unless the Port 197 * Configuration register's PBF bit is set) 198 * 01:01 RBM Reject Broadcast Mode 199 * 0: Receive broadcast address 200 * 1: Reject frames with broadcast address 201 * Overridden by the promiscuous mode. 202 * 02:02 PBF Pass Bad Frames 203 * (0: Normal mode, 1: Pass bad Frames) 204 * The Ethernet receiver passes to the CPU errored 205 * frames (like fragments and collided packets) 206 * that are normally rejected. 207 * NOTE: Frames are only passed if they 208 * successfully pass address filtering. 209 * 06:03 Reserved 210 * 07:07 EN Enable (0: Disabled, 1: Enable) 211 * When enabled, the ethernet port is ready to 212 * transmit/receive. 213 * 09:08 LPBK Loop Back Mode 214 * 00: Normal mode 215 * 01: Internal loop back mode (TX data is looped 216 * back to the RX lines. No transition is seen 217 * on the interface pins) 218 * 10: External loop back mode (TX data is looped 219 * back to the RX lines and also transmitted 220 * out to the MII interface pins) 221 * 11: Reserved 222 * 10:10 FC Force Collision 223 * 0: Normal mode. 224 * 1: Force Collision on any TX frame. 225 * For RXM test (in Loopback mode). 226 * 11:11 Reserved. 227 * 12:12 HS Hash Size 228 * 0: 8K address filtering 229 * (256KB of memory space required). 230 * 1: 512 address filtering 231 * ( 16KB of memory space required). 232 * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) 233 * 14:14 HDM Hash Default Mode 234 * 0: Discard addresses not found in address table 235 * 1: Pass addresses not found in address table 236 * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) 237 * NOTE: Valid only when auto-negotiation for 238 * duplex mode is disabled. 239 * 30:16 Reserved 240 * 31:31 ACCS Accelerate Slot Time 241 * (0: Normal mode, 1: Reserved) 242 */ 243#define ETH_EPCR_PM ETH__BIT(0) 244#define ETH_EPCR_RBM ETH__BIT(1) 245#define ETH_EPCR_PBF ETH__BIT(2) 246#define ETH_EPCR_EN ETH__BIT(7) 247#define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) 248#define ETH_EPCR_LPBK_Normal 0 249#define ETH_EPCR_LPBK_Internal 1 250#define ETH_EPCR_LPBK_External 2 251#define ETH_EPCR_FC ETH__BIT(10) 252 253#define ETH_EPCR_HS ETH__BIT(12) 254#define ETH_EPCR_HS_8K 0 255#define ETH_EPCR_HS_512 ETH_EPCR_HS 256 257#define ETH_EPCR_HM ETH__BIT(13) 258#define ETH_EPCR_HM_0 0 259#define ETH_EPCR_HM_1 ETH_EPCR_HM 260 261#define ETH_EPCR_HDM ETH__BIT(14) 262#define ETH_EPCR_HDM_Discard 0 263#define ETH_EPCR_HDM_Pass ETH_EPCR_HDM 264 265#define ETH_EPCR_HD_Half 0 266#define ETH_EPCR_HD_Full ETH_EPCR_HD_Full 267 268#define ETH_EPCR_ACCS ETH__BIT(31) 269 270 271 272/* 273 * Table 598: Port Configuration Extend Register (PCXR) 274 * 00:00 IGMP IGMP Packets Capture Enable 275 * 0: IGMP packets are treated as normal Multicast 276 * packets. 277 * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 278 * are trapped and sent to high priority RX 279 * queue. 280 * 01:01 SPAN Spanning Tree Packets Capture Enable 281 * 0: BPDU (Bridge Protocol Data Unit) packets are 282 * treated as normal Multicast packets. 283 * 1: BPDU packets are trapped and sent to high 284 * priority RX queue. 285 * 02:02 PAR Partition Enable (0: Normal, 1: Partition) 286 * When more than 61 collisions occur while 287 * transmitting, the port enters Partition mode. 288 * It waits for the first good packet from the 289 * wire and then goes back to Normal mode. Under 290 * Partition mode it continues transmitting, but 291 * it does not receive. 292 * 05:03 PRIOtx Priority weight in the round-robin between high 293 * and low priority TX queues. 294 * 000: 1 pkt from HIGH, 1 pkt from LOW. 295 * 001: 2 pkt from HIGH, 1 pkt from LOW. 296 * 010: 4 pkt from HIGH, 1 pkt from LOW. 297 * 011: 6 pkt from HIGH, 1 pkt from LOW. 298 * 100: 8 pkt from HIGH, 1 pkt from LOW. 299 * 101: 10 pkt from HIGH, 1 pkt from LOW. 300 * 110: 12 pkt from HIGH, 1 pkt from LOW. 301 * 111: All pkt from HIGH, 0 pkt from LOW. LOW is 302 * served only if HIGH is empty. 303 * NOTE: If the HIGH queue is emptied before 304 * finishing the count, the count is reset 305 * until the next first HIGH comes in. 306 * 07:06 PRIOrx Default Priority for Packets Received on this 307 * Port (00: Lowest priority, 11: Highest priority) 308 * 08:08 PRIOrx_Override Override Priority for Packets Received on this 309 * Port (0: Do not override, 1: Override with 310 * <PRIOrx> field) 311 * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode 312 * (0: Enable, 1: Disable) 313 * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control 314 * 0: Enable; When enabled, 1 is written (through 315 * SMI access) to the PHY's register 4 bit 10 316 * to advertise flow-control capability. 317 * 1: Disable; Only enables flow control after the 318 * PHY address is set by the CPU. When changing 319 * the PHY address the flow control 320 * auto-negotiation must be disabled. 321 * 11:11 FLP Force Link Pass 322 * (0: Force Link Pass, 1: Do NOT Force Link pass) 323 * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) 324 * NOTE: Only valid when auto negotiation for flow 325 * control is disabled. 326 * 13:13 Reserved 327 * 15:14 MFL Max Frame Length 328 * Maximum packet allowed for reception (including 329 * CRC): 00: 1518 bytes, 01: 1536 bytes, 330 * 10: 2048 bytes, 11: 64K bytes 331 * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) 332 * 17:17 MIBctrMode Reserved. (MBZ) 333 * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) 334 * NOTE: Only valid if SpeedEn bit is set. 335 * 19:19 SpeedEn Enable Auto-negotiation for Speed 336 * (0: Enable, 1: Disable) 337 * 20:20 RMIIen RMII enable 338 * 0: Port functions as MII port 339 * 1: Port functions as RMII port 340 * 21:21 DSCPen DSCP enable 341 * 0: IP DSCP field decoding is disabled. 342 * 1: IP DSCP field decoding is enabled. 343 * 31:22 Reserved 344 */ 345#define ETH_EPCXR_IGMP ETH__BIT(0) 346#define ETH_EPCXR_SPAN ETH__BIT(1) 347#define ETH_EPCXR_PAR ETH__BIT(2) 348#define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) 349#define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) 350#define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) 351#define ETH_EPCXR_DLPXen ETH__BIT(9) 352#define ETH_EPCXR_FCTLen ETH__BIT(10) 353#define ETH_EPCXR_FLP ETH__BIT(11) 354#define ETH_EPCXR_FCTL ETH__BIT(12) 355#define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) 356#define ETH_EPCXR_MFL_SET(v) ((v) << 14) 357#define ETH_EPCXR_MFL_MASK 0x3 358#define ETH_EPCXR_MFL_1518 0 359#define ETH_EPCXR_MFL_1536 1 360#define ETH_EPCXR_MFL_2084 2 361#define ETH_EPCXR_MFL_64K 3 362#define ETH_EPCXR_MIBclrMode ETH__BIT(16) 363#define ETH_EPCXR_MIBctrMode ETH__BIT(17) 364#define ETH_EPCXR_Speed ETH__BIT(18) 365#define ETH_EPCXR_SpeedEn ETH__BIT(19) 366#define ETH_EPCXR_RMIIEn ETH__BIT(20) 367#define ETH_EPCXR_DSCPEn ETH__BIT(21) 368 369 370 371/* 372 * Table 599: Port Command Register (PCMR) 373 * 14:00 Reserved 374 * 15:15 FJ Force Jam / Flow Control 375 * When in half-duplex mode, the CPU uses this bit 376 * to force collisions on the Ethernet segment. 377 * When the CPU recognizes that it is going to run 378 * out of receive buffers, it can force the 379 * transmitter to send jam frames, forcing 380 * collisions on the wire. To allow transmission 381 * on the Ethernet segment, the CPU must clear the 382 * FJ bit when more resources are available. When 383 * in full-duplex and flow-control is enabled, this 384 * bit causes the port's transmitter to send 385 * flow-control PAUSE packets. The CPU must reset 386 * this bit when more resources are available. 387 * 31:16 Reserved 388 */ 389 390#define ETH_EPCMR_FJ ETH__BIT(15) 391 392 393/* 394 * Table 600: Port Status Register (PSR) -- Read Only 395 * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) 396 * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) 397 * 02:02 Fctl Indicates Flow-control Mode 398 * (0: enabled, 1: disabled) 399 * 03:03 Link Indicates Link Status (0: down, 1: up) 400 * 04:04 Pause Indicates that the port is in flow-control 401 * disabled state. This bit is set when an IEEE 402 * 802.3x flow-control PAUSE (XOFF) packet is 403 * received (assuming that flow-control is 404 * enabled and the port is in full-duplex mode). 405 * Reset when XON is received, or when the XOFF 406 * timer has expired. 407 * 05:05 TxLow Tx Low Priority Status 408 * Indicates the status of the low priority 409 * transmit queue: (0: Stopped, 1: Running) 410 * 06:06 TxHigh Tx High Priority Status 411 * Indicates the status of the high priority 412 * transmit queue: (0: Stopped, 1: Running) 413 * 07:07 TXinProg TX in Progress 414 * Indicates that the port's transmitter is in an 415 * active transmission state. 416 * 31:08 Reserved 417 */ 418#define ETH_EPSR_Speed ETH__BIT(0) 419#define ETH_EPSR_Duplex ETH__BIT(1) 420#define ETH_EPSR_Fctl ETH__BIT(2) 421#define ETH_EPSR_Link ETH__BIT(3) 422#define ETH_EPSR_Pause ETH__BIT(4) 423#define ETH_EPSR_TxLow ETH__BIT(5) 424#define ETH_EPSR_TxHigh ETH__BIT(6) 425#define ETH_EPSR_TXinProg ETH__BIT(7) 426 427 428/* 429 * Table 601: Serial Parameters Register (SPR) 430 * 01:00 JAM_LENGTH Two bits to determine the JAM Length 431 * (in Backpressure) as follows: 432 * 00 = 12K bit-times 433 * 01 = 24K bit-times 434 * 10 = 32K bit-times 435 * 11 = 48K bit-times 436 * 06:02 JAM_IPG Five bits to determine the JAM IPG. 437 * The step is four bit-times. The value may vary 438 * between 4 bit time to 124. 439 * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. 440 * The step is four bit-times. The value may vary 441 * between 4 bit time to 124. 442 * 16:12 IPG_DATA Inter-Packet Gap (IPG) 443 * The step is four bit-times. The value may vary 444 * between 12 bit time to 124. 445 * NOTE: These bits may be changed only when the 446 * Ethernet ports is disabled. 447 * 21:17 Data_Blind Data Blinder 448 * The number of nibbles from the beginning of the 449 * IPG, in which the IPG counter is restarted when 450 * detecting a carrier activity. Following this 451 * value, the port enters the Data Blinder zone and 452 * does not reset the IPG counter. This ensures 453 * fair access to the medium. 454 * The default is 10 hex (64 bit times - 2/3 of the 455 * default IPG). The step is 4 bit-times. Valid 456 * range is 3 to 1F hex nibbles. 457 * NOTE: These bits may be only changed when the 458 * Ethernet port is disabled. 459 * 22:22 Limit4 The number of consecutive packet collisions that 460 * occur before the collision counter is reset. 461 * 0: The port resets its collision counter after 462 * 16 consecutive retransmit trials and 463 * restarts the Backoff algorithm. 464 * 1: The port resets its collision counter and 465 * restarts the Backoff algorithm after 4 466 * consecutive transmit trials. 467 * 31:23 Reserved 468 */ 469#define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) 470#define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) 471#define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) 472#define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) 473#define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) 474#define ETH_ESPR_Limit4(v) ETH__BIT(22) 475 476/* 477 * Table 602: Hash Table Pointer Register (HTPR) 478 * 31:00 HTP 32-bit pointer to the address table. 479 * Bits [2:0] must be set to zero. 480 */ 481 482/* 483 * Table 603: Flow Control Source Address Low (FCSAL) 484 * 15:0 SA[15:0] Source Address 485 * The least significant bits of the source 486 * address for the port. This address is used for 487 * Flow Control. 488 * 31:16 Reserved 489 */ 490 491/* 492 * Table 604: Flow Control Source Address High (FCSAH) 493 * 31:0 SA[47:16] Source Address 494 * The most significant bits of the source address 495 * for the port. This address is used for Flow 496 * Control. 497 */ 498 499 500/* 501 * Table 605: SDMA Configuration Register (SDCR) 502 * 01:00 Reserved 503 * 05:02 RC Retransmit Count 504 * Sets the maximum number of retransmits per 505 * packet. After executing retransmit for RC 506 * times, the TX SDMA closes the descriptor with a 507 * Retransmit Limit error indication and processes 508 * the next packet. When RC is set to 0, the 509 * number of retransmits is unlimited. In this 510 * case, the retransmit process is only terminated 511 * if CPU issues an Abort command. 512 * 06:06 BLMR Big/Little Endian Receive Mode 513 * The DMA supports Big or Little Endian 514 * configurations on a per channel basis. The BLMR 515 * bit only affects data transfer to memory. 516 * 0: Big Endian 517 * 1: Little Endian 518 * 07:07 BLMT Big/Little Endian Transmit Mode 519 * The DMA supports Big or Little Endian 520 * configurations on a per channel basis. The BLMT 521 * bit only affects data transfer from memory. 522 * 0: Big Endian 523 * 1: Little Endian 524 * 08:08 POVR PCI Override 525 * When set, causes the SDMA to direct all its 526 * accesses in PCI_0 direction and overrides 527 * normal address decoding process. 528 * 09:09 RIFB Receive Interrupt on Frame Boundaries 529 * When set, the SDMA Rx generates interrupts only 530 * on frame boundaries (i.e. after writing the 531 * frame status to the descriptor). 532 * 11:10 Reserved 533 * 13:12 BSZ Burst Size 534 * Sets the maximum burst size for SDMA 535 * transactions: 536 * 00: Burst is limited to 1 64bit words. 537 * 01: Burst is limited to 2 64bit words. 538 * 10: Burst is limited to 4 64bit words. 539 * 11: Burst is limited to 8 64bit words. 540 * 31:14 Reserved 541 */ 542#define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) 543#define ETH_ESDCR_BLMR ETH__BIT(6) 544#define ETH_ESDCR_BLMT ETH__BIT(7) 545#define ETH_ESDCR_POVR ETH__BIT(8) 546#define ETH_ESDCR_RIFB ETH__BIT(9) 547#define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) 548#define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ 549 (v) |= ETH__INS(n, 12)) 550#define ETH_ESDCR_BSZ_1 0 551#define ETH_ESDCR_BSZ_2 1 552#define ETH_ESDCR_BSZ_4 2 553#define ETH_ESDCR_BSZ_8 3 554 555#define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ 556 "4 64-bit words", "8 64-bit words" } 557 558/* 559 * Table 606: SDMA Command Register (SDCMR) 560 * 06:00 Reserved 561 * 07:07 ERD Enable RX DMA. 562 * Set to 1 by the CPU to cause the SDMA to start 563 * a receive process. Cleared when the CPU issues 564 * an Abort Receive command. 565 * 14:08 Reserved 566 * 15:15 AR Abort Receive 567 * Set to 1 by the CPU to abort a receive SDMA 568 * operation. When the AR bit is set, the SDMA 569 * aborts its current operation and moves to IDLE. 570 * No descriptor is closed. The AR bit is cleared 571 * upon entering IDLE. After setting the AR bit, 572 * the CPU must poll the bit to verify that the 573 * abort sequence is completed. 574 * 16:16 STDH Stop TX High 575 * Set to 1 by the CPU to stop the transmission 576 * process from the high priority queue at the end 577 * of the current frame. An interrupt is generated 578 * when the stop command has been executed. 579 * Writing 1 to STDH resets TXDH bit. 580 * Writing 0 to this bit has no effect. 581 * 17:17 STDL Stop TX Low 582 * Set to 1 by the CPU to stop the transmission 583 * process from the low priority queue at the end 584 * of the current frame. An interrupt is generated 585 * when the stop command has been executed. 586 * Writing 1 to STDL resets TXDL bit. 587 * Writing 0 to this bit has no effect. 588 * 22:18 Reserved 589 * 23:23 TXDH Start Tx High 590 * Set to 1 by the CPU to cause the SDMA to fetch 591 * the first descriptor and start a transmit 592 * process from the high priority Tx queue. 593 * Writing 1 to TXDH resets STDH bit. 594 * Writing 0 to this bit has no effect. 595 * 24:24 TXDL Start Tx Low 596 * Set to 1 by the CPU to cause the SDMA to fetch 597 * the first descriptor and start a transmit 598 * process from the low priority Tx queue. 599 * Writing 1 to TXDL resets STDL bit. 600 * Writing 0 to this bit has no effect. 601 * 30:25 Reserved 602 * 31:31 AT Abort Transmit 603 * Set to 1 by the CPU to abort a transmit DMA 604 * operation. When the AT bit is set, the SDMA 605 * aborts its current operation and moves to IDLE. 606 * No descriptor is closed. Cleared upon entering 607 * IDLE. After setting AT bit, the CPU must poll 608 * it in order to verify that the abort sequence 609 * is completed. 610 */ 611#define ETH_ESDCMR_ERD ETH__BIT(7) 612#define ETH_ESDCMR_AR ETH__BIT(15) 613#define ETH_ESDCMR_STDH ETH__BIT(16) 614#define ETH_ESDCMR_STDL ETH__BIT(17) 615#define ETH_ESDCMR_TXDH ETH__BIT(23) 616#define ETH_ESDCMR_TXDL ETH__BIT(24) 617#define ETH_ESDCMR_AT ETH__BIT(31) 618 619/* 620 * Table 607: Interrupt Cause Register (ICR) 621 * 00:00 RxBuffer Rx Buffer Return 622 * Indicates an Rx buffer returned to CPU ownership 623 * or that the port finished reception of a Rx 624 * frame in either priority queues. 625 * NOTE: In order to get a Rx Buffer return per 626 * priority queue, use bit 19:16. This bit is 627 * set upon closing any Rx descriptor which 628 * has its EI bit set. To limit the 629 * interrupts to frame (rather than buffer) 630 * boundaries, the user must set SDMA 631 * Configuration register's RIFB bit. When 632 * the RIFB bit is set, an interrupt 633 * generates only upon closing the first 634 * descriptor of a received packet, if this 635 * descriptor has it EI bit set. 636 * 01:01 Reserved 637 * 02:02 TxBufferHigh Tx Buffer for High priority Queue 638 * Indicates a Tx buffer returned to CPU ownership 639 * or that the port finished transmission of a Tx 640 * frame. 641 * NOTE: This bit is set upon closing any Tx 642 * descriptor which has its EI bit set. To 643 * limit the interrupts to frame (rather than 644 * buffer) boundaries, the user must set EI 645 * only in the last descriptor. 646 * 03:03 TxBufferLow Tx Buffer for Low Priority Queue 647 * Indicates a Tx buffer returned to CPU ownership 648 * or that the port finished transmission of a Tx 649 * frame. 650 * NOTE: This bit is set upon closing any Tx 651 * descriptor which has its EI bit set. To 652 * limit the interrupts to frame (rather than 653 * buffer) boundaries, the user must set EI 654 * only in the last descriptor. 655 * 05:04 Reserved 656 * 06:06 TxEndHigh Tx End for High Priority Queue 657 * Indicates that the Tx DMA stopped processing the 658 * high priority queue after stop command, or that 659 * it reached the end of the high priority 660 * descriptor chain. 661 * 07:07 TxEndLow Tx End for Low Priority Queue 662 * Indicates that the Tx DMA stopped processing the 663 * low priority queue after stop command, or that 664 * it reached the end of the low priority 665 * descriptor chain. 666 * 08:08 RxError Rx Resource Error 667 * Indicates a Rx resource error event in one of 668 * the priority queues. 669 * NOTE: To get a Rx Resource Error Indication per 670 * priority queue, use bit 23:20. 671 * 09:09 Reserved 672 * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue 673 * Indicates a Tx resource error event during 674 * packet transmission from the high priority queue 675 * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue 676 * Indicates a Tx resource error event during 677 * packet transmission from the low priority queue 678 * 12:12 RxOVR Rx Overrun 679 * Indicates an overrun event that occurred during 680 * reception of a packet. 681 * 13:13 TxUdr Tx Underrun 682 * Indicates an underrun event that occurred during 683 * transmission of packet from either queue. 684 * 15:14 Reserved 685 * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] 686 * Indicates a Rx buffer returned to CPU ownership 687 * or that the port completed reception of a Rx 688 * frame in a receive priority queue[0] 689 * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] 690 * Indicates a Rx buffer returned to CPU ownership 691 * or that the port completed reception of a Rx 692 * frame in a receive priority queue[1]. 693 * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] 694 * Indicates a Rx buffer returned to CPU ownership 695 * or that the port completed reception of a Rx 696 * frame in a receive priority queue[2]. 697 * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] 698 * Indicates a Rx buffer returned to CPU ownership 699 * or that the port completed reception of a Rx 700 * frame in a receive priority queue[3]. 701 * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] 702 * Indicates a Rx resource error event in receive 703 * priority queue[0]. 704 * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] 705 * Indicates a Rx resource error event in receive 706 * priority queue[1]. 707 * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] 708 * Indicates a Rx resource error event in receive 709 * priority queue[2]. 710 * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] 711 * Indicates a Rx resource error event in receive 712 * priority queue[3]. 713 * 27:24 Reserved 714 * 28:29 MIIPhySTC MII PHY Status Change 715 * Indicates a status change reported by the PHY 716 * connected to this port. Set when the MII 717 * management interface block identifies a change 718 * in PHY's register 1. 719 * 29:29 SMIdone SMI Command Done 720 * Indicates that the SMI completed a MII 721 * management command (either read or write) that 722 * was initiated by the CPU writing to the SMI 723 * register. 724 * 30:30 Reserved 725 * 31:31 EtherIntSum Ethernet Interrupt Summary 726 * This bit is a logical OR of the (unmasked) bits 727 * [30:04] in the Interrupt Cause register. 728 */ 729 730#define ETH_IR_RxBuffer ETH__BIT(0) 731#define ETH_IR_TxBufferHigh ETH__BIT(2) 732#define ETH_IR_TxBufferLow ETH__BIT(3) 733#define ETH_IR_TxEndHigh ETH__BIT(6) 734#define ETH_IR_TxEndLow ETH__BIT(7) 735#define ETH_IR_RxError ETH__BIT(8) 736#define ETH_IR_TxErrorHigh ETH__BIT(10) 737#define ETH_IR_TxErrorLow ETH__BIT(11) 738#define ETH_IR_RxOVR ETH__BIT(12) 739#define ETH_IR_TxUdr ETH__BIT(13) 740#define ETH_IR_RxBuffer_0 ETH__BIT(16) 741#define ETH_IR_RxBuffer_1 ETH__BIT(17) 742#define ETH_IR_RxBuffer_2 ETH__BIT(18) 743#define ETH_IR_RxBuffer_3 ETH__BIT(19) 744#define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) 745#define ETH_IR_RxError_0 ETH__BIT(20) 746#define ETH_IR_RxError_1 ETH__BIT(21) 747#define ETH_IR_RxError_2 ETH__BIT(22) 748#define ETH_IR_RxError_3 ETH__BIT(23) 749#define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) 750#define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ 751 ETH_IR_RxBuffer_1|\ 752 ETH_IR_RxBuffer_2|\ 753 ETH_IR_RxBuffer_3|\ 754 ETH_IR_RxError_0|\ 755 ETH_IR_RxError_1|\ 756 ETH_IR_RxError_2|\ 757 ETH_IR_RxError_3) 758#define ETH_IR_MIIPhySTC ETH__BIT(28) 759#define ETH_IR_SMIdone ETH__BIT(29) 760#define ETH_IR_EtherIntSum ETH__BIT(31) 761#define ETH_IR_Summary ETH__BIT(31) 762 763/* 764 * Table 608: Interrupt Mask Register (IMR) 765 * 31:00 Various Mask bits for the Interrupt Cause register. 766 */ 767 768/* 769 * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), 770 * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. 771 */ 772 773/* 774 * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) 775 * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. 776 */ 777 778/* 779 * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) 780 * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. 781 */ 782 783/* 784 * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) 785 * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. 786 */ 787 788/* 789 * Table 613: VLAN Priority Tag to Priority (VPT2P) 790 * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] 791 * entries. 792 * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] 793 * entries. 794 * 31:16 Reserved 795 */ 796#endif /* _DEV_GTETHREG_H_ */ 797