isareg.h revision 1.4
1/* $NetBSD: isareg.h,v 1.4 1994/10/27 04:17:49 cgd Exp $ */ 2 3/*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)isa.h 5.7 (Berkeley) 5/9/91 39 */ 40 41/* 42 * ISA Bus conventions 43 */ 44 45#ifndef LOCORE 46#include <sys/cdefs.h> 47 48unsigned char rtcin __P((int)); 49void sysbeep __P((int, int)); 50unsigned kbd_8042cmd __P((int)); 51#endif /* !LOCORE */ 52 53 54/* 55 * Input / Output Port Assignments 56 */ 57 58#ifndef IO_BEGIN 59#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 60 61 /* CPU Board */ 62#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 63#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 64#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ 65#define IO_TIMER1 0x040 /* 8253 Timer #1 */ 66#define IO_TIMER2 0x048 /* 8253 Timer #2 (EISA only) */ 67#define IO_KBD 0x060 /* 8042 Keyboard */ 68#define IO_PPI 0x061 /* Programmable Peripheral Interface */ 69#define IO_RTC 0x070 /* RTC */ 70#define IO_NMI IO_RTC /* NMI Control */ 71#define IO_DMAPG 0x080 /* DMA Page Registers */ 72#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 73#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 74#define IO_NPX 0x0F0 /* Numeric Coprocessor */ 75 76 /* Cards */ 77 /* 0x100 - 0x16F Open */ 78 79#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ 80#define IO_PMP2 0x178 /* 82347 Power Management Peripheral */ 81 82 /* 0x17A - 0x1EF Open */ 83 84#define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ 85#define IO_GAME 0x200 /* Game Controller */ 86 87 /* 0x208 - 0x237 Open */ 88 89#define IO_BMS2 0x238 /* secondary InPort Bus Mouse */ 90#define IO_BMS1 0x23c /* primary InPort Bus Mouse */ 91 92 /* 0x240 - 0x277 Open */ 93 94#define IO_LPT2 0x278 /* Parallel Port #2 */ 95 96 /* 0x280 - 0x2E7 Open */ 97 98#define IO_COM4 0x2e8 /* COM4 i/o address */ 99 100 /* 0x2F0 - 0x2F7 Open */ 101 102#define IO_COM2 0x2f8 /* COM2 i/o address */ 103 104 /* 0x300 - 0x32F Open */ 105 106#define IO_BT0 0x330 /* bustek 742a default addr. */ 107#define IO_AHA0 0x330 /* adaptec 1542 default addr. */ 108#define IO_UHA0 0x330 /* ultrastore 14f default addr. */ 109#define IO_BT1 0x334 /* bustek 742a default addr. */ 110#define IO_AHA1 0x334 /* adaptec 1542 default addr. */ 111 112 /* 0x338 - 0x34F Open */ 113 114#define IO_WDS 0x350 /* WD7000 scsi */ 115 116 /* 0x354 - 0x36F Open */ 117 118#define IO_FD2 0x370 /* secondary base i/o address */ 119#define IO_LPT1 0x378 /* Parallel Port #1 */ 120 121 /* 0x380 - 0x3AF Open */ 122 123#define IO_MDA 0x3B0 /* Monochome Adapter */ 124#define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 125#define IO_VGA 0x3C0 /* E/VGA Ports */ 126#define IO_CGA 0x3D0 /* CGA Ports */ 127 128 /* 0x3E0 - 0x3E7 Open */ 129 130#define IO_COM3 0x3e8 /* COM3 i/o address */ 131#define IO_FD1 0x3f0 /* primary base i/o address */ 132#define IO_COM1 0x3f8 /* COM1 i/o address */ 133 134#define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 135#endif /* !IO_ISABEGIN */ 136 137/* 138 * Input / Output Port Sizes - these are from several sources, and tend 139 * to be the larger of what was found, ie COM ports can be 4, but some 140 * boards do not fully decode the address, thus 8 ports are used. 141 */ 142 143#ifndef IO_ISASIZES 144#define IO_ISASIZES 145 146#define IO_COMSIZE 8 /* 8250, 16X50 com controllers (*/ 147#define IO_CGASIZE 16 /* CGA controllers */ 148#define IO_DMASIZE 16 /* 8237 DMA controllers */ 149#define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */ 150#define IO_FDCSIZE 8 /* Nec765 floppy controllers */ 151#define IO_WDCSIZE 8 /* WD compatible disk controller */ 152#define IO_GAMSIZE 16 /* AT compatible game controller */ 153#define IO_ICUSIZE 16 /* 8259A interrupt controllers */ 154#define IO_KBDSIZE 16 /* 8042 Keyboard controllers */ 155#define IO_LPTSIZE 8 /* LPT controllers, some use onl */ 156#define IO_MDASIZE 16 /* Monochrome display controller */ 157#define IO_RTCSIZE 16 /* CMOS real time clock, NMI con */ 158#define IO_TMRSIZE 16 /* 8253 programmable timers */ 159#define IO_NPXSIZE 16 /* 80387/80487 NPX registers */ 160#define IO_VGASIZE 16 /* VGA controllers */ 161#define IO_PMPSIZE 2 /* 82347 Power Management Peripheral */ 162#endif /* !IO_ISASIZES */ 163 164/* 165 * Input / Output Memory Physical Addresses 166 */ 167 168#ifndef IOM_BEGIN 169#define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */ 170#define IOM_END 0x100000 /* End of I/O Memory "hole" */ 171#define IOM_SIZE (IOM_END - IOM_BEGIN) 172#endif /* !IOM_BEGIN */ 173 174/* 175 * RAM Physical Address Space (ignoring the above mentioned "hole") 176 */ 177 178#ifndef RAM_BEGIN 179#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ 180#define RAM_END 0x1000000 /* End of RAM Memory */ 181#define RAM_SIZE (RAM_END - RAM_BEGIN) 182#endif /* !RAM_BEGIN */ 183 184/* 185 * Oddball Physical Memory Addresses 186 */ 187#ifndef COMPAQ_RAMRELOC 188#define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 189#define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ 190#define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 191#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ 192#endif /* !COMPAQ_RAMRELOC */ 193 194/* stuff that used to be in pccons.c */ 195#define MONO_BASE 0x3B4 196#define MONO_BUF (KERNBASE + 0xB0000) 197#define CGA_BASE 0x3D4 198#define CGA_BUF (KERNBASE + 0xB8000) 199#define IOPHYSMEM 0xA0000 200 201/* 202 * size of dma bounce buffer in pages 203 * - currently 1 page per channel 204 */ 205#ifndef DMA_BOUNCE 206#define DMA_BOUNCE 8 207#endif 208 209#ifndef LOCORE 210extern vm_offset_t isaphysmem; 211#endif /* !LOCORE */ 212