i82365_isasubr.c revision 1.26
1/* $NetBSD: i82365_isasubr.c,v 1.26 2000/12/19 06:04:02 mycroft Exp $ */ 2 3#define PCICISADEBUG 4 5/* 6 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 7 * Copyright (c) 1998 Bill Sommerfeld. All rights reserved. 8 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Marc Horowitz. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 37#include <sys/types.h> 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/device.h> 41#include <sys/extent.h> 42#include <sys/malloc.h> 43 44#include <machine/bus.h> 45#include <machine/intr.h> 46 47#include <dev/isa/isareg.h> 48#include <dev/isa/isavar.h> 49 50#include <dev/pcmcia/pcmciareg.h> 51#include <dev/pcmcia/pcmciavar.h> 52#include <dev/pcmcia/pcmciachip.h> 53 54#include <dev/ic/i82365reg.h> 55#include <dev/ic/i82365var.h> 56#include <dev/isa/i82365_isavar.h> 57 58/***************************************************************************** 59 * Configurable parameters. 60 *****************************************************************************/ 61 62#include "opt_pcic_isa_alloc_iobase.h" 63#include "opt_pcic_isa_alloc_iosize.h" 64#include "opt_pcic_isa_intr_alloc_mask.h" 65 66/* 67 * Default I/O allocation range. If both are set to non-zero, these 68 * values will be used instead. Otherwise, the code attempts to probe 69 * the bus width. Systems with 10 address bits should use 0x300 and 0xff. 70 * Systems with 12 address bits (most) should use 0x400 and 0xbff. 71 */ 72 73#ifndef PCIC_ISA_ALLOC_IOBASE 74#define PCIC_ISA_ALLOC_IOBASE 0 75#endif 76 77#ifndef PCIC_ISA_ALLOC_IOSIZE 78#define PCIC_ISA_ALLOC_IOSIZE 0 79#endif 80 81int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE; 82int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE; 83 84 85/* 86 * Default IRQ allocation bitmask. This defines the range of allowable 87 * IRQs for PCMCIA slots. Useful if order of probing would screw up other 88 * devices, or if PCIC hardware/cards have trouble with certain interrupt 89 * lines. 90 */ 91 92#ifndef PCIC_ISA_INTR_ALLOC_MASK 93#define PCIC_ISA_INTR_ALLOC_MASK 0xffff 94#endif 95 96int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK; 97 98#ifndef PCIC_IRQ_PROBE 99#ifdef hpcmips 100/* 101 * The irq probing doesn't work with current vrisab implementation. 102 * The irq is just an key to find matching GPIO port to use and is fixed. 103 */ 104#define PCIC_IRQ_PROBE 0 105#else 106#define PCIC_IRQ_PROBE 1 107#endif 108#endif 109 110int pcic_irq_probe = PCIC_IRQ_PROBE; 111 112/***************************************************************************** 113 * End of configurable parameters. 114 *****************************************************************************/ 115 116#ifdef PCICISADEBUG 117int pcicsubr_debug = 0; 118#define DPRINTF(arg) do { if (pcicsubr_debug) printf arg ; } while (0) 119#else 120#define DPRINTF(arg) 121#endif 122 123/* 124 * count the interrupt if we have a status set 125 * just use socket 0 126 */ 127 128void pcic_isa_probe_interrupts __P((struct pcic_softc *, struct pcic_handle *)); 129static int pcic_isa_count_intr __P((void *)); 130 131static int 132pcic_isa_count_intr(arg) 133 void *arg; 134{ 135 struct pcic_softc *sc; 136 struct pcic_isa_softc *isc; 137 struct pcic_handle *h; 138 int cscreg; 139 140 h = arg; 141 sc = (struct pcic_softc *)h->ph_parent; 142 isc = (struct pcic_isa_softc *)h->ph_parent; 143 144 cscreg = pcic_read(h, PCIC_CSC); 145 if (cscreg & PCIC_CSC_CD) { 146 if ((++sc->intr_detect % 20) == 0) 147 printf("."); 148 else 149 DPRINTF((".")); 150 return (1); 151 } 152 153 /* 154 * make sure we don't get stuck in a loop due to 155 * unhandled level interupts 156 */ 157 if (++sc->intr_false > 40) { 158 isa_intr_disestablish(isc->sc_ic, sc->ih); 159 sc->ih = 0; 160 161 pcic_write(h, PCIC_CSC_INTR, 0); 162 delay(10); 163 } 164 165#ifdef PCICISADEBUG 166 if (cscreg) 167 DPRINTF(("o")); 168 else 169 DPRINTF(("X")); 170#endif 171 return (cscreg ? 1 : 0); 172} 173 174/* 175 * use soft interrupt card detect to find out which irqs are available 176 * for this controller 177 */ 178void 179pcic_isa_probe_interrupts(sc, h) 180 struct pcic_softc *sc; 181 struct pcic_handle *h; 182{ 183 struct pcic_isa_softc *isc = (void *) sc; 184 isa_chipset_tag_t ic; 185 int i, j, mask, irq; 186 int cd, cscintr, intr, csc; 187 188 ic = isc->sc_ic; 189 190 printf("%s: controller %d detecting irqs with mask 0x%04x:", 191 sc->dev.dv_xname, h->chip, sc->intr_mask[h->chip]); 192 DPRINTF(("\n")); 193 194 /* clear any current interrupt */ 195 pcic_read(h, PCIC_CSC); 196 197 /* first disable the status irq, card detect is enabled later */ 198 pcic_write(h, PCIC_CSC_INTR, 0); 199 200 /* steer the interrupt to isa and disable ring and interrupt */ 201 intr = pcic_read(h, PCIC_INTR); 202 DPRINTF(("pcic: old intr 0x%x\n", intr)); 203 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | PCIC_INTR_IRQ_MASK); 204 pcic_write(h, PCIC_INTR, intr); 205 206 207 /* clear any current interrupt */ 208 pcic_read(h, PCIC_CSC); 209 210 cd = pcic_read(h, PCIC_CARD_DETECT); 211 cd |= PCIC_CARD_DETECT_SW_INTR; 212 213 mask = 0; 214 for (i = 0; i < 16; i++) { 215 /* honor configured limitations */ 216 if ((sc->intr_mask[h->chip] & (1 << i)) == 0) 217 continue; 218 219 DPRINTF(("probing irq %d: ", i)); 220 221 /* ask for a pulse interrupt so we don't share */ 222 if (isa_intr_alloc(ic, (1 << i), IST_PULSE, &irq)) { 223 DPRINTF(("currently allocated\n")); 224 continue; 225 } 226 227 cscintr = PCIC_CSC_INTR_CD_ENABLE; 228 cscintr |= (irq << PCIC_CSC_INTR_IRQ_SHIFT); 229 pcic_write(h, PCIC_CSC_INTR, cscintr); 230 delay(10); 231 232 /* Clear any pending interrupt. */ 233 (void) pcic_read(h, PCIC_CSC); 234 235 if ((sc->ih = isa_intr_establish(ic, irq, IST_EDGE, IPL_TTY, 236 pcic_isa_count_intr, h)) == NULL) 237 panic("cant get interrupt"); 238 239 /* interrupt 40 times */ 240 sc->intr_detect = 0; 241 for (j = 0; j < 40 && sc->ih; j++) { 242 sc->intr_false = 0; 243 pcic_write(h, PCIC_CARD_DETECT, cd); 244 delay(100); 245 csc = pcic_read(h, PCIC_CSC); 246 DPRINTF(("%s", csc ? "-" : "")); 247 } 248 DPRINTF((" total %d\n", sc->intr_detect)); 249 /* allow for misses */ 250 if (sc->intr_detect > 37 && sc->intr_detect <= 40) { 251 printf("%d", i); 252 DPRINTF((" succeded\n")); 253 mask |= (1 << i); 254 } 255 256 if (sc->ih) { 257 isa_intr_disestablish(ic, sc->ih); 258 sc->ih = 0; 259 260 pcic_write(h, PCIC_CSC_INTR, 0); 261 delay(10); 262 } 263 } 264 sc->intr_mask[h->chip] = mask; 265 266 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none"); 267} 268 269/* 270 * called with interrupts enabled, light up the irqs to find out 271 * which irq lines are actually hooked up to our pcic 272 */ 273void 274pcic_isa_config_interrupts(self) 275 struct device *self; 276{ 277 struct pcic_softc *sc; 278 struct pcic_isa_softc *isc; 279 struct pcic_handle *h; 280 isa_chipset_tag_t ic; 281 int s, i, chipmask, chipuniq; 282 283 sc = (struct pcic_softc *) self; 284 isc = (struct pcic_isa_softc *) self; 285 ic = isc->sc_ic; 286 287 /* probe each controller */ 288 chipmask = 0xffff; 289 for (i = 0; i < PCIC_NSLOTS; i += 2) { 290 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 291 h = &sc->handle[i]; 292 else if (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) 293 h = &sc->handle[i + 1]; 294 else 295 continue; 296 297 sc->intr_mask[h->chip] = 298 PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask; 299 300 /* the cirrus chips lack support for the soft interrupt */ 301 if (pcic_irq_probe != 0 && 302 h->vendor != PCIC_VENDOR_CIRRUS_PD6710 && 303 h->vendor != PCIC_VENDOR_CIRRUS_PD672X) 304 pcic_isa_probe_interrupts(sc, h); 305 306 chipmask &= sc->intr_mask[h->chip]; 307 } 308 /* now see if there is at least one irq per chip not shared by all */ 309 chipuniq = 1; 310 for (i = 0; i < PCIC_NSLOTS; i += 2) { 311 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 312 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 313 continue; 314 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) { 315 chipuniq = 0; 316 break; 317 } 318 } 319 /* 320 * the rest of the following code used to run at config time with 321 * no interrupts and gets unhappy if this is violated so... 322 */ 323 s = splhigh(); 324 325 /* 326 * allocate our irq. it will be used by both controllers. I could 327 * use two different interrupts, but interrupts are relatively 328 * scarce, shareable, and for PCIC controllers, very infrequent. 329 */ 330 if ((self->dv_cfdata->cf_flags & 1) == 0) { 331 if (sc->irq != IRQUNK) { 332 if ((chipmask & (1 << sc->irq)) == 0) 333 printf("%s: warning: configured irq %d not " 334 "detected as available\n", 335 sc->dev.dv_xname, sc->irq); 336 } else if (chipmask == 0 || 337 isa_intr_alloc(ic, chipmask, IST_EDGE, &sc->irq)) { 338 printf("%s: no available irq; ", sc->dev.dv_xname); 339 sc->irq = IRQUNK; 340 } else if ((chipmask & ~(1 << sc->irq)) == 0 && chipuniq == 0) { 341 printf("%s: can't share irq with cards; ", 342 sc->dev.dv_xname); 343 sc->irq = IRQUNK; 344 } 345 } else { 346 printf("%s: ", sc->dev.dv_xname); 347 sc->irq = IRQUNK; 348 } 349 350 if (sc->irq != IRQUNK) { 351 sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY, 352 pcic_intr, sc); 353 if (sc->ih == NULL) { 354 printf("%s: can't establish interrupt", 355 sc->dev.dv_xname); 356 sc->irq = IRQUNK; 357 } 358 } 359 if (sc->irq == IRQUNK) 360 printf("polling for socket events\n"); 361 else 362 printf("%s: using irq %d for socket events\n", sc->dev.dv_xname, 363 sc->irq); 364 365 pcic_attach_sockets_finish(sc); 366 367 splx(s); 368} 369 370/* 371 * XXX This routine does not deal with the aliasing issue that its 372 * trying to. 373 * 374 * Any isa device may be decoding only 10 bits of address including 375 * the pcic. This routine only detects if the pcic is doing 10 bits. 376 * 377 * What should be done is detect the pcic's idea of the bus width, 378 * and then within those limits allocate a sparse map, where the 379 * each sub region is offset by 0x400. 380 */ 381void pcic_isa_bus_width_probe (sc, iot, ioh, base, length) 382 struct pcic_softc *sc; 383 bus_space_tag_t iot; 384 bus_space_handle_t ioh; 385 bus_addr_t base; 386 u_int32_t length; 387{ 388 bus_space_handle_t ioh_high; 389 int i, iobuswidth, tmp1, tmp2; 390 391 /* 392 * figure out how wide the isa bus is. Do this by checking if the 393 * pcic controller is mirrored 0x400 above where we expect it to be. 394 */ 395 396 iobuswidth = 12; 397 398 /* Map i/o space. */ 399 if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) { 400 printf("%s: can't map high i/o space\n", sc->dev.dv_xname); 401 return; 402 } 403 404 for (i = 0; i < PCIC_NSLOTS; i++) { 405 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 406 /* 407 * read the ident flags from the normal space and 408 * from the mirror, and compare them 409 */ 410 411 bus_space_write_1(iot, ioh, PCIC_REG_INDEX, 412 sc->handle[i].sock + PCIC_IDENT); 413 tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA); 414 415 bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX, 416 sc->handle[i].sock + PCIC_IDENT); 417 tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA); 418 419 if (tmp1 == tmp2) 420 iobuswidth = 10; 421 } 422 } 423 424 bus_space_free(iot, ioh_high, length); 425 426 /* 427 * XXX some hardware doesn't seem to grok addresses in 0x400 range-- 428 * apparently missing a bit or more of address lines. (e.g. 429 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI 430 * TravelMate 5000--not clear which is at fault) 431 * 432 * Add a kludge to detect 10 bit wide buses and deal with them, 433 * and also a config file option to override the probe. 434 */ 435 436 if (iobuswidth == 10) { 437 sc->iobase = 0x300; 438 sc->iosize = 0x0ff; 439 } else { 440 sc->iobase = 0x400; 441 sc->iosize = 0xbff; 442 } 443 444 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n", 445 sc->dev.dv_xname, (long) sc->iobase, 446 447 (long) sc->iobase + sc->iosize)); 448 449 if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) { 450 sc->iobase = pcic_isa_alloc_iobase; 451 sc->iosize = pcic_isa_alloc_iosize; 452 453 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx " 454 "(config override)\n", sc->dev.dv_xname, (long) sc->iobase, 455 (long) sc->iobase + sc->iosize)); 456 } 457} 458 459void * 460pcic_isa_chip_intr_establish(pch, pf, ipl, fct, arg) 461 pcmcia_chipset_handle_t pch; 462 struct pcmcia_function *pf; 463 int ipl; 464 int (*fct) __P((void *)); 465 void *arg; 466{ 467 struct pcic_handle *h = (struct pcic_handle *) pch; 468 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 469 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 470 isa_chipset_tag_t ic = isc->sc_ic; 471 int irq, ist; 472 void *ih; 473 int reg; 474 475 if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL) 476 ist = IST_EDGE; 477 else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE) 478 ist = IST_PULSE; 479 else 480 ist = IST_EDGE; 481 482 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq)) 483 return (NULL); 484 485 h->ih_irq = irq; 486 if (h->flags & PCIC_FLAG_ENABLED) { 487 reg = pcic_read(h, PCIC_INTR); 488 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 489 pcic_write(h, PCIC_INTR, reg | irq); 490 } 491 492 if ((ih = isa_intr_establish(ic, irq, ist, ipl, fct, arg)) == NULL) 493 return (NULL); 494 495 printf("%s: card irq %d\n", h->pcmcia->dv_xname, irq); 496 497 return (ih); 498} 499 500void 501pcic_isa_chip_intr_disestablish(pch, ih) 502 pcmcia_chipset_handle_t pch; 503 void *ih; 504{ 505 struct pcic_handle *h = (struct pcic_handle *) pch; 506 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 507 isa_chipset_tag_t ic = isc->sc_ic; 508 int reg; 509 510 isa_intr_disestablish(ic, ih); 511 512 h->ih_irq = 0; 513 if (h->flags & PCIC_FLAG_ENABLED) { 514 reg = pcic_read(h, PCIC_INTR); 515 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 516 pcic_write(h, PCIC_INTR, reg); 517 } 518} 519