1/* $NetBSD: z8530reg.h,v 1.13 2022/05/24 20:50:19 andvar Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)zsreg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43/* 44 * Zilog SCC registers, as implemented on the Sun-4c. 45 * 46 * Each Z8530 implements two channels (called `a' and `b'). 47 * 48 * The damnable chip was designed to fit on Z80 I/O ports, and thus 49 * has everything multiplexed out the wazoo. We have to select 50 * a register, then read or write the register, and so on. Worse, 51 * the parameter bits are scattered all over the register space. 52 * This thing is full of `miscellaneous' control registers. 53 * 54 * Worse yet, the registers have incompatible functions on read 55 * and write operations. We describe the registers below according 56 * to whether they are `read registers' (RR) or `write registers' (WR). 57 * As if this were not enough, some of the channel B status bits show 58 * up in channel A, and vice versa. The blasted thing shares write 59 * registers 2 and 9 across both channels, and reads registers 2 and 3 60 * differently for the two channels. We can, however, ignore this much 61 * of the time. 62 * 63 * This file also includes flags for the Z85C30 and Z85230 enhanced scc. 64 * The CMOS 8530 includes extra SDLC functionality, and is used in a 65 * number of Macs (often in the Z85C80, an 85C30 combined w/ a SCSI 66 * controller). -wrs 67 * 68 * Some of the names in this files were chosen to make the hsis driver 69 * work unchanged (which means that they will match some in SunOS). 70 * 71 * `S.C.' stands for Special Condition, which is any of these: 72 * receiver overrun (aka silo overflow) 73 * framing error (missing stop bit, etc) 74 * end of frame (in synchronous modes) 75 * parity error (when `parity error is S.C.' is set) 76 * 77 * Registers with only a single `numeric value' get a name. 78 * Other registers hold bits and are only numbered; the bit 79 * definitions imply the register number (see below). 80 * 81 * We never use the receive and transmit data registers as 82 * indirects (choosing instead the zc_data register), so they 83 * are not defined here. 84 */ 85#define ZSRR_IVEC 2 /* interrupt vector (channel 0) */ 86#define ZSRR_IPEND 3 /* interrupt pending (ch. 0 only) */ 87#define ZSRR_TXSYNC 6 /* sync transmit char (monosync mode) */ 88#define ZSRR_RXSYNC 7 /* sync receive char (monosync mode) */ 89#define ZSRR_SYNCLO 6 /* sync low byte (bisync mode) */ 90#define ZSRR_SYNCHI 7 /* sync high byte (bisync mode) */ 91#define ZSRR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ 92#define ZSRR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ 93#define ZSRR_BAUDLO 12 /* baud rate generator (low half) */ 94#define ZSRR_BAUDHI 13 /* baud rate generator (high half) */ 95#define ZSRR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/ 96 97#define ZSWR_IVEC 2 /* interrupt vector (shared) */ 98#define ZSWR_TXSYNC 6 /* sync transmit char (monosync mode) */ 99#define ZSWR_RXSYNC 7 /* sync receive char (monosync mode) */ 100#define ZSWR_SYNCLO 6 /* sync low byte (bisync mode) */ 101#define ZSWR_SYNCHI 7 /* sync high byte (bisync mode) */ 102#define ZSWR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */ 103#define ZSWR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */ 104#define ZSWR_BAUDLO 12 /* baud rate generator (low half) */ 105#define ZSWR_BAUDHI 13 /* baud rate generator (high half) */ 106#define ZSWR_ENHANCED 7 /* write address of WR7' */ 107 108/* 109 * Registers 0 through 7 may be written with any one of the 8 command 110 * modifiers, and/or any one of the 4 reset modifiers, defined below. 111 * To write registers 8 through 15, however, the command modifier must 112 * always be `point high'. Rather than track this bizzareness all over 113 * the driver, we try to avoid using any modifiers, ever (but they are 114 * defined here if you want them). 115 */ 116#define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */ 117#define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */ 118#define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */ 119#define ZSM_NULL 0x00 /* nothing special */ 120 121#define ZSM_RESET_IUS 0x38 /* reset interrupt under service */ 122#define ZSM_RESET_ERR 0x30 /* reset error cond */ 123#define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */ 124#define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */ 125#define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */ 126#define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */ 127#define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */ 128#define ZSM_NULL 0x00 /* nothing special */ 129 130/* 131 * Commands for Write Register 0 (`Command Register'). 132 * These are just the command modifiers or'ed with register number 0 133 * (which of course equals the command modifier). 134 */ 135#define ZSWR0_RESET_EOM ZSM_RESET_TXUEOM 136#define ZSWR0_RESET_TXCRC ZSM_RESET_TXCRC 137#define ZSWR0_RESET_RXCRC ZSM_RESET_RXCRC 138#define ZSWR0_CLR_INTR ZSM_RESET_IUS 139#define ZSWR0_RESET_ERRORS ZSM_RESET_ERR 140#define ZSWR0_EI_NEXTRXC ZSM_EI_NEXTRXC 141#define ZSWR0_SEND_ABORT ZSM_SEND_ABORT 142#define ZSWR0_RESET_STATUS ZSM_RESET_STINT 143#define ZSWR0_RESET_TXINT ZSM_RESET_TXINT 144 145/* 146 * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data 147 * Transfer Mode Definition'). Note that bits 3 and 4 are taken together 148 * as a single unit, and bits 5 and 6 are useful only if bit 7 is set. 149 */ 150#define ZSWR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */ 151#define ZSWR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */ 152#define ZSWR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */ 153#define ZSWR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */ 154 155#define ZSWR1_RIE_NONE 0x00 /* disable rxint entirely */ 156#define ZSWR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */ 157#define ZSWR1_RIE 0x10 /* rxint per char & on S.C. */ 158#define ZSWR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */ 159 160#define ZSWR1_PE_SC 0x04 /* parity error is special condition */ 161#define ZSWR1_TIE 0x02 /* transmit interrupt enable */ 162#define ZSWR1_SIE 0x01 /* external/status interrupt enable */ 163 164#define ZSWR1_IMASK 0x1F /* mask of all itr. enable bits. */ 165 166/* HSIS compat */ 167#define ZSWR1_REQ_ENABLE (ZSWR1_REQ_WAIT | ZSWR1_REQ_TX) 168 169/* 170 * Bits in Write Register 3 (`Receive Parameters and Control'). 171 * Bits 7 and 6 are taken as a unit. Note that the receive bits 172 * per character ordering is insane. 173 * 174 * Here `hardware flow control' means CTS enables the transmitter 175 * and DCD enables the receiver. The latter is neither interesting 176 * nor useful, and gets in our way, making it almost unusable. 177 */ 178#define ZSWR3_RX_5 0x00 /* receive 5 bits per char */ 179#define ZSWR3_RX_7 0x40 /* receive 7 bits per char */ 180#define ZSWR3_RX_6 0x80 /* receive 6 bits per char */ 181#define ZSWR3_RX_8 0xc0 /* receive 8 bits per char */ 182#define ZSWR3_RXSIZE 0xc0 /* receive char size mask */ 183 184#define ZSWR3_HFC 0x20 /* hardware flow control */ 185#define ZSWR3_HUNT 0x10 /* enter hunt mode */ 186#define ZSWR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */ 187#define ZSWR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */ 188#define ZSWR3_SDLC_SHORT_ADDR 0x02 /* short address mode (SDLC only) */ 189#define ZSWR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */ 190#define ZSWR3_RX_ENABLE 0x01 /* receiver enable */ 191 192/* 193 * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters 194 * and Modes'). Bits 7&6, 5&4, and 3&2 are taken as units. 195 */ 196#define ZSWR4_CLK_X1 0x00 /* clock divisor = 1 */ 197#define ZSWR4_CLK_X16 0x40 /* clock divisor = 16 */ 198#define ZSWR4_CLK_X32 0x80 /* clock divisor = 32 */ 199#define ZSWR4_CLK_X64 0xc0 /* clock divisor = 64 */ 200#define ZSWR4_CLK_MASK 0xc0 /* clock divisor mask */ 201 202#define ZSWR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */ 203#define ZSWR4_BISYNC 0x10 /* 16 bit sync char (sync only) */ 204#define ZSWR4_SDLC 0x20 /* SDLC mode */ 205#define ZSWR4_EXTSYNC 0x30 /* external sync mode */ 206#define ZSWR4_SYNC_MASK 0x30 /* sync mode bit mask */ 207 208#define ZSWR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */ 209#define ZSWR4_ONESB 0x04 /* 1 stop bit */ 210#define ZSWR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */ 211#define ZSWR4_TWOSB 0x0c /* 2 stop bits */ 212#define ZSWR4_SBMASK 0x0c /* mask of all stop bits */ 213 214#define ZSWR4_EVENP 0x02 /* check for even parity */ 215#define ZSWR4_PARENB 0x01 /* enable parity checking */ 216#define ZSWR4_PARMASK 0x03 /* mask of all parity bits */ 217 218/* 219 * Bits in Write Register 5 (`Transmit Parameter and Controls'). 220 * Bits 6 and 5 are taken as a unit; the ordering is, as with RX 221 * bits per char, not sensible. 222 */ 223#define ZSWR5_DTR 0x80 /* assert (set to -12V) DTR */ 224 225#define ZSWR5_TX_5 0x00 /* transmit 5 or fewer bits */ 226#define ZSWR5_TX_7 0x20 /* transmit 7 bits */ 227#define ZSWR5_TX_6 0x40 /* transmit 6 bits */ 228#define ZSWR5_TX_8 0x60 /* transmit 8 bits */ 229#define ZSWR5_TXSIZE 0x60 /* transmit char size mask */ 230 231#define ZSWR5_BREAK 0x10 /* send break (continuous 0s) */ 232#define ZSWR5_TX_ENABLE 0x08 /* enable transmitter */ 233#define ZSWR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */ 234#define ZSWR5_RTS 0x02 /* assert RTS */ 235#define ZSWR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */ 236 237#ifdef not_done_here 238/* 239 * Bits in Write Register 7 when the chip is in SDLC mode. 240 */ 241#define ZSWR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */ 242#endif 243 244/* 245 * Bits in Write Register 7' (ZSWR_ENHANCED above). This register is 246 * only available on the 85230. Despite the fact it contains flags 247 * and not a single value, the register was named as it is read 248 * via RR14. Weird. 249 */ 250 /* 0x80 unused */ 251#define ZSWR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */ 252#define ZSWR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */ 253#define ZSWR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */ 254#define ZSWR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */ 255#define ZSWR7P_RTS_DEACT 0x04 /* automatically deassert RTS */ 256#define ZSWR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */ 257#define ZSWR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */ 258 259/* 260 * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6 261 * are taken as a unit and indicate the type of reset; 00 means no reset 262 * (and is not defined here). 263 */ 264#define ZSWR9_HARD_RESET 0xc0 /* force hardware reset */ 265#define ZSWR9_A_RESET 0x80 /* reset channel A (0) */ 266#define ZSWR9_B_RESET 0x40 /* reset channel B (1) */ 267#define ZSWR9_SOFT_INTAC 0x20 /* Not in NMOS version */ 268 269#define ZSWR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */ 270#define ZSWR9_MASTER_IE 0x08 /* master interrupt enable */ 271#define ZSWR9_DLC 0x04 /* disable lower chain */ 272#define ZSWR9_NO_VECTOR 0x02 /* no vector */ 273#define ZSWR9_VECTOR_INCL_STAT 0x01 /* vector includes status */ 274 275/* 276 * Bits in Write Register 10 (`Miscellaneous Transmitter/Receiver Control 277 * Bits'). Bits 6 & 5 are taken as a unit, and some of the bits are 278 * meaningful only in certain modes. Bleah. 279 */ 280#define ZSWR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */ 281 282#define ZSWR10_NRZ 0x00 /* NRZ encoding */ 283#define ZSWR10_NRZI 0x20 /* NRZI encoding */ 284#define ZSWR10_FM1 0x40 /* FM1 encoding */ 285#define ZSWR10_FM0 0x60 /* FM0 encoding */ 286 287#define ZSWR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */ 288#define ZSWR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */ 289#define ZSWR10_ABORT_ON_UNDERRUN 0x4 /* abort on xmit underrun (SDLC) */ 290#define ZSWR10_LOOP_MODE 0x02 /* loop mode (SDLC) */ 291#define ZSWR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */ 292 293/* 294 * Bits in Write Register 11 (`Clock Mode Control'). Bits 6&5, 4&3, and 295 * 1&0 are taken as units. Various bits depend on other bits in complex 296 * ways; see the Zilog manual. 297 */ 298#define ZSWR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */ 299 /* (else have TTL oscil. on RTxC*) */ 300#define ZSWR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */ 301#define ZSWR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */ 302#define ZSWR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */ 303#define ZSWR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */ 304 305#define ZSWR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */ 306#define ZSWR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */ 307#define ZSWR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */ 308#define ZSWR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */ 309 310#define ZSWR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */ 311 /* (unless it is being used above) */ 312#define ZSWR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */ 313#define ZSWR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */ 314#define ZSWR11_TRXC_BAUD 0x02 /* TRxC output from BRG */ 315#define ZSWR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */ 316 317/* 318 * Formula for Write Registers 12 and 13 (`Lower Byte of Baud Rate 319 * Generator Time Constant' and `Upper Byte of ...'). Inputs: 320 * 321 * f BRG input clock frequency (in Hz) AFTER division 322 * by 1, 16, 32, or 64 (per clock divisor in WR4) 323 * bps desired rate in bits per second (9600, etc) 324 * 325 * We want 326 * 327 * f 328 * ----- + 0.5 - 2 329 * 2 bps 330 * 331 * rounded down to an integer. This can be computed entirely 332 * in integer arithmetic as: 333 * 334 * f + bps 335 * ------- - 2 336 * 2 bps 337 */ 338#define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2) 339 340/* inverse of above: given a BRG Time Constant, return Bits Per Second */ 341#define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2)) 342 343/* 344 * Bits in Write Register 14 (`Miscellaneous Control Bits'). 345 * Bits 7 through 5 are taken as a unit and make up a `DPLL command'. 346 */ 347#define ZSWR14_DPLL_NOOP 0x00 /* leave DPLL alone */ 348#define ZSWR14_DPLL_SEARCH 0x20 /* enter search mode */ 349#define ZSWR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */ 350#define ZSWR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */ 351#define ZSWR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */ 352#define ZSWR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */ 353#define ZSWR14_DPLL_FM 0xc0 /* operate in FM mode */ 354#define ZSWR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */ 355 356#define ZSWR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */ 357#define ZSWR14_AUTO_ECHO 0x08 /* set auto echo mode */ 358#define ZSWR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */ 359#define ZSWR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */ 360 /* (else from RTxC* pin or xtal osc) */ 361#define ZSWR14_BAUD_ENA 0x01 /* enable BRG countdown */ 362 363/* 364 * Bits in Write Register 15 (`External/Status Interrupt Control'). 365 * Most of these cause status interrupts whenever the corresponding 366 * bit or pin changes state (i.e., any rising or falling edge). 367 * 368 * NOTE: ZSWR15_SDLC_FIFO & ZSWR15_ENABLE_ENHANCED should not be 369 * set on an NMOS 8530. Also, ZSWR15_ENABLE_ENHANCED is only 370 * available on the 85230. 371 */ 372#define ZSWR15_BREAK_IE 0x80 /* enable break/abort status int */ 373#define ZSWR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */ 374#define ZSWR15_CTS_IE 0x20 /* enable CTS* pin status int */ 375#define ZSWR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */ 376#define ZSWR15_DCD_IE 0x08 /* enable DCD* pin status int */ 377#define ZSWR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */ 378#define ZSWR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */ 379#define ZSWR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */ 380 381/* 382 * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External 383 * Status'). 384 */ 385#define ZSRR0_BREAK 0x80 /* break/abort detected */ 386#define ZSRR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */ 387#define ZSRR0_CTS 0x20 /* clear to send */ 388#define ZSRR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */ 389#define ZSRR0_DCD 0x08 /* data carrier detect */ 390#define ZSRR0_TX_READY 0x04 /* transmit buffer empty */ 391#define ZSRR0_ZERO_COUNT 0x02 /* zero count in baud clock */ 392#define ZSRR0_RX_READY 0x01 /* received character ready */ 393 394/* 395 * Bits in Read Register 1 (the Zilog book does not name this one). 396 */ 397#define ZSRR1_EOF 0x80 /* end of frame (SDLC mode) */ 398#define ZSRR1_FE 0x40 /* CRC/framing error */ 399#define ZSRR1_DO 0x20 /* data (receiver) overrun */ 400#define ZSRR1_PE 0x10 /* parity error */ 401#define ZSRR1_RC0 0x08 /* residue code 0 (SDLC mode) */ 402#define ZSRR1_RC1 0x04 /* residue code 1 (SDLC mode) */ 403#define ZSRR1_RC2 0x02 /* residue code 2 (SDLC mode) */ 404#define ZSRR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */ 405 406/* 407 * Read Register 2 in B channel contains status bits if VECTOR_INCL_STAT 408 * is set. 409 */ 410 411/* 412 * Bits in Read Register 3 (`Interrupt Pending'). Only channel A 413 * has an RR3. 414 */ 415 /* 0x80 unused, returned as 0 */ 416 /* 0x40 unused, returned as 0 */ 417#define ZSRR3_IP_A_RX 0x20 /* channel A recv int pending */ 418#define ZSRR3_IP_A_TX 0x10 /* channel A xmit int pending */ 419#define ZSRR3_IP_A_STAT 0x08 /* channel A status int pending */ 420#define ZSRR3_IP_B_RX 0x04 /* channel B recv int pending */ 421#define ZSRR3_IP_B_TX 0x02 /* channel B xmit int pending */ 422#define ZSRR3_IP_B_STAT 0x01 /* channel B status int pending */ 423 424/* 425 * Bits in Read Register 10 (`contains some miscellaneous status bits'). 426 */ 427#define ZSRR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */ 428#define ZSRR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */ 429 /* 0x20 unused */ 430#define ZSRR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */ 431 /* 0x08 unused */ 432 /* 0x04 unused */ 433#define ZSRR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */ 434 435/* 436 * Bits in Read Register 15. This register is one of the few that 437 * simply reads back the corresponding Write Register. 438 */ 439#define ZSRR15_BREAK_IE 0x80 /* break/abort status int enable */ 440#define ZSRR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */ 441#define ZSRR15_CTS_IE 0x20 /* CTS* pin status int enable */ 442#define ZSRR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */ 443#define ZSRR15_DCD_IE 0x08 /* DCD* pin status int enable */ 444 /* 0x04 unused, returned as zero */ 445#define ZSRR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */ 446 /* 0x01 unused, returned as zero */ 447