wivar.h revision 1.31
1/* $NetBSD: wivar.h,v 1.31 2003/05/13 06:33:40 dyoung Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the 37 * Oslo IETF plenary meeting. 38 */ 39struct wi_softc { 40 struct device sc_dev; 41 struct ieee80211com sc_ic; 42 void *sc_ih; /* interrupt handler */ 43 int (*sc_enable)(struct wi_softc *); 44 void (*sc_disable)(struct wi_softc *); 45 void (*sc_reset)(struct wi_softc *); 46 47 int sc_attached; 48 int sc_enabled; 49 int sc_firmware_type; 50#define WI_NOTYPE 0 51#define WI_LUCENT 1 52#define WI_INTERSIL 2 53#define WI_SYMBOL 3 54 int sc_pri_firmware_ver; /* Primary firm vers */ 55 int sc_sta_firmware_ver; /* Station firm vers */ 56 int sc_pci; /* attach to PCI-Bus */ 57 58 bus_space_tag_t sc_iot; /* bus cookie */ 59 bus_space_handle_t sc_ioh; /* bus i/o handle */ 60 61 struct ifmedia sc_media; 62 caddr_t sc_drvbpf; 63 int sc_flags; 64 int sc_bap_id; 65 int sc_bap_off; 66 67 u_int16_t sc_portnum; 68 69 u_int16_t sc_dbm_adjust; 70 u_int16_t sc_max_datalen; 71 u_int16_t sc_frag_thresh; 72 u_int16_t sc_rts_thresh; 73 u_int16_t sc_system_scale; 74 u_int16_t sc_tx_rate; 75 u_int16_t sc_cnfauthmode; 76 u_int16_t sc_roaming_mode; 77 u_int16_t sc_microwave_oven; 78 79 int sc_nodelen; 80 char sc_nodename[IEEE80211_NWID_LEN]; 81 82 int sc_buflen; 83#define WI_NTXBUF 3 84 struct sc_txdesc { 85 int d_fid; 86 int d_len; 87 } sc_txd[WI_NTXBUF]; 88 int sc_txnext; 89 int sc_txcur; 90 int sc_tx_timer; 91 int sc_scan_timer; 92 int sc_syn_timer; 93 94 struct wi_counters sc_stats; 95 u_int16_t sc_ibss_port; 96 97 struct wi_apinfo sc_aps[MAXAPINFO]; 98 int sc_naps; 99 100 int sc_false_syns; 101 102 u_int16_t sc_txbuf[IEEE80211_MAX_LEN/2]; 103}; 104 105#define sc_if sc_ic.ic_if 106 107/* maximum consecutive false change-of-BSSID indications */ 108#define WI_MAX_FALSE_SYNS 10 109 110#define WI_SCAN_INQWAIT 3 /* wait sec before inquire */ 111#define WI_SCAN_WAIT 5 /* maximum scan wait */ 112 113/* Values for wi_flags. */ 114#define WI_FLAGS_ATTACHED 0x0001 115#define WI_FLAGS_INITIALIZED 0x0002 116#define WI_FLAGS_OUTRANGE 0x0004 117#define WI_FLAGS_HAS_MOR 0x0010 118#define WI_FLAGS_HAS_ROAMING 0x0020 119#define WI_FLAGS_HAS_DIVERSITY 0x0040 120#define WI_FLAGS_HAS_SYSSCALE 0x0080 121#define WI_FLAGS_BUG_AUTOINC 0x0100 122#define WI_FLAGS_HAS_FRAGTHR 0x0200 123#define WI_FLAGS_HAS_DBMADJUST 0x0400 124 125struct wi_card_ident { 126 u_int16_t card_id; 127 char *card_name; 128 u_int8_t firm_type; 129}; 130 131/* 132 * register space access macros 133 */ 134#ifdef WI_AT_BIGENDIAN_BUS_HACK 135 /* 136 * XXX - ugly hack for sparc bus_space_* macro deficiencies: 137 * assume the bus we are accessing is big endian. 138 */ 139 140#define CSR_WRITE_4(sc, reg, val) \ 141 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 142 (sc->sc_pci? reg * 2: reg) , htole32(val)) 143#define CSR_WRITE_2(sc, reg, val) \ 144 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 145 (sc->sc_pci? reg * 2: reg), htole16(val)) 146#define CSR_WRITE_1(sc, reg, val) \ 147 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 148 (sc->sc_pci? reg * 2: reg), val) 149 150#define CSR_READ_4(sc, reg) \ 151 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 152 (sc->sc_pci? reg * 2: reg))) 153#define CSR_READ_2(sc, reg) \ 154 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 155 (sc->sc_pci? reg * 2: reg))) 156#define CSR_READ_1(sc, reg) \ 157 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 158 (sc->sc_pci? reg * 2: reg)) 159 160#else 161 162#define CSR_WRITE_4(sc, reg, val) \ 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 164 (sc->sc_pci? reg * 2: reg) , val) 165#define CSR_WRITE_2(sc, reg, val) \ 166 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 167 (sc->sc_pci? reg * 2: reg), val) 168#define CSR_WRITE_1(sc, reg, val) \ 169 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 170 (sc->sc_pci? reg * 2: reg), val) 171 172#define CSR_READ_4(sc, reg) \ 173 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 174 (sc->sc_pci? reg * 2: reg)) 175#define CSR_READ_2(sc, reg) \ 176 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 177 (sc->sc_pci? reg * 2: reg)) 178#define CSR_READ_1(sc, reg) \ 179 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 180 (sc->sc_pci? reg * 2: reg)) 181#endif 182 183#ifndef __BUS_SPACE_HAS_STREAM_METHODS 184#define bus_space_write_stream_2 bus_space_write_2 185#define bus_space_write_multi_stream_2 bus_space_write_multi_2 186#define bus_space_read_stream_2 bus_space_read_2 187#define bus_space_read_multi_stream_2 bus_space_read_multi_2 188#endif 189 190#define CSR_WRITE_STREAM_2(sc, reg, val) \ 191 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \ 192 (sc->sc_pci? reg * 2: reg), val) 193#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \ 194 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 195 (sc->sc_pci? reg * 2: reg), val, count) 196#define CSR_READ_STREAM_2(sc, reg) \ 197 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \ 198 (sc->sc_pci? reg * 2: reg)) 199#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \ 200 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 201 (sc->sc_pci? reg * 2: reg), buf, count) 202 203 204int wi_attach(struct wi_softc *); 205int wi_detach(struct wi_softc *); 206int wi_activate(struct device *, enum devact); 207int wi_intr(void *arg); 208void wi_power(struct wi_softc *, int); 209void wi_shutdown(struct wi_softc *); 210