wivar.h revision 1.24
1/* $NetBSD: wivar.h,v 1.24 2002/11/16 06:02:54 dyoung Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * FreeBSD driver ported to NetBSD by Bill Sommerfeld in the back of the 37 * Oslo IETF plenary meeting. 38 */ 39struct wi_softc { 40 struct device sc_dev; 41 struct ieee80211com sc_ic; 42 void *sc_ih; /* interrupt handler */ 43 int (*sc_enable)(struct wi_softc *); 44 void (*sc_disable)(struct wi_softc *); 45 46 int sc_attached; 47 int sc_enabled; 48 int sc_firmware_type; 49#define WI_NOTYPE 0 50#define WI_LUCENT 1 51#define WI_INTERSIL 2 52#define WI_SYMBOL 3 53 int sc_pri_firmware_ver; /* Primary firm vers */ 54 int sc_sta_firmware_ver; /* Station firm vers */ 55 int sc_pci; /* attach to PCI-Bus */ 56 57 bus_space_tag_t sc_iot; /* bus cookie */ 58 bus_space_handle_t sc_ioh; /* bus i/o handle */ 59 60 struct ifmedia sc_media; 61 caddr_t sc_drvbpf; 62 int sc_flags; 63 int sc_bap_id; 64 int sc_bap_off; 65 66 u_int16_t sc_dbm_adjust; 67 u_int16_t sc_max_datalen; 68 u_int16_t sc_frag_thresh; 69 u_int16_t sc_rts_thresh; 70 u_int16_t sc_system_scale; 71 u_int16_t sc_tx_rate; 72 u_int16_t sc_cnfauthmode; 73 u_int16_t sc_roaming_mode; 74 u_int16_t sc_microwave_oven; 75 76 int sc_nodelen; 77 char sc_nodename[IEEE80211_NWID_LEN]; 78 79 int sc_buflen; 80#define WI_NTXBUF 3 81 struct sc_txdesc { 82 int d_fid; 83 int d_len; 84 } sc_txd[WI_NTXBUF]; 85 int sc_txnext; 86 int sc_txcur; 87 int sc_tx_timer; 88 int sc_scan_timer; 89 90 struct wi_counters sc_stats; 91 u_int16_t sc_ibss_port; 92 93 struct wi_apinfo sc_aps[MAXAPINFO]; 94 int sc_naps; 95}; 96 97#define sc_if sc_ic.ic_if 98 99#define WI_SCAN_INQWAIT 3 /* wait sec before inquire */ 100#define WI_SCAN_WAIT 5 /* maximum scan wait */ 101 102/* Values for wi_flags. */ 103#define WI_FLAGS_ATTACHED 0x0001 104#define WI_FLAGS_INITIALIZED 0x0002 105#define WI_FLAGS_OUTRANGE 0x0004 106#define WI_FLAGS_HAS_MOR 0x0010 107#define WI_FLAGS_HAS_ROAMING 0x0020 108#define WI_FLAGS_HAS_DIVERSITY 0x0040 109#define WI_FLAGS_HAS_SYSSCALE 0x0080 110#define WI_FLAGS_BUG_AUTOINC 0x0100 111 112struct wi_card_ident { 113 u_int16_t card_id; 114 char *card_name; 115 u_int8_t firm_type; 116}; 117 118/* 119 * register space access macros 120 */ 121#ifdef WI_AT_BIGENDIAN_BUS_HACK 122 /* 123 * XXX - ugly hack for sparc bus_space_* macro deficiencies: 124 * assume the bus we are accessing is big endian. 125 */ 126 127#define CSR_WRITE_4(sc, reg, val) \ 128 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 129 (sc->sc_pci? reg * 2: reg) , htole32(val)) 130#define CSR_WRITE_2(sc, reg, val) \ 131 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 132 (sc->sc_pci? reg * 2: reg), htole16(val)) 133#define CSR_WRITE_1(sc, reg, val) \ 134 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 135 (sc->sc_pci? reg * 2: reg), val) 136 137#define CSR_READ_4(sc, reg) \ 138 le32toh(bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 139 (sc->sc_pci? reg * 2: reg))) 140#define CSR_READ_2(sc, reg) \ 141 le16toh(bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 142 (sc->sc_pci? reg * 2: reg))) 143#define CSR_READ_1(sc, reg) \ 144 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 145 (sc->sc_pci? reg * 2: reg)) 146 147#else 148 149#define CSR_WRITE_4(sc, reg, val) \ 150 bus_space_write_4(sc->sc_iot, sc->sc_ioh, \ 151 (sc->sc_pci? reg * 2: reg) , val) 152#define CSR_WRITE_2(sc, reg, val) \ 153 bus_space_write_2(sc->sc_iot, sc->sc_ioh, \ 154 (sc->sc_pci? reg * 2: reg), val) 155#define CSR_WRITE_1(sc, reg, val) \ 156 bus_space_write_1(sc->sc_iot, sc->sc_ioh, \ 157 (sc->sc_pci? reg * 2: reg), val) 158 159#define CSR_READ_4(sc, reg) \ 160 bus_space_read_4(sc->sc_iot, sc->sc_ioh, \ 161 (sc->sc_pci? reg * 2: reg)) 162#define CSR_READ_2(sc, reg) \ 163 bus_space_read_2(sc->sc_iot, sc->sc_ioh, \ 164 (sc->sc_pci? reg * 2: reg)) 165#define CSR_READ_1(sc, reg) \ 166 bus_space_read_1(sc->sc_iot, sc->sc_ioh, \ 167 (sc->sc_pci? reg * 2: reg)) 168#endif 169 170#ifndef __BUS_SPACE_HAS_STREAM_METHODS 171#define bus_space_write_stream_2 bus_space_write_2 172#define bus_space_write_multi_stream_2 bus_space_write_multi_2 173#define bus_space_read_stream_2 bus_space_read_2 174#define bus_space_read_multi_stream_2 bus_space_read_multi_2 175#endif 176 177#define CSR_WRITE_STREAM_2(sc, reg, val) \ 178 bus_space_write_stream_2(sc->sc_iot, sc->sc_ioh, \ 179 (sc->sc_pci? reg * 2: reg), val) 180#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \ 181 bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 182 (sc->sc_pci? reg * 2: reg), val, count) 183#define CSR_READ_STREAM_2(sc, reg) \ 184 bus_space_read_stream_2(sc->sc_iot, sc->sc_ioh, \ 185 (sc->sc_pci? reg * 2: reg)) 186#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \ 187 bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, \ 188 (sc->sc_pci? reg * 2: reg), buf, count) 189 190 191int wi_attach(struct wi_softc *); 192int wi_detach(struct wi_softc *); 193int wi_activate(struct device *, enum devact); 194int wi_intr(void *arg); 195void wi_power(struct wi_softc *, int); 196void wi_shutdown(struct wi_softc *); 197