seeq8005.c revision 1.44
1/* $NetBSD: seeq8005.c,v 1.44 2010/01/19 22:06:25 pooka Exp $ */ 2 3/* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36/* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39/* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45/* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52/* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56/* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63#include <sys/cdefs.h> 64__KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.44 2010/01/19 22:06:25 pooka Exp $"); 65 66#include <sys/param.h> 67#include <sys/systm.h> 68#include <sys/endian.h> 69#include <sys/errno.h> 70#include <sys/ioctl.h> 71#include <sys/mbuf.h> 72#include <sys/socket.h> 73#include <sys/syslog.h> 74#include <sys/device.h> 75 76#include <net/if.h> 77#include <net/if_dl.h> 78#include <net/if_types.h> 79#include <net/if_ether.h> 80#include <net/if_media.h> 81 82#include <net/bpf.h> 83#include <net/bpfdesc.h> 84 85#include "rnd.h" 86#if NRND > 0 87#include <sys/rnd.h> 88#endif 89 90#include <sys/bus.h> 91#include <sys/intr.h> 92 93#include <dev/ic/seeq8005reg.h> 94#include <dev/ic/seeq8005var.h> 95 96/*#define SEEQ_DEBUG*/ 97 98/* for debugging convenience */ 99#ifdef SEEQ8005_DEBUG 100#define SEEQ_DEBUG_MISC 1 101#define SEEQ_DEBUG_TX 2 102#define SEEQ_DEBUG_RX 4 103#define SEEQ_DEBUG_PKT 8 104#define SEEQ_DEBUG_TXINT 16 105#define SEEQ_DEBUG_RXINT 32 106int seeq8005_debug = 0; 107#define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 108#else 109#define DPRINTF(f, x) 110#endif 111 112#define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 113 114#define SEEQ_READ16(sc, iot, ioh, reg) \ 115 ((sc)->sc_flags & SF_8BIT ? \ 116 (bus_space_read_1((iot), (ioh), (reg)) | \ 117 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 118 (bus_space_read_2((iot), (ioh), (reg)))) 119 120#define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 121 if ((sc)->sc_flags & SF_8BIT) { \ 122 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 123 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 124 } else \ 125 bus_space_write_2((iot), (ioh), (reg), (val)); \ 126} while (/*CONSTCOND*/0) 127 128/* 129 * prototypes 130 */ 131 132static int ea_init(struct ifnet *); 133static int ea_ioctl(struct ifnet *, u_long, void *); 134static void ea_start(struct ifnet *); 135static void ea_watchdog(struct ifnet *); 136static void ea_chipreset(struct seeq8005_softc *); 137static void ea_ramtest(struct seeq8005_softc *); 138static int ea_stoptx(struct seeq8005_softc *); 139static int ea_stoprx(struct seeq8005_softc *); 140static void ea_stop(struct ifnet *, int); 141static void ea_await_fifo_empty(struct seeq8005_softc *); 142static void ea_await_fifo_full(struct seeq8005_softc *); 143static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 144static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 145static void ea_select_buffer(struct seeq8005_softc *, int); 146static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 147static void ea_read(struct seeq8005_softc *, int, int); 148static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 149static void ea_txint(struct seeq8005_softc *); 150static void ea_rxint(struct seeq8005_softc *); 151static void eatxpacket(struct seeq8005_softc *); 152static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 153static void ea_mc_reset(struct seeq8005_softc *); 154static void ea_mc_reset_8004(struct seeq8005_softc *); 155static void ea_mc_reset_8005(struct seeq8005_softc *); 156static int ea_mediachange(struct ifnet *); 157static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 158 159static char* padbuf = NULL; 160 161 162/* 163 * Attach chip. 164 */ 165 166void 167seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 168 int nmedia, int defmedia) 169{ 170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 171 bus_space_tag_t iot = sc->sc_iot; 172 bus_space_handle_t ioh = sc->sc_ioh; 173 u_int id; 174 175 KASSERT(myaddr != NULL); 176 printf(" address %s", ether_sprintf(myaddr)); 177 178 /* Stop the board. */ 179 180 ea_chipreset(sc); 181 182 /* Work out data bus width. */ 183 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 184 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 185 /* Try 8-bit mode */ 186 sc->sc_flags |= SF_8BIT; 187 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 188 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 189 aprint_normal("\n"); 190 aprint_error_dev(&sc->sc_dev, "Cannot determine data bus width\n"); 191 return; 192 } 193 } 194 195 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 196 197 /* Get the product ID */ 198 199 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 200 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 201 202 switch (id & SEEQ_PRODUCTID_MASK) { 203 case SEEQ_PRODUCTID_8004: 204 sc->sc_variant = SEEQ_8004; 205 switch (id & SEEQ_PRODUCTID_REV_MASK) { 206 case SEEQ_PRODUCTID_REV_80C04: 207 printf(", SEEQ 80C04\n"); 208 break; 209 case SEEQ_PRODUCTID_REV_80C04A: 210 printf(", SEEQ 80C04A\n"); 211 break; 212 default: 213 /* Unknown SEEQ 8004 variants */ 214 printf(", SEEQ 8004 rev %x\n", 215 id & SEEQ_PRODUCTID_REV_MASK); 216 break; 217 } 218 break; 219 default: /* XXX */ 220 sc->sc_variant = SEEQ_8005; 221 printf(", SEEQ 8005\n"); 222 break; 223 } 224 225 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 226 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 227 228 /* 229 * Set up tx and rx buffers. 230 * 231 * We use approximately a quarter of the packet memory for TX 232 * buffers and the rest for RX buffers 233 */ 234 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 235 sc->sc_tx_bufs = 1; 236 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 237 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 238 sc->sc_enabled = 0; 239 240 /* Test the RAM */ 241 ea_ramtest(sc); 242 243 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 244 device_xname(&sc->sc_dev), sc->sc_buffersize >> 10, 245 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 246 247 if (padbuf == NULL) { 248 padbuf = malloc(ETHER_MIN_LEN - ETHER_CRC_LEN, M_DEVBUF, 249 M_ZERO | M_NOWAIT); 250 if (padbuf == NULL) { 251 aprint_error_dev(&sc->sc_dev, "can't allocate pad buffer\n"); 252 return; 253 } 254 } 255 256 /* Initialise ifnet structure. */ 257 258 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 259 ifp->if_softc = sc; 260 ifp->if_start = ea_start; 261 ifp->if_ioctl = ea_ioctl; 262 ifp->if_init = ea_init; 263 ifp->if_stop = ea_stop; 264 ifp->if_watchdog = ea_watchdog; 265 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 266 if (sc->sc_variant == SEEQ_8004) 267 ifp->if_flags |= IFF_SIMPLEX; 268 IFQ_SET_READY(&ifp->if_snd); 269 270 /* Initialize media goo. */ 271 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 272 if (media != NULL) { 273 int i; 274 275 for (i = 0; i < nmedia; i++) 276 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 277 ifmedia_set(&sc->sc_media, defmedia); 278 } else { 279 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 280 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 281 } 282 283 /* We can support 802.1Q VLAN-sized frames. */ 284 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 285 286 /* Now we can attach the interface. */ 287 288 if_attach(ifp); 289 ether_ifattach(ifp, myaddr); 290 291 printf("\n"); 292 293#if NRND > 0 294 /* After \n because it can print a line of its own. */ 295 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 296 RND_TYPE_NET, 0); 297#endif 298} 299 300/* 301 * Media change callback. 302 */ 303static int 304ea_mediachange(struct ifnet *ifp) 305{ 306 struct seeq8005_softc *sc = ifp->if_softc; 307 308 if (sc->sc_mediachange) 309 return ((*sc->sc_mediachange)(sc)); 310 return (EINVAL); 311} 312 313/* 314 * Media status callback. 315 */ 316static void 317ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 318{ 319 struct seeq8005_softc *sc = ifp->if_softc; 320 321 if (sc->sc_enabled == 0) { 322 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 323 ifmr->ifm_status = 0; 324 return; 325 } 326 327 if (sc->sc_mediastatus) 328 (*sc->sc_mediastatus)(sc, ifmr); 329} 330 331/* 332 * Test the RAM on the ethernet card. 333 */ 334 335void 336ea_ramtest(struct seeq8005_softc *sc) 337{ 338 bus_space_tag_t iot = sc->sc_iot; 339 bus_space_handle_t ioh = sc->sc_ioh; 340 int loop; 341 u_int sum = 0; 342 343 /* 344 * Test the buffer memory on the board. 345 * Write simple pattens to it and read them back. 346 */ 347 348 /* Set up the whole buffer RAM for writing */ 349 350 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 351 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 352 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 353 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 354 355#define SEEQ_RAMTEST_LOOP(value) \ 356do { \ 357 /* Set the write start address and write a pattern */ \ 358 ea_writebuf(sc, NULL, 0x0000, 0); \ 359 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 360 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 361 \ 362 /* Set the read start address and verify the pattern */ \ 363 ea_readbuf(sc, NULL, 0x0000, 0); \ 364 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 365 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 366 ++sum; \ 367} while (/*CONSTCOND*/0) 368 369 SEEQ_RAMTEST_LOOP(loop); 370 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 371 SEEQ_RAMTEST_LOOP(0xaa55); 372 SEEQ_RAMTEST_LOOP(0x55aa); 373 374 /* Report */ 375 376 if (sum > 0) 377 aprint_error_dev(&sc->sc_dev, "buffer RAM failed self test, %d faults\n", sum); 378} 379 380 381/* 382 * Stop the tx interface. 383 * 384 * Returns 0 if the tx was already stopped or 1 if it was active 385 */ 386 387static int 388ea_stoptx(struct seeq8005_softc *sc) 389{ 390 bus_space_tag_t iot = sc->sc_iot; 391 bus_space_handle_t ioh = sc->sc_ioh; 392 int timeout; 393 int status; 394 395 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 396 397 sc->sc_enabled = 0; 398 399 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 400 if (!(status & SEEQ_STATUS_TX_ON)) 401 return 0; 402 403 /* Stop any tx and wait for confirmation */ 404 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 405 sc->sc_command | SEEQ_CMD_TX_OFF); 406 407 timeout = 20000; 408 do { 409 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 410 delay(1); 411 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 412 if (timeout == 0) 413 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 414 device_xname(&sc->sc_dev)); 415 416 /* Clear any pending tx interrupt */ 417 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 418 sc->sc_command | SEEQ_CMD_TX_INTACK); 419 return 1; 420} 421 422 423/* 424 * Stop the rx interface. 425 * 426 * Returns 0 if the tx was already stopped or 1 if it was active 427 */ 428 429static int 430ea_stoprx(struct seeq8005_softc *sc) 431{ 432 bus_space_tag_t iot = sc->sc_iot; 433 bus_space_handle_t ioh = sc->sc_ioh; 434 int timeout; 435 int status; 436 437 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 438 439 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 440 if (!(status & SEEQ_STATUS_RX_ON)) 441 return 0; 442 443 /* Stop any rx and wait for confirmation */ 444 445 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 446 sc->sc_command | SEEQ_CMD_RX_OFF); 447 448 timeout = 20000; 449 do { 450 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 451 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 452 if (timeout == 0) 453 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 454 device_xname(&sc->sc_dev)); 455 456 /* Clear any pending rx interrupt */ 457 458 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 459 sc->sc_command | SEEQ_CMD_RX_INTACK); 460 return 1; 461} 462 463 464/* 465 * Stop interface. 466 * Stop all IO and shut the interface down 467 */ 468 469/* ARGSUSED */ 470static void 471ea_stop(struct ifnet *ifp, int disable) 472{ 473 struct seeq8005_softc *sc = ifp->if_softc; 474 bus_space_tag_t iot = sc->sc_iot; 475 bus_space_handle_t ioh = sc->sc_ioh; 476 477 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 478 479 /* Stop all IO */ 480 ea_stoptx(sc); 481 ea_stoprx(sc); 482 483 /* Disable rx and tx interrupts */ 484 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 485 486 /* Clear any pending interrupts */ 487 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 488 sc->sc_command | SEEQ_CMD_RX_INTACK | 489 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 490 SEEQ_CMD_BW_INTACK); 491 492 if (sc->sc_variant == SEEQ_8004) { 493 /* Put the chip to sleep */ 494 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 495 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 496 sc->sc_config3 | SEEQ_CFG3_SLEEP); 497 } 498 499 /* Cancel any watchdog timer */ 500 sc->sc_ethercom.ec_if.if_timer = 0; 501} 502 503 504/* 505 * Reset the chip 506 * Following this the software registers are reset 507 */ 508 509static void 510ea_chipreset(struct seeq8005_softc *sc) 511{ 512 bus_space_tag_t iot = sc->sc_iot; 513 bus_space_handle_t ioh = sc->sc_ioh; 514 515 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 516 517 /* Reset the controller. Min of 4us delay here */ 518 519 /* 520 * This can be called before we know whether the chip is in 8- or 521 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 522 * harmless in 8-bit mode, so we do that second. 523 */ 524 525 /* In 16-bit mode, this will munge the PreamSelect bit. */ 526 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 527 delay(4); 528 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 529 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 530 delay(4); 531 532 sc->sc_command = 0; 533 sc->sc_config1 = 0; 534 sc->sc_config2 = 0; 535 sc->sc_config3 = 0; 536} 537 538 539/* 540 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 541 * switching the FIFO from write to read. We also use it when changing 542 * the address for writes. 543 */ 544static void 545ea_await_fifo_empty(struct seeq8005_softc *sc) 546{ 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 int timeout; 550 551 timeout = 20000; 552 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 553 SEEQ_STATUS_FIFO_DIR) != 0) 554 return; /* FIFO is reading anyway. */ 555 while (--timeout > 0) 556 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 557 SEEQ_STATUS_FIFO_EMPTY) 558 return; 559 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", device_xname(&sc->sc_dev)); 560} 561 562/* 563 * Wait for the DMA FIFO to fill before reading from it. 564 */ 565static void 566ea_await_fifo_full(struct seeq8005_softc *sc) 567{ 568 bus_space_tag_t iot = sc->sc_iot; 569 bus_space_handle_t ioh = sc->sc_ioh; 570 int timeout; 571 572 timeout = 20000; 573 while (--timeout > 0) 574 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 575 SEEQ_STATUS_FIFO_FULL) 576 return; 577 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", device_xname(&sc->sc_dev)); 578} 579 580/* 581 * write to the buffer memory on the interface 582 * 583 * The buffer address is set to ADDR. 584 * If len != 0 then data is copied from the address starting at buf 585 * to the interface buffer. 586 * BUF must be usable as a u_int16_t *. 587 * If LEN is odd, it must be safe to overwrite one extra byte. 588 */ 589 590static void 591ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 592{ 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 596 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 597 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 598 599#ifdef DIAGNOSTIC 600 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 601 panic("%s: unaligned writebuf", device_xname(&sc->sc_dev)); 602 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 603 panic("%s: writebuf out of range", device_xname(&sc->sc_dev)); 604#endif 605 606 if (addr != -1) { 607 ea_await_fifo_empty(sc); 608 609 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 610 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 611 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 612 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 613 } 614 615 if (len > 0) { 616 if (sc->sc_flags & SF_8BIT) 617 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 618 (u_int8_t *)buf, len); 619 else 620 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 621 /* LINTED: alignment checked above */ 622 (u_int16_t *)buf, len / 2); 623 } 624 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 625 /* Write the last byte */ 626 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, buf[len - 1]); 627 } 628 /* Leave FIFO to empty in the background */ 629} 630 631 632/* 633 * read from the buffer memory on the interface 634 * 635 * The buffer address is set to ADDR. 636 * If len != 0 then data is copied from the interface buffer to the 637 * address starting at buf. 638 * BUF must be usable as a u_int16_t *. 639 * If LEN is odd, it must be safe to overwrite one extra byte. 640 */ 641 642static void 643ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 644{ 645 bus_space_tag_t iot = sc->sc_iot; 646 bus_space_handle_t ioh = sc->sc_ioh; 647 int runup; 648 649 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 650 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 651 652#ifdef DIAGNOSTIC 653 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 654 panic("%s: unaligned readbuf", device_xname(&sc->sc_dev)); 655 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 656 panic("%s: readbuf out of range", device_xname(&sc->sc_dev)); 657#endif 658 659 if (addr != -1) { 660 /* 661 * SEEQ 80C04 bug: 662 * Starting reading from certain addresses seems to cause 663 * us to get bogus results, so we avoid them. 664 */ 665 runup = 0; 666 if (sc->sc_variant == SEEQ_8004 && 667 ((addr & 0x00ff) == 0x00ea || 668 (addr & 0x00ff) == 0x00ee || 669 (addr & 0x00ff) == 0x00f0)) 670 runup = (addr & 0x00ff) - 0x00e8; 671 672 ea_await_fifo_empty(sc); 673 674 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 675 676 /* 677 * 80C04 bug workaround. I found this in the old arm32 "eb" 678 * driver. I've no idea what it does, but it seems to stop 679 * the chip mangling data so often. 680 */ 681 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 682 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 683 ea_await_fifo_empty(sc); 684 685 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 686 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 687 sc->sc_command | SEEQ_CMD_FIFO_READ); 688 689 ea_await_fifo_full(sc); 690 while (runup > 0) { 691 /* LINTED: Reading a volatile _does_ have an effect */ 692 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 693 runup -= 2; 694 } 695 } 696 697 if (len > 0) { 698 if (sc->sc_flags & SF_8BIT) 699 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 700 (u_int8_t *)buf, len); 701 else 702 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 703 /* LINTED: pointer alignment checked above */ 704 (u_int16_t *)buf, len / 2); 705 } 706 if (!(sc->sc_flags & SF_8BIT) && len % 2) { 707 /* Read the last byte */ 708 buf[len - 1] = bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 709 } 710} 711 712static void 713ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 714{ 715 716 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 717 sc->sc_config1 | bufcode); 718} 719 720/* Must be called at splnet */ 721static void 722ea_set_address(struct seeq8005_softc *sc, int which, const u_int8_t *ea) 723{ 724 int i; 725 726 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 727 for (i = 0; i < ETHER_ADDR_LEN; ++i) 728 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 729 ea[i]); 730} 731 732/* 733 * Initialize interface. 734 * 735 * This should leave the interface in a state for packet reception and 736 * transmission. 737 */ 738 739static int 740ea_init(struct ifnet *ifp) 741{ 742 struct seeq8005_softc *sc = ifp->if_softc; 743 bus_space_tag_t iot = sc->sc_iot; 744 bus_space_handle_t ioh = sc->sc_ioh; 745 int s; 746 747 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 748 749 s = splnet(); 750 751 /* First, reset the board. */ 752 753 ea_chipreset(sc); 754 755 /* Set up defaults for the registers */ 756 757 sc->sc_command = 0; 758 sc->sc_config1 = 0; 759#if BYTE_ORDER == BIG_ENDIAN 760 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 761#else 762 sc->sc_config2 = 0; 763#endif 764 sc->sc_config3 = 0; 765 766 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 767 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 768 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 769 if (sc->sc_variant == SEEQ_8004) { 770 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 771 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 772 } 773 774 /* Write the station address - the receiver must be off */ 775 ea_set_address(sc, 0, (const u_int8_t *)CLLADDR(ifp->if_sadl)); 776 777 /* Split board memory into Rx and Tx. */ 778 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 779 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 780 781 if (sc->sc_variant == SEEQ_8004) { 782 /* Make the interface IFF_SIMPLEX. */ 783 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 784 /* Enable reception of long packets (for vlan(4)). */ 785 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 786 } 787 788 /* Configure rx. */ 789 ea_mc_reset(sc); 790 if (ifp->if_flags & IFF_PROMISC) 791 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 792 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 793 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 794 else 795 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 796 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 797 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 798 799 /* Setup the Rx pointers */ 800 sc->sc_rx_ptr = sc->sc_tx_bufsize; 801 802 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 803 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 804 805 806 /* Place a NULL header at the beginning of the receive area */ 807 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 808 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 810 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 811 812 813 /* Configure TX. */ 814 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 815 816 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 817 818 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 819 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 820 821 /* Reset tx buffer pointers */ 822 sc->sc_tx_cur = 0; 823 sc->sc_tx_used = 0; 824 sc->sc_tx_next = 0; 825 826 /* Place a NULL header at the beginning of the transmit area */ 827 ea_writebuf(sc, NULL, 0x0000, 0); 828 829 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 830 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 831 832 sc->sc_command |= SEEQ_CMD_TX_INTEN; 833 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 834 835 /* Turn on Rx */ 836 sc->sc_command |= SEEQ_CMD_RX_INTEN; 837 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 838 sc->sc_command | SEEQ_CMD_RX_ON); 839 840 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 841 842 843 /* Set flags appropriately. */ 844 ifp->if_flags |= IFF_RUNNING; 845 ifp->if_flags &= ~IFF_OACTIVE; 846 sc->sc_enabled = 1; 847 848 /* And start output. */ 849 ea_start(ifp); 850 851 splx(s); 852 return 0; 853} 854 855/* 856 * Start output on interface. Get datagrams from the queue and output them, 857 * giving the receiver a chance between datagrams. Call only from splnet or 858 * interrupt level! 859 */ 860 861static void 862ea_start(struct ifnet *ifp) 863{ 864 struct seeq8005_softc *sc = ifp->if_softc; 865 int s; 866 867 s = splnet(); 868 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 869 870 /* 871 * Don't do anything if output is active. seeq8005intr() will call 872 * us (actually eatxpacket()) back when the card's ready for more 873 * frames. 874 */ 875 if (ifp->if_flags & IFF_OACTIVE) 876 return; 877 878 /* Mark interface as output active */ 879 880 ifp->if_flags |= IFF_OACTIVE; 881 882 /* tx packets */ 883 884 eatxpacket(sc); 885 splx(s); 886} 887 888 889/* 890 * Transfer a packet to the interface buffer and start transmission 891 * 892 * Called at splnet() 893 */ 894 895void 896eatxpacket(struct seeq8005_softc *sc) 897{ 898 bus_space_tag_t iot = sc->sc_iot; 899 bus_space_handle_t ioh = sc->sc_ioh; 900 struct mbuf *m0; 901 struct ifnet *ifp; 902 903 ifp = &sc->sc_ethercom.ec_if; 904 905 /* Dequeue the next packet. */ 906 IFQ_DEQUEUE(&ifp->if_snd, m0); 907 908 /* If there's nothing to send, return. */ 909 if (!m0) { 910 ifp->if_flags &= ~IFF_OACTIVE; 911 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 912 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 913 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 914 return; 915 } 916 917 /* Give the packet to the bpf, if any. */ 918 if (ifp->if_bpf) 919 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 920 921 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 922 923 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 924 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 925 926 ea_writembuf(sc, m0, 0x0000); 927 m_freem(m0); 928 929 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 930 931 /* Now transmit the datagram. */ 932 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 933 sc->sc_command | SEEQ_CMD_TX_ON); 934 935 /* Make sure we notice if the chip goes silent on us. */ 936 ifp->if_timer = 5; 937 938 DPRINTF(SEEQ_DEBUG_TX, 939 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 940 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 941} 942 943/* 944 * Copy a packet from an mbuf to the transmit buffer on the card. 945 * 946 * Puts a valid Tx header at the start of the packet, and a null header at 947 * the end. 948 */ 949static int 950ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 951{ 952 struct mbuf *m; 953 int len, nextpacket; 954 u_int8_t hdr[4]; 955 956 /* 957 * Copy the datagram to the packet buffer. 958 */ 959 len = 0; 960 for (m = m0; m; m = m->m_next) { 961 if (m->m_len == 0) 962 continue; 963 ea_writebuf(sc, mtod(m, u_char *), bufstart + 4 + len, 964 m->m_len); 965 len += m->m_len; 966 } 967 968 if (len < ETHER_MIN_LEN) { 969 ea_writebuf(sc, padbuf, bufstart + 4 + len, 970 ETHER_MIN_LEN - len); 971 len = ETHER_MIN_LEN; 972 } 973 974 /* Follow it with a NULL packet header */ 975 memset(hdr, 0, 4); 976 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 977 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 978 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 979 980 /* Ok we now have a packet len bytes long in our packet buffer */ 981 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 982 983 /* Write the packet header */ 984 nextpacket = len + 4; 985 hdr[0] = (nextpacket >> 8) & 0xff; 986 hdr[1] = nextpacket & 0xff; 987 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 988 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 989 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 990 ea_writebuf(sc, hdr, 0x0000, 4); 991 992 return len; 993} 994 995/* 996 * Ethernet controller interrupt. 997 */ 998 999int 1000seeq8005intr(void *arg) 1001{ 1002 struct seeq8005_softc *sc = arg; 1003 bus_space_tag_t iot = sc->sc_iot; 1004 bus_space_handle_t ioh = sc->sc_ioh; 1005 int status, handled; 1006 1007 handled = 0; 1008 1009 /* Get the controller status */ 1010 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 1011 1012 /* Tx interrupt ? */ 1013 if (status & SEEQ_STATUS_TX_INT) { 1014 handled = 1; 1015 1016 /* Acknowledge the interrupt */ 1017 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1018 sc->sc_command | SEEQ_CMD_TX_INTACK); 1019 1020 ea_txint(sc); 1021 } 1022 1023 1024 /* Rx interrupt ? */ 1025 if (status & SEEQ_STATUS_RX_INT) { 1026 handled = 1; 1027 1028 /* Acknowledge the interrupt */ 1029 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1030 sc->sc_command | SEEQ_CMD_RX_INTACK); 1031 1032 /* Processes the received packets */ 1033 ea_rxint(sc); 1034 } 1035 1036#if NRND > 0 1037 if (handled) 1038 rnd_add_uint32(&sc->rnd_source, status); 1039#endif 1040 return handled; 1041} 1042 1043static void 1044ea_txint(struct seeq8005_softc *sc) 1045{ 1046 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1047 bus_space_tag_t iot = sc->sc_iot; 1048 bus_space_handle_t ioh = sc->sc_ioh; 1049 u_int8_t txhdr[4]; 1050 u_int txstatus; 1051 1052 ea_readbuf(sc, txhdr, 0x0000, 4); 1053 1054 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1055 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1056 txstatus = txhdr[3]; 1057 1058 /* 1059 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1060 * one collision. On the 8004 we can find out exactly how many 1061 * collisions occurred. 1062 * 1063 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1064 * completed. 1065 * 1066 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1067 * occurred and the packet transmission was aborted. 1068 * This situation is untested as present. 1069 * 1070 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1071 * when we deliberately transmit oversized packets (e.g. for 1072 * 802.1Q). 1073 */ 1074 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1075 switch (sc->sc_variant) { 1076 case SEEQ_8004: { 1077 int colls; 1078 1079 /* 1080 * The 8004 contains a 4 bit collision count 1081 * in the status register. 1082 */ 1083 1084 /* This appears to be broken on 80C04.AE */ 1085/* ifp->if_collisions += 1086 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1087 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1088 1089 /* Use the TX Collision register */ 1090 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1091 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1092 ifp->if_collisions += colls; 1093 break; 1094 } 1095 case SEEQ_8005: 1096 /* We known there was at least 1 collision */ 1097 ifp->if_collisions++; 1098 break; 1099 } 1100 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1101 printf("seeq_intr: col16 %x\n", txstatus); 1102 ifp->if_collisions += 16; 1103 ifp->if_oerrors++; 1104 } 1105 1106 /* Have we completed transmission on the packet ? */ 1107 if (txstatus & SEEQ_PKTSTAT_DONE) { 1108 /* Clear watchdog timer. */ 1109 ifp->if_timer = 0; 1110 ifp->if_flags &= ~IFF_OACTIVE; 1111 1112 /* Update stats */ 1113 ifp->if_opackets++; 1114 1115 /* Tx next packet */ 1116 1117 eatxpacket(sc); 1118 } 1119} 1120 1121void 1122ea_rxint(struct seeq8005_softc *sc) 1123{ 1124 bus_space_tag_t iot = sc->sc_iot; 1125 bus_space_handle_t ioh = sc->sc_ioh; 1126 u_int addr; 1127 int len; 1128 int ctrl; 1129 int ptr; 1130 int status; 1131 u_int8_t rxhdr[4]; 1132 struct ifnet *ifp; 1133 1134 ifp = &sc->sc_ethercom.ec_if; 1135 1136 1137 /* We start from the last rx pointer position */ 1138 addr = sc->sc_rx_ptr; 1139 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1140 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1141 1142 do { 1143 /* Read rx header */ 1144 ea_readbuf(sc, rxhdr, addr, 4); 1145 1146 /* Split the packet header */ 1147 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1148 ctrl = rxhdr[2]; 1149 status = rxhdr[3]; 1150 1151 DPRINTF(SEEQ_DEBUG_RX, 1152 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1153 addr, ptr, ctrl, status)); 1154 1155 /* Zero packet ptr ? then must be null header so exit */ 1156 if (ptr == 0) break; 1157 1158 /* Sanity-check the next-packet pointer and flags. */ 1159 if (__predict_false(ptr < sc->sc_tx_bufsize || 1160 (ctrl & SEEQ_PKTCMD_TX))) { 1161 ++ifp->if_ierrors; 1162 log(LOG_ERR, 1163 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1164 device_xname(&sc->sc_dev), addr, ptr); 1165 ea_init(ifp); 1166 return; 1167 } 1168 1169 /* Get packet length */ 1170 len = (ptr - addr) - 4; 1171 1172 if (len < 0) 1173 len += sc->sc_rx_bufsize; 1174 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1175 1176 /* Has the packet rx completed ? if not then exit */ 1177 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1178 break; 1179 1180 /* 1181 * Did we have any errors? then note error and go to 1182 * next packet 1183 */ 1184 if (__predict_false(status & 1185 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1186 SEEQ_RXSTAT_SHORT_FRAME))) { 1187 ++ifp->if_ierrors; 1188 log(LOG_WARNING, 1189 "%s: rx packet error at %04x (err=%02x)\n", 1190 device_xname(&sc->sc_dev), addr, status & 0x0f); 1191 /* XXX shouldn't need to reset if it's genuine. */ 1192 ea_init(ifp); 1193 return; 1194 } 1195 /* 1196 * Is the packet too big? We allow slightly oversize packets 1197 * for vlan(4) and tcpdump purposes, but the rest of the world 1198 * wants incoming packets in a single mbuf cluster. 1199 */ 1200 if (__predict_false(len > MCLBYTES)) { 1201 ++ifp->if_ierrors; 1202 log(LOG_ERR, 1203 "%s: rx packet size error at %04x (len=%d)\n", 1204 device_xname(&sc->sc_dev), addr, len); 1205 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1206 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1207 sc->sc_config2); 1208 ea_init(ifp); 1209 return; 1210 } 1211 1212 ifp->if_ipackets++; 1213 /* Pass data up to upper levels. */ 1214 ea_read(sc, addr + 4, len); 1215 1216 addr = ptr; 1217 } while (len != 0); 1218 1219 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1220 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1221 1222 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1223 1224 /* Store new rx pointer */ 1225 sc->sc_rx_ptr = addr; 1226 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1227 1228 /* Make sure the receiver is on */ 1229 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1230 sc->sc_command | SEEQ_CMD_RX_ON); 1231} 1232 1233 1234/* 1235 * Pass a packet up to the higher levels. 1236 */ 1237 1238static void 1239ea_read(struct seeq8005_softc *sc, int addr, int len) 1240{ 1241 struct mbuf *m; 1242 struct ifnet *ifp; 1243 1244 ifp = &sc->sc_ethercom.ec_if; 1245 1246 /* Pull packet off interface. */ 1247 m = ea_get(sc, addr, len, ifp); 1248 if (m == 0) 1249 return; 1250 1251 /* 1252 * Check if there's a BPF listener on this interface. 1253 * If so, hand off the raw packet to bpf. 1254 */ 1255 if (ifp->if_bpf) 1256 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1257 1258 (*ifp->if_input)(ifp, m); 1259} 1260 1261/* 1262 * Pull read data off a interface. Len is length of data, with local net 1263 * header stripped. We copy the data into mbufs. When full cluster sized 1264 * units are present we copy into clusters. 1265 */ 1266 1267struct mbuf * 1268ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1269{ 1270 struct mbuf *top, **mp, *m; 1271 int len; 1272 u_int cp, epkt; 1273 1274 cp = addr; 1275 epkt = cp + totlen; 1276 1277 MGETHDR(m, M_DONTWAIT, MT_DATA); 1278 if (m == 0) 1279 return 0; 1280 m->m_pkthdr.rcvif = ifp; 1281 m->m_pkthdr.len = totlen; 1282 m->m_len = MHLEN; 1283 top = 0; 1284 mp = ⊤ 1285 1286 while (totlen > 0) { 1287 if (top) { 1288 MGET(m, M_DONTWAIT, MT_DATA); 1289 if (m == 0) { 1290 m_freem(top); 1291 return 0; 1292 } 1293 m->m_len = MLEN; 1294 } 1295 len = min(totlen, epkt - cp); 1296 if (len >= MINCLSIZE) { 1297 MCLGET(m, M_DONTWAIT); 1298 if (m->m_flags & M_EXT) 1299 m->m_len = len = min(len, MCLBYTES); 1300 else 1301 len = m->m_len; 1302 } else { 1303 /* 1304 * Place initial small packet/header at end of mbuf. 1305 */ 1306 if (len < m->m_len) { 1307 if (top == 0 && len + max_linkhdr <= m->m_len) 1308 m->m_data += max_linkhdr; 1309 m->m_len = len; 1310 } else 1311 len = m->m_len; 1312 } 1313 if (top == 0) { 1314 /* Make sure the payload is aligned */ 1315 char *newdata = (char *) 1316 ALIGN((char*)m->m_data + 1317 sizeof(struct ether_header)) - 1318 sizeof(struct ether_header); 1319 len -= newdata - m->m_data; 1320 m->m_len = len; 1321 m->m_data = newdata; 1322 } 1323 ea_readbuf(sc, mtod(m, u_char *), 1324 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1325 len); 1326 cp += len; 1327 *mp = m; 1328 mp = &m->m_next; 1329 totlen -= len; 1330 if (cp == epkt) 1331 cp = addr; 1332 } 1333 1334 return top; 1335} 1336 1337/* 1338 * Process an ioctl request. Mostly boilerplate. 1339 */ 1340static int 1341ea_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1342{ 1343 struct seeq8005_softc *sc = ifp->if_softc; 1344 int s, error = 0; 1345 1346 s = splnet(); 1347 switch (cmd) { 1348 1349 default: 1350 error = ether_ioctl(ifp, cmd, data); 1351 if (error == ENETRESET) { 1352 /* 1353 * Multicast list has changed; set the hardware filter 1354 * accordingly. 1355 */ 1356 if (ifp->if_flags & IFF_RUNNING) 1357 ea_mc_reset(sc); 1358 error = 0; 1359 } 1360 break; 1361 } 1362 1363 splx(s); 1364 return error; 1365} 1366 1367/* Must be called at splnet() */ 1368 1369static void 1370ea_mc_reset(struct seeq8005_softc *sc) 1371{ 1372 1373 switch (sc->sc_variant) { 1374 case SEEQ_8004: 1375 ea_mc_reset_8004(sc); 1376 return; 1377 case SEEQ_8005: 1378 ea_mc_reset_8005(sc); 1379 return; 1380 } 1381} 1382 1383static void 1384ea_mc_reset_8004(struct seeq8005_softc *sc) 1385{ 1386 struct ethercom *ec = &sc->sc_ethercom; 1387 struct ifnet *ifp = &ec->ec_if; 1388 struct ether_multi *enm; 1389 u_int32_t crc; 1390 int i; 1391 struct ether_multistep step; 1392 u_int8_t af[8]; 1393 1394 /* 1395 * Set up multicast address filter by passing all multicast addresses 1396 * through a crc generator, and then using bits 2 - 7 as an index 1397 * into the 64 bit logical address filter. The high order bits 1398 * selects the word, while the rest of the bits select the bit within 1399 * the word. 1400 */ 1401 1402 if (ifp->if_flags & IFF_PROMISC) { 1403 ifp->if_flags |= IFF_ALLMULTI; 1404 for (i = 0; i < 8; i++) 1405 af[i] = 0xff; 1406 return; 1407 } 1408 for (i = 0; i < 8; i++) 1409 af[i] = 0; 1410 ETHER_FIRST_MULTI(step, ec, enm); 1411 while (enm != NULL) { 1412 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1413 sizeof(enm->enm_addrlo)) != 0) { 1414 /* 1415 * We must listen to a range of multicast addresses. 1416 * For now, just accept all multicasts, rather than 1417 * trying to set only those filter bits needed to match 1418 * the range. (At this time, the only use of address 1419 * ranges is for IP multicast routing, for which the 1420 * range is big enough to require all bits set.) 1421 */ 1422 ifp->if_flags |= IFF_ALLMULTI; 1423 for (i = 0; i < 8; i++) 1424 af[i] = 0xff; 1425 break; 1426 } 1427 1428 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1429 1430 /* Just want the 6 most significant bits. */ 1431 crc = (crc >> 2) & 0x3f; 1432 1433 /* Turn on the corresponding bit in the filter. */ 1434 af[crc >> 3] |= 1 << (crc & 0x7); 1435 1436 ETHER_NEXT_MULTI(step, enm); 1437 } 1438 ifp->if_flags &= ~IFF_ALLMULTI; 1439 1440 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1441 for (i = 0; i < 8; ++i) 1442 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1443 SEEQ_BUFWIN, af[i]); 1444} 1445 1446static void 1447ea_mc_reset_8005(struct seeq8005_softc *sc) 1448{ 1449 struct ether_multi *enm; 1450 struct ether_multistep step; 1451 int naddr, maxaddrs; 1452 1453 naddr = 0; 1454 maxaddrs = 5; 1455 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1456 while (enm != NULL) { 1457 /* Have we got space? */ 1458 if (naddr >= maxaddrs || 1459 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1460 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1461 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1462 return; 1463 } 1464 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1465 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1466 naddr++; 1467 ETHER_NEXT_MULTI(step, enm); 1468 } 1469 for (; naddr < maxaddrs; naddr++) 1470 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1471 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1472 sc->sc_config1); 1473} 1474 1475/* 1476 * Device timeout routine. 1477 */ 1478 1479static void 1480ea_watchdog(struct ifnet *ifp) 1481{ 1482 struct seeq8005_softc *sc = ifp->if_softc; 1483 1484 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1485 device_xname(&sc->sc_dev), 1486 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1487 ifp->if_oerrors++; 1488 1489 /* Kick the interface */ 1490 1491 ea_init(ifp); 1492 1493 ifp->if_timer = 0; 1494} 1495 1496/* End of if_ea.c */ 1497