seeq8005.c revision 1.31
1/* $NetBSD: seeq8005.c,v 1.31 2001/11/13 13:14:43 lukem Exp $ */ 2 3/* 4 * Copyright (c) 2000, 2001 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36/* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39/* 40 * This driver currently supports the following chips: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45/* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52/* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56/* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63#include <sys/cdefs.h> 64__KERNEL_RCSID(0, "$NetBSD: seeq8005.c,v 1.31 2001/11/13 13:14:43 lukem Exp $"); 65 66#include <sys/types.h> 67#include <sys/param.h> 68#include <sys/systm.h> 69#include <sys/endian.h> 70#include <sys/errno.h> 71#include <sys/ioctl.h> 72#include <sys/mbuf.h> 73#include <sys/socket.h> 74#include <sys/syslog.h> 75#include <sys/device.h> 76 77#include <net/if.h> 78#include <net/if_dl.h> 79#include <net/if_types.h> 80#include <net/if_ether.h> 81#include <net/if_media.h> 82 83#include "bpfilter.h" 84#if NBPFILTER > 0 85#include <net/bpf.h> 86#include <net/bpfdesc.h> 87#endif 88 89#include "rnd.h" 90#if NRND > 0 91#include <sys/rnd.h> 92#endif 93 94#include <machine/bus.h> 95#include <machine/intr.h> 96 97#include <dev/ic/seeq8005reg.h> 98#include <dev/ic/seeq8005var.h> 99 100/*#define SEEQ_DEBUG*/ 101 102/* for debugging convenience */ 103#ifdef SEEQ8005_DEBUG 104#define SEEQ_DEBUG_MISC 1 105#define SEEQ_DEBUG_TX 2 106#define SEEQ_DEBUG_RX 4 107#define SEEQ_DEBUG_PKT 8 108#define SEEQ_DEBUG_TXINT 16 109#define SEEQ_DEBUG_RXINT 32 110int seeq8005_debug = 0; 111#define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 112#else 113#define DPRINTF(f, x) 114#endif 115 116#define SEEQ_TX_BUFFER_SIZE 0x800 /* (> ETHER_MAX_LEN) */ 117 118#define SEEQ_READ16(sc, iot, ioh, reg) \ 119 ((sc)->sc_flags & SF_8BIT ? \ 120 (bus_space_read_1((iot), (ioh), (reg)) | \ 121 (bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \ 122 (bus_space_read_2((iot), (ioh), (reg)))) 123 124#define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \ 125 if ((sc)->sc_flags & SF_8BIT) { \ 126 bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \ 127 bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \ 128 } else \ 129 bus_space_write_2((iot), (ioh), (reg), (val)); \ 130} while (/*CONSTCOND*/0) 131 132/* 133 * prototypes 134 */ 135 136static int ea_init(struct ifnet *); 137static int ea_ioctl(struct ifnet *, u_long, caddr_t); 138static void ea_start(struct ifnet *); 139static void ea_watchdog(struct ifnet *); 140static void ea_chipreset(struct seeq8005_softc *); 141static void ea_ramtest(struct seeq8005_softc *); 142static int ea_stoptx(struct seeq8005_softc *); 143static int ea_stoprx(struct seeq8005_softc *); 144static void ea_stop(struct ifnet *, int); 145static void ea_await_fifo_empty(struct seeq8005_softc *); 146static void ea_await_fifo_full(struct seeq8005_softc *); 147static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 148static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 149static void ea_select_buffer(struct seeq8005_softc *, int); 150static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 151static void ea_read(struct seeq8005_softc *, int, int); 152static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 153static void ea_txint(struct seeq8005_softc *); 154static void ea_rxint(struct seeq8005_softc *); 155static void eatxpacket(struct seeq8005_softc *); 156static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 157static void ea_mc_reset(struct seeq8005_softc *); 158static void ea_mc_reset_8004(struct seeq8005_softc *); 159static void ea_mc_reset_8005(struct seeq8005_softc *); 160static int ea_mediachange(struct ifnet *); 161static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 162 163 164/* 165 * Attach chip. 166 */ 167 168void 169seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 170 int nmedia, int defmedia) 171{ 172 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 173 bus_space_tag_t iot = sc->sc_iot; 174 bus_space_handle_t ioh = sc->sc_ioh; 175 u_int id; 176 177 KASSERT(myaddr != NULL); 178 printf(" address %s", ether_sprintf(myaddr)); 179 180 /* Stop the board. */ 181 182 ea_chipreset(sc); 183 184 /* Work out data bus width. */ 185 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 186 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 187 /* Try 8-bit mode */ 188 sc->sc_flags |= SF_8BIT; 189 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, 0x1234); 190 if (SEEQ_READ16(sc, iot, ioh, SEEQ_RX_PTR) != 0x1234) { 191 printf("\n%s: Cannot determine data bus width\n", 192 sc->sc_dev.dv_xname); 193 return; 194 } 195 } 196 197 printf(", %d-bit", sc->sc_flags & SF_8BIT ? 8 : 16); 198 199 /* Get the product ID */ 200 201 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 202 id = SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 203 204 switch (id & SEEQ_PRODUCTID_MASK) { 205 case SEEQ_PRODUCTID_8004: 206 sc->sc_variant = SEEQ_8004; 207 switch (id & SEEQ_PRODUCTID_REV_MASK) { 208 case SEEQ_PRODUCTID_REV_80C04: 209 printf(", SEEQ 80C04\n"); 210 break; 211 case SEEQ_PRODUCTID_REV_80C04A: 212 printf(", SEEQ 80C04A\n"); 213 break; 214 default: 215 /* Unknown SEEQ 8004 variants */ 216 printf(", SEEQ 8004 rev %x\n", 217 id & SEEQ_PRODUCTID_REV_MASK); 218 break; 219 } 220 break; 221 default: /* XXX */ 222 sc->sc_variant = SEEQ_8005; 223 printf(", SEEQ 8005\n"); 224 break; 225 } 226 227 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 228 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 229 230 /* 231 * Set up tx and rx buffers. 232 * 233 * We use approximately a quarter of the packet memory for TX 234 * buffers and the rest for RX buffers 235 */ 236 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 237 sc->sc_tx_bufs = 1; 238 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 239 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 240 sc->sc_enabled = 0; 241 242 /* Test the RAM */ 243 ea_ramtest(sc); 244 245 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 246 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 247 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 248 249 /* Initialise ifnet structure. */ 250 251 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 252 ifp->if_softc = sc; 253 ifp->if_start = ea_start; 254 ifp->if_ioctl = ea_ioctl; 255 ifp->if_init = ea_init; 256 ifp->if_stop = ea_stop; 257 ifp->if_watchdog = ea_watchdog; 258 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 259 if (sc->sc_variant == SEEQ_8004) 260 ifp->if_flags |= IFF_SIMPLEX; 261 IFQ_SET_READY(&ifp->if_snd); 262 263 /* Initialize media goo. */ 264 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 265 if (media != NULL) { 266 int i; 267 268 for (i = 0; i < nmedia; i++) 269 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 270 ifmedia_set(&sc->sc_media, defmedia); 271 } else { 272 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 273 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 274 } 275 276 /* We can support 802.1Q VLAN-sized frames. */ 277 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 278 279 /* Now we can attach the interface. */ 280 281 if_attach(ifp); 282 ether_ifattach(ifp, myaddr); 283 284 printf("\n"); 285 286#if NRND > 0 287 /* After \n because it can print a line of its own. */ 288 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 289 RND_TYPE_NET, 0); 290#endif 291} 292 293/* 294 * Media change callback. 295 */ 296static int 297ea_mediachange(struct ifnet *ifp) 298{ 299 struct seeq8005_softc *sc = ifp->if_softc; 300 301 if (sc->sc_mediachange) 302 return ((*sc->sc_mediachange)(sc)); 303 return (EINVAL); 304} 305 306/* 307 * Media status callback. 308 */ 309static void 310ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 311{ 312 struct seeq8005_softc *sc = ifp->if_softc; 313 314 if (sc->sc_enabled == 0) { 315 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 316 ifmr->ifm_status = 0; 317 return; 318 } 319 320 if (sc->sc_mediastatus) 321 (*sc->sc_mediastatus)(sc, ifmr); 322} 323 324/* 325 * Test the RAM on the ethernet card. 326 */ 327 328void 329ea_ramtest(struct seeq8005_softc *sc) 330{ 331 bus_space_tag_t iot = sc->sc_iot; 332 bus_space_handle_t ioh = sc->sc_ioh; 333 int loop; 334 u_int sum = 0; 335 336 /* 337 * Test the buffer memory on the board. 338 * Write simple pattens to it and read them back. 339 */ 340 341 /* Set up the whole buffer RAM for writing */ 342 343 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 344 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 345 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 346 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 347 348#define SEEQ_RAMTEST_LOOP(value) \ 349do { \ 350 /* Set the write start address and write a pattern */ \ 351 ea_writebuf(sc, NULL, 0x0000, 0); \ 352 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 353 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (value)); \ 354 \ 355 /* Set the read start address and verify the pattern */ \ 356 ea_readbuf(sc, NULL, 0x0000, 0); \ 357 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 358 if (SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN) != (value)) \ 359 ++sum; \ 360} while (/*CONSTCOND*/0) 361 362 SEEQ_RAMTEST_LOOP(loop); 363 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 364 SEEQ_RAMTEST_LOOP(0xaa55); 365 SEEQ_RAMTEST_LOOP(0x55aa); 366 367 /* Report */ 368 369 if (sum > 0) 370 printf("%s: buffer RAM failed self test, %d faults\n", 371 sc->sc_dev.dv_xname, sum); 372} 373 374 375/* 376 * Stop the tx interface. 377 * 378 * Returns 0 if the tx was already stopped or 1 if it was active 379 */ 380 381static int 382ea_stoptx(struct seeq8005_softc *sc) 383{ 384 bus_space_tag_t iot = sc->sc_iot; 385 bus_space_handle_t ioh = sc->sc_ioh; 386 int timeout; 387 int status; 388 389 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 390 391 sc->sc_enabled = 0; 392 393 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 394 if (!(status & SEEQ_STATUS_TX_ON)) 395 return 0; 396 397 /* Stop any tx and wait for confirmation */ 398 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 399 sc->sc_command | SEEQ_CMD_TX_OFF); 400 401 timeout = 20000; 402 do { 403 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 404 delay(1); 405 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 406 if (timeout == 0) 407 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 408 sc->sc_dev.dv_xname); 409 410 /* Clear any pending tx interrupt */ 411 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 412 sc->sc_command | SEEQ_CMD_TX_INTACK); 413 return 1; 414} 415 416 417/* 418 * Stop the rx interface. 419 * 420 * Returns 0 if the tx was already stopped or 1 if it was active 421 */ 422 423static int 424ea_stoprx(struct seeq8005_softc *sc) 425{ 426 bus_space_tag_t iot = sc->sc_iot; 427 bus_space_handle_t ioh = sc->sc_ioh; 428 int timeout; 429 int status; 430 431 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 432 433 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 434 if (!(status & SEEQ_STATUS_RX_ON)) 435 return 0; 436 437 /* Stop any rx and wait for confirmation */ 438 439 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 440 sc->sc_command | SEEQ_CMD_RX_OFF); 441 442 timeout = 20000; 443 do { 444 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 445 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 446 if (timeout == 0) 447 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 448 sc->sc_dev.dv_xname); 449 450 /* Clear any pending rx interrupt */ 451 452 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 453 sc->sc_command | SEEQ_CMD_RX_INTACK); 454 return 1; 455} 456 457 458/* 459 * Stop interface. 460 * Stop all IO and shut the interface down 461 */ 462 463static void 464ea_stop(struct ifnet *ifp, int disable) 465{ 466 struct seeq8005_softc *sc = ifp->if_softc; 467 bus_space_tag_t iot = sc->sc_iot; 468 bus_space_handle_t ioh = sc->sc_ioh; 469 470 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 471 472 /* Stop all IO */ 473 ea_stoptx(sc); 474 ea_stoprx(sc); 475 476 /* Disable rx and tx interrupts */ 477 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 478 479 /* Clear any pending interrupts */ 480 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 481 sc->sc_command | SEEQ_CMD_RX_INTACK | 482 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 483 SEEQ_CMD_BW_INTACK); 484 485 if (sc->sc_variant == SEEQ_8004) { 486 /* Put the chip to sleep */ 487 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 488 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 489 sc->sc_config3 | SEEQ_CFG3_SLEEP); 490 } 491 492 /* Cancel any watchdog timer */ 493 sc->sc_ethercom.ec_if.if_timer = 0; 494} 495 496 497/* 498 * Reset the chip 499 * Following this the software registers are reset 500 */ 501 502static void 503ea_chipreset(struct seeq8005_softc *sc) 504{ 505 bus_space_tag_t iot = sc->sc_iot; 506 bus_space_handle_t ioh = sc->sc_ioh; 507 508 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 509 510 /* Reset the controller. Min of 4us delay here */ 511 512 /* 513 * This can be called before we know whether the chip is in 8- or 514 * 16-bit mode, so we do a reset in both modes. The 16-bit reset is 515 * harmless in 8-bit mode, so we do that second. 516 */ 517 518 /* In 16-bit mode, this will munge the PreamSelect bit. */ 519 bus_space_write_1(iot, ioh, SEEQ_CONFIG2 + 1, SEEQ_CFG2_RESET >> 8); 520 delay(4); 521 /* In 8-bit mode, this will zero the bottom half of config reg 2. */ 522 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 523 delay(4); 524 525 sc->sc_command = 0; 526 sc->sc_config1 = 0; 527 sc->sc_config2 = 0; 528 sc->sc_config3 = 0; 529} 530 531 532/* 533 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 534 * switching the FIFO from write to read. We also use it when changing 535 * the address for writes. 536 */ 537static void 538ea_await_fifo_empty(struct seeq8005_softc *sc) 539{ 540 bus_space_tag_t iot = sc->sc_iot; 541 bus_space_handle_t ioh = sc->sc_ioh; 542 int timeout; 543 544 timeout = 20000; 545 if ((SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 546 SEEQ_STATUS_FIFO_DIR) != 0) 547 return; /* FIFO is reading anyway. */ 548 while (--timeout > 0) 549 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 550 SEEQ_STATUS_FIFO_EMPTY) 551 return; 552 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 553} 554 555/* 556 * Wait for the DMA FIFO to fill before reading from it. 557 */ 558static void 559ea_await_fifo_full(struct seeq8005_softc *sc) 560{ 561 bus_space_tag_t iot = sc->sc_iot; 562 bus_space_handle_t ioh = sc->sc_ioh; 563 int timeout; 564 565 timeout = 20000; 566 while (--timeout > 0) 567 if (SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS) & 568 SEEQ_STATUS_FIFO_FULL) 569 return; 570 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 571} 572 573/* 574 * write to the buffer memory on the interface 575 * 576 * The buffer address is set to ADDR. 577 * If len != 0 then data is copied from the address starting at buf 578 * to the interface buffer. 579 * BUF must be usable as a u_int16_t *. 580 * If LEN is odd, it must be safe to overwrite one extra byte. 581 */ 582 583static void 584ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 585{ 586 bus_space_tag_t iot = sc->sc_iot; 587 bus_space_handle_t ioh = sc->sc_ioh; 588 589 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 590 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 591 592#ifdef DIAGNOSTIC 593 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 594 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 595 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 596 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 597#endif 598 599 /* Assume that copying too much is safe. */ 600 if (len % 2 != 0) 601 len++; 602 603 if (addr != -1) { 604 ea_await_fifo_empty(sc); 605 606 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 607 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 608 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 609 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr); 610 } 611 612 if (len > 0) { 613 if (sc->sc_flags & SF_8BIT) 614 bus_space_write_multi_1(iot, ioh, SEEQ_BUFWIN, 615 (u_int8_t *)buf, len); 616 else 617 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 618 (u_int16_t *)buf, len / 2); 619 } 620 /* Leave FIFO to empty in the background */ 621} 622 623 624/* 625 * read from the buffer memory on the interface 626 * 627 * The buffer address is set to ADDR. 628 * If len != 0 then data is copied from the interface buffer to the 629 * address starting at buf. 630 * BUF must be usable as a u_int16_t *. 631 * If LEN is odd, it must be safe to overwrite one extra byte. 632 */ 633 634static void 635ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 636{ 637 bus_space_tag_t iot = sc->sc_iot; 638 bus_space_handle_t ioh = sc->sc_ioh; 639 int runup; 640 641 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 642 SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS), addr, len)); 643 644#ifdef DIAGNOSTIC 645 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 646 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 647 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 648 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 649#endif 650 651 /* Assume that copying too much is safe. */ 652 if (len % 2 != 0) 653 len++; 654 655 if (addr != -1) { 656 /* 657 * SEEQ 80C04 bug: 658 * Starting reading from certain addresses seems to cause 659 * us to get bogus results, so we avoid them. 660 */ 661 runup = 0; 662 if (sc->sc_variant == SEEQ_8004 && 663 ((addr & 0x00ff) == 0x00ea || 664 (addr & 0x00ff) == 0x00ee || 665 (addr & 0x00ff) == 0x00f0)) 666 runup = (addr & 0x00ff) - 0x00e8; 667 668 ea_await_fifo_empty(sc); 669 670 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 671 672 /* 673 * 80C04 bug workaround. I found this in the old arm32 "eb" 674 * driver. I've no idea what it does, but it seems to stop 675 * the chip mangling data so often. 676 */ 677 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 678 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 679 ea_await_fifo_empty(sc); 680 681 SEEQ_WRITE16(sc, iot, ioh, SEEQ_DMA_ADDR, addr - runup); 682 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 683 sc->sc_command | SEEQ_CMD_FIFO_READ); 684 685 ea_await_fifo_full(sc); 686 while (runup > 0) { 687 (void)SEEQ_READ16(sc, iot, ioh, SEEQ_BUFWIN); 688 runup -= 2; 689 } 690 } 691 692 if (len > 0) { 693 if (sc->sc_flags & SF_8BIT) 694 bus_space_read_multi_1(iot, ioh, SEEQ_BUFWIN, 695 (u_int8_t *)buf, len); 696 else 697 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 698 (u_int16_t *)buf, len / 2); 699 } 700} 701 702static void 703ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 704{ 705 706 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 707 sc->sc_config1 | bufcode); 708} 709 710/* Must be called at splnet */ 711static void 712ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 713{ 714 int i; 715 716 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 717 for (i = 0; i < ETHER_ADDR_LEN; ++i) 718 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 719 ea[i]); 720} 721 722/* 723 * Initialize interface. 724 * 725 * This should leave the interface in a state for packet reception and 726 * transmission. 727 */ 728 729static int 730ea_init(struct ifnet *ifp) 731{ 732 struct seeq8005_softc *sc = ifp->if_softc; 733 bus_space_tag_t iot = sc->sc_iot; 734 bus_space_handle_t ioh = sc->sc_ioh; 735 int s; 736 737 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 738 739 s = splnet(); 740 741 /* First, reset the board. */ 742 743 ea_chipreset(sc); 744 745 /* Set up defaults for the registers */ 746 747 sc->sc_command = 0; 748 sc->sc_config1 = 0; 749#if BYTE_ORDER == BIG_ENDIAN 750 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 751#else 752 sc->sc_config2 = 0; 753#endif 754 sc->sc_config3 = 0; 755 756 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 757 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 758 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 759 if (sc->sc_variant == SEEQ_8004) { 760 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 761 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 762 } 763 764 /* Write the station address - the receiver must be off */ 765 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 766 767 /* Split board memory into Rx and Tx. */ 768 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 769 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 770 771 if (sc->sc_variant == SEEQ_8004) { 772 /* Make the interface IFF_SIMPLEX. */ 773 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 774 /* Enable reception of long packets (for vlan(4)). */ 775 sc->sc_config2 |= SEEQ_CFG2_PASS_LONGSHORT; 776 } 777 778 /* Configure rx. */ 779 ea_mc_reset(sc); 780 if (ifp->if_flags & IFF_PROMISC) 781 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 782 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 783 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 784 else 785 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 786 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 787 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 788 789 /* Setup the Rx pointers */ 790 sc->sc_rx_ptr = sc->sc_tx_bufsize; 791 792 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 793 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 794 795 796 /* Place a NULL header at the beginning of the receive area */ 797 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 798 799 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 800 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 801 802 803 /* Configure TX. */ 804 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 805 806 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 807 808 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 809 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 810 811 /* Reset tx buffer pointers */ 812 sc->sc_tx_cur = 0; 813 sc->sc_tx_used = 0; 814 sc->sc_tx_next = 0; 815 816 /* Place a NULL header at the beginning of the transmit area */ 817 ea_writebuf(sc, NULL, 0x0000, 0); 818 819 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 820 SEEQ_WRITE16(sc, iot, ioh, SEEQ_BUFWIN, 0x0000); 821 822 sc->sc_command |= SEEQ_CMD_TX_INTEN; 823 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, sc->sc_command); 824 825 /* Turn on Rx */ 826 sc->sc_command |= SEEQ_CMD_RX_INTEN; 827 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 828 sc->sc_command | SEEQ_CMD_RX_ON); 829 830 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 831 832 833 /* Set flags appropriately. */ 834 ifp->if_flags |= IFF_RUNNING; 835 ifp->if_flags &= ~IFF_OACTIVE; 836 sc->sc_enabled = 1; 837 838 /* And start output. */ 839 ea_start(ifp); 840 841 splx(s); 842 return 0; 843} 844 845/* 846 * Start output on interface. Get datagrams from the queue and output them, 847 * giving the receiver a chance between datagrams. Call only from splnet or 848 * interrupt level! 849 */ 850 851static void 852ea_start(struct ifnet *ifp) 853{ 854 struct seeq8005_softc *sc = ifp->if_softc; 855 int s; 856 857 s = splnet(); 858 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 859 860 /* 861 * Don't do anything if output is active. seeq8005intr() will call 862 * us (actually eatxpacket()) back when the card's ready for more 863 * frames. 864 */ 865 if (ifp->if_flags & IFF_OACTIVE) 866 return; 867 868 /* Mark interface as output active */ 869 870 ifp->if_flags |= IFF_OACTIVE; 871 872 /* tx packets */ 873 874 eatxpacket(sc); 875 splx(s); 876} 877 878 879/* 880 * Transfer a packet to the interface buffer and start transmission 881 * 882 * Called at splnet() 883 */ 884 885void 886eatxpacket(struct seeq8005_softc *sc) 887{ 888 bus_space_tag_t iot = sc->sc_iot; 889 bus_space_handle_t ioh = sc->sc_ioh; 890 struct mbuf *m0; 891 struct ifnet *ifp; 892 893 ifp = &sc->sc_ethercom.ec_if; 894 895 /* Dequeue the next packet. */ 896 IFQ_DEQUEUE(&ifp->if_snd, m0); 897 898 /* If there's nothing to send, return. */ 899 if (!m0) { 900 ifp->if_flags &= ~IFF_OACTIVE; 901 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 902 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 903 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 904 return; 905 } 906 907#if NBPFILTER > 0 908 /* Give the packet to the bpf, if any. */ 909 if (ifp->if_bpf) 910 bpf_mtap(ifp->if_bpf, m0); 911#endif 912 913 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 914 915 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 916 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 917 918 ea_writembuf(sc, m0, 0x0000); 919 m_freem(m0); 920 921 SEEQ_WRITE16(sc, iot, ioh, SEEQ_TX_PTR, 0x0000); 922 923 /* Now transmit the datagram. */ 924 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 925 sc->sc_command | SEEQ_CMD_TX_ON); 926 927 /* Make sure we notice if the chip goes silent on us. */ 928 ifp->if_timer = 5; 929 930 DPRINTF(SEEQ_DEBUG_TX, 931 ("st=%04x\n", SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS))); 932 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 933} 934 935/* 936 * Copy a packet from an mbuf to the transmit buffer on the card. 937 * 938 * Puts a valid Tx header at the start of the packet, and a null header at 939 * the end. 940 */ 941static int 942ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 943{ 944 struct mbuf *m; 945 int len, nextpacket; 946 u_int8_t hdr[4]; 947 948 /* 949 * Copy the datagram to the packet buffer. 950 */ 951 len = 0; 952 for (m = m0; m; m = m->m_next) { 953 if (m->m_len == 0) 954 continue; 955 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 956 m->m_len); 957 len += m->m_len; 958 } 959 960 len = max(len, ETHER_MIN_LEN); 961 962 /* Follow it with a NULL packet header */ 963 memset(hdr, 0, 4); 964 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 965 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 966 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 967 968 /* Ok we now have a packet len bytes long in our packet buffer */ 969 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 970 971 /* Write the packet header */ 972 nextpacket = len + 4; 973 hdr[0] = (nextpacket >> 8) & 0xff; 974 hdr[1] = nextpacket & 0xff; 975 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 976 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 977 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 978 ea_writebuf(sc, hdr, 0x0000, 4); 979 980 return len; 981} 982 983/* 984 * Ethernet controller interrupt. 985 */ 986 987int 988seeq8005intr(void *arg) 989{ 990 struct seeq8005_softc *sc = arg; 991 bus_space_tag_t iot = sc->sc_iot; 992 bus_space_handle_t ioh = sc->sc_ioh; 993 int status, handled; 994 995 handled = 0; 996 997 /* Get the controller status */ 998 status = SEEQ_READ16(sc, iot, ioh, SEEQ_STATUS); 999 1000 /* Tx interrupt ? */ 1001 if (status & SEEQ_STATUS_TX_INT) { 1002 handled = 1; 1003 1004 /* Acknowledge the interrupt */ 1005 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1006 sc->sc_command | SEEQ_CMD_TX_INTACK); 1007 1008 ea_txint(sc); 1009 } 1010 1011 1012 /* Rx interrupt ? */ 1013 if (status & SEEQ_STATUS_RX_INT) { 1014 handled = 1; 1015 1016 /* Acknowledge the interrupt */ 1017 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1018 sc->sc_command | SEEQ_CMD_RX_INTACK); 1019 1020 /* Processes the received packets */ 1021 ea_rxint(sc); 1022 } 1023 1024#if NRND > 0 1025 if (handled) 1026 rnd_add_uint32(&sc->rnd_source, status); 1027#endif 1028 return handled; 1029} 1030 1031static void 1032ea_txint(struct seeq8005_softc *sc) 1033{ 1034 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1035 bus_space_tag_t iot = sc->sc_iot; 1036 bus_space_handle_t ioh = sc->sc_ioh; 1037 u_int8_t txhdr[4]; 1038 u_int txstatus; 1039 1040 ea_readbuf(sc, txhdr, 0x0000, 4); 1041 1042 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 1043 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 1044 txstatus = txhdr[3]; 1045 1046 /* 1047 * If SEEQ_TXSTAT_COLLISION is set then we received at least 1048 * one collision. On the 8004 we can find out exactly how many 1049 * collisions occurred. 1050 * 1051 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 1052 * completed. 1053 * 1054 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 1055 * occurred and the packet transmission was aborted. 1056 * This situation is untested as present. 1057 * 1058 * The SEEQ_TXSTAT_BABBLE is untested as it should only be set 1059 * when we deliberately transmit oversized packets (e.g. for 1060 * 802.1Q). 1061 */ 1062 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1063 switch (sc->sc_variant) { 1064 case SEEQ_8004: { 1065 int colls; 1066 1067 /* 1068 * The 8004 contains a 4 bit collision count 1069 * in the status register. 1070 */ 1071 1072 /* This appears to be broken on 80C04.AE */ 1073/* ifp->if_collisions += 1074 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1075 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1076 1077 /* Use the TX Collision register */ 1078 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1079 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1080 ifp->if_collisions += colls; 1081 break; 1082 } 1083 case SEEQ_8005: 1084 /* We known there was at least 1 collision */ 1085 ifp->if_collisions++; 1086 break; 1087 } 1088 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1089 printf("seeq_intr: col16 %x\n", txstatus); 1090 ifp->if_collisions += 16; 1091 ifp->if_oerrors++; 1092 } 1093 1094 /* Have we completed transmission on the packet ? */ 1095 if (txstatus & SEEQ_PKTSTAT_DONE) { 1096 /* Clear watchdog timer. */ 1097 ifp->if_timer = 0; 1098 ifp->if_flags &= ~IFF_OACTIVE; 1099 1100 /* Update stats */ 1101 ifp->if_opackets++; 1102 1103 /* Tx next packet */ 1104 1105 eatxpacket(sc); 1106 } 1107} 1108 1109void 1110ea_rxint(struct seeq8005_softc *sc) 1111{ 1112 bus_space_tag_t iot = sc->sc_iot; 1113 bus_space_handle_t ioh = sc->sc_ioh; 1114 u_int addr; 1115 int len; 1116 int ctrl; 1117 int ptr; 1118 int pack; 1119 int status; 1120 u_int8_t rxhdr[4]; 1121 struct ifnet *ifp; 1122 1123 ifp = &sc->sc_ethercom.ec_if; 1124 1125 1126 /* We start from the last rx pointer position */ 1127 addr = sc->sc_rx_ptr; 1128 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1129 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1130 1131 do { 1132 /* Read rx header */ 1133 ea_readbuf(sc, rxhdr, addr, 4); 1134 1135 /* Split the packet header */ 1136 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1137 ctrl = rxhdr[2]; 1138 status = rxhdr[3]; 1139 1140 DPRINTF(SEEQ_DEBUG_RX, 1141 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1142 addr, ptr, ctrl, status)); 1143 1144 /* Zero packet ptr ? then must be null header so exit */ 1145 if (ptr == 0) break; 1146 1147 /* Sanity-check the next-packet pointer and flags. */ 1148 if (__predict_false(ptr < sc->sc_tx_bufsize || 1149 (ctrl & SEEQ_PKTCMD_TX))) { 1150 ++ifp->if_ierrors; 1151 log(LOG_ERR, 1152 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1153 sc->sc_dev.dv_xname, addr, ptr); 1154 ea_init(ifp); 1155 return; 1156 } 1157 1158 /* Get packet length */ 1159 len = (ptr - addr) - 4; 1160 1161 if (len < 0) 1162 len += sc->sc_rx_bufsize; 1163 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1164 1165 /* Has the packet rx completed ? if not then exit */ 1166 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1167 break; 1168 1169 /* 1170 * Did we have any errors? then note error and go to 1171 * next packet 1172 */ 1173 if (__predict_false(status & 1174 (SEEQ_RXSTAT_CRC_ERROR | SEEQ_RXSTAT_DRIBBLE_ERROR | 1175 SEEQ_RXSTAT_SHORT_FRAME))) { 1176 ++ifp->if_ierrors; 1177 log(LOG_WARNING, 1178 "%s: rx packet error at %04x (err=%02x)\n", 1179 sc->sc_dev.dv_xname, addr, status & 0x0f); 1180 /* XXX shouldn't need to reset if it's genuine. */ 1181 ea_init(ifp); 1182 return; 1183 } 1184 /* 1185 * Is the packet too big? We allow slightly oversize packets 1186 * for vlan(4) and tcpdump purposes, but the rest of the world 1187 * wants incoming packets in a single mbuf cluster. 1188 */ 1189 if (__predict_false(len > MCLBYTES)) { 1190 ++ifp->if_ierrors; 1191 log(LOG_ERR, 1192 "%s: rx packet size error at %04x (len=%d)\n", 1193 sc->sc_dev.dv_xname, addr, len); 1194 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1195 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, 1196 sc->sc_config2); 1197 ea_init(ifp); 1198 return; 1199 } 1200 1201 ifp->if_ipackets++; 1202 /* Pass data up to upper levels. */ 1203 ea_read(sc, addr + 4, len); 1204 1205 addr = ptr; 1206 ++pack; 1207 } while (len != 0); 1208 1209 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1210 SEEQ_WRITE16(sc, iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1211 1212 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1213 1214 /* Store new rx pointer */ 1215 sc->sc_rx_ptr = addr; 1216 SEEQ_WRITE16(sc, iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1217 1218 /* Make sure the receiver is on */ 1219 SEEQ_WRITE16(sc, iot, ioh, SEEQ_COMMAND, 1220 sc->sc_command | SEEQ_CMD_RX_ON); 1221} 1222 1223 1224/* 1225 * Pass a packet up to the higher levels. 1226 */ 1227 1228static void 1229ea_read(struct seeq8005_softc *sc, int addr, int len) 1230{ 1231 struct mbuf *m; 1232 struct ifnet *ifp; 1233 1234 ifp = &sc->sc_ethercom.ec_if; 1235 1236 /* Pull packet off interface. */ 1237 m = ea_get(sc, addr, len, ifp); 1238 if (m == 0) 1239 return; 1240 1241#if NBPFILTER > 0 1242 /* 1243 * Check if there's a BPF listener on this interface. 1244 * If so, hand off the raw packet to bpf. 1245 */ 1246 if (ifp->if_bpf) 1247 bpf_mtap(ifp->if_bpf, m); 1248#endif 1249 1250 (*ifp->if_input)(ifp, m); 1251} 1252 1253/* 1254 * Pull read data off a interface. Len is length of data, with local net 1255 * header stripped. We copy the data into mbufs. When full cluster sized 1256 * units are present we copy into clusters. 1257 */ 1258 1259struct mbuf * 1260ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1261{ 1262 struct mbuf *top, **mp, *m; 1263 int len; 1264 u_int cp, epkt; 1265 1266 cp = addr; 1267 epkt = cp + totlen; 1268 1269 MGETHDR(m, M_DONTWAIT, MT_DATA); 1270 if (m == 0) 1271 return 0; 1272 m->m_pkthdr.rcvif = ifp; 1273 m->m_pkthdr.len = totlen; 1274 m->m_len = MHLEN; 1275 top = 0; 1276 mp = ⊤ 1277 1278 while (totlen > 0) { 1279 if (top) { 1280 MGET(m, M_DONTWAIT, MT_DATA); 1281 if (m == 0) { 1282 m_freem(top); 1283 return 0; 1284 } 1285 m->m_len = MLEN; 1286 } 1287 len = min(totlen, epkt - cp); 1288 if (len >= MINCLSIZE) { 1289 MCLGET(m, M_DONTWAIT); 1290 if (m->m_flags & M_EXT) 1291 m->m_len = len = min(len, MCLBYTES); 1292 else 1293 len = m->m_len; 1294 } else { 1295 /* 1296 * Place initial small packet/header at end of mbuf. 1297 */ 1298 if (len < m->m_len) { 1299 if (top == 0 && len + max_linkhdr <= m->m_len) 1300 m->m_data += max_linkhdr; 1301 m->m_len = len; 1302 } else 1303 len = m->m_len; 1304 } 1305 if (top == 0) { 1306 /* Make sure the payload is aligned */ 1307 caddr_t newdata = (caddr_t) 1308 ALIGN(m->m_data + sizeof(struct ether_header)) - 1309 sizeof(struct ether_header); 1310 len -= newdata - m->m_data; 1311 m->m_len = len; 1312 m->m_data = newdata; 1313 } 1314 ea_readbuf(sc, mtod(m, u_char *), 1315 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1316 len); 1317 cp += len; 1318 *mp = m; 1319 mp = &m->m_next; 1320 totlen -= len; 1321 if (cp == epkt) 1322 cp = addr; 1323 } 1324 1325 return top; 1326} 1327 1328/* 1329 * Process an ioctl request. Mostly boilerplate. 1330 */ 1331static int 1332ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1333{ 1334 struct seeq8005_softc *sc = ifp->if_softc; 1335 int s, error = 0; 1336 1337 s = splnet(); 1338 switch (cmd) { 1339 1340 default: 1341 error = ether_ioctl(ifp, cmd, data); 1342 if (error == ENETRESET) { 1343 /* 1344 * Multicast list has changed; set the hardware filter 1345 * accordingly. 1346 */ 1347 ea_mc_reset(sc); 1348 error = 0; 1349 } 1350 break; 1351 } 1352 1353 splx(s); 1354 return error; 1355} 1356 1357/* Must be called at splnet() */ 1358 1359static void 1360ea_mc_reset(struct seeq8005_softc *sc) 1361{ 1362 1363 switch (sc->sc_variant) { 1364 case SEEQ_8004: 1365 ea_mc_reset_8004(sc); 1366 return; 1367 case SEEQ_8005: 1368 ea_mc_reset_8005(sc); 1369 return; 1370 } 1371} 1372 1373static void 1374ea_mc_reset_8004(struct seeq8005_softc *sc) 1375{ 1376 struct ethercom *ec = &sc->sc_ethercom; 1377 struct ifnet *ifp = &ec->ec_if; 1378 struct ether_multi *enm; 1379 u_int32_t crc; 1380 int i; 1381 struct ether_multistep step; 1382 u_int8_t af[8]; 1383 1384 /* 1385 * Set up multicast address filter by passing all multicast addresses 1386 * through a crc generator, and then using bits 2 - 7 as an index 1387 * into the 64 bit logical address filter. The high order bits 1388 * selects the word, while the rest of the bits select the bit within 1389 * the word. 1390 */ 1391 1392 if (ifp->if_flags & IFF_PROMISC) { 1393 ifp->if_flags |= IFF_ALLMULTI; 1394 for (i = 0; i < 8; i++) 1395 af[i] = 0xff; 1396 return; 1397 } 1398 for (i = 0; i < 8; i++) 1399 af[i] = 0; 1400 ETHER_FIRST_MULTI(step, ec, enm); 1401 while (enm != NULL) { 1402 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1403 sizeof(enm->enm_addrlo)) != 0) { 1404 /* 1405 * We must listen to a range of multicast addresses. 1406 * For now, just accept all multicasts, rather than 1407 * trying to set only those filter bits needed to match 1408 * the range. (At this time, the only use of address 1409 * ranges is for IP multicast routing, for which the 1410 * range is big enough to require all bits set.) 1411 */ 1412 ifp->if_flags |= IFF_ALLMULTI; 1413 for (i = 0; i < 8; i++) 1414 af[i] = 0xff; 1415 break; 1416 } 1417 1418 crc = ether_crc32_be(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1419 1420 /* Just want the 6 most significant bits. */ 1421 crc = (crc >> 2) & 0x3f; 1422 1423 /* Turn on the corresponding bit in the filter. */ 1424 af[crc >> 3] |= 1 << (crc & 0x7); 1425 1426 ETHER_NEXT_MULTI(step, enm); 1427 } 1428 ifp->if_flags &= ~IFF_ALLMULTI; 1429 1430 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1431 for (i = 0; i < 8; ++i) 1432 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1433 SEEQ_BUFWIN, af[i]); 1434} 1435 1436static void 1437ea_mc_reset_8005(struct seeq8005_softc *sc) 1438{ 1439 struct ether_multi *enm; 1440 struct ether_multistep step; 1441 int naddr, maxaddrs; 1442 1443 naddr = 0; 1444 maxaddrs = 5; 1445 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1446 while (enm != NULL) { 1447 /* Have we got space? */ 1448 if (naddr >= maxaddrs || 1449 memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1450 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1451 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1452 return; 1453 } 1454 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1455 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1456 naddr++; 1457 ETHER_NEXT_MULTI(step, enm); 1458 } 1459 for (; naddr < maxaddrs; naddr++) 1460 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1461 SEEQ_WRITE16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1462 sc->sc_config1); 1463} 1464 1465/* 1466 * Device timeout routine. 1467 */ 1468 1469static void 1470ea_watchdog(struct ifnet *ifp) 1471{ 1472 struct seeq8005_softc *sc = ifp->if_softc; 1473 1474 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1475 sc->sc_dev.dv_xname, 1476 SEEQ_READ16(sc, sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1477 ifp->if_oerrors++; 1478 1479 /* Kick the interface */ 1480 1481 ea_init(ifp); 1482 1483 ifp->if_timer = 0; 1484} 1485 1486/* End of if_ea.c */ 1487