seeq8005.c revision 1.22
1/* $NetBSD: seeq8005.c,v 1.22 2001/04/06 00:02:49 bjh21 Exp $ */ 2 3/* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995-1998 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36/* 37 * seeq8005.c - SEEQ 8005 device driver 38 */ 39/* 40 * This driver currently supports the following chip: 41 * SEEQ 8005 Advanced Ethernet Data Link Controller 42 * SEEQ 80C04 Ethernet Data Link Controller 43 * SEEQ 80C04A AutoDUPLEX CMOS Ethernet Data Link Controller 44 */ 45/* 46 * More information on the 8004 and 8005 AEDLC controllers can be found in 47 * the SEEQ Technology Inc 1992 Data Comm Devices data book. 48 * 49 * This data book may no longer be available as these are rather old chips 50 * (1991 - 1993) 51 */ 52/* 53 * This driver is based on the arm32 ea(4) driver, hence the names of many 54 * of the functions. 55 */ 56/* 57 * Bugs/possible improvements: 58 * - Does not currently support DMA 59 * - Does not transmit multiple packets in one go 60 * - Does not support 8-bit busses 61 */ 62 63#include "opt_inet.h" 64#include "opt_ns.h" 65 66#include <sys/types.h> 67#include <sys/param.h> 68 69__RCSID("$NetBSD: seeq8005.c,v 1.22 2001/04/06 00:02:49 bjh21 Exp $"); 70 71#include <sys/systm.h> 72#include <sys/endian.h> 73#include <sys/errno.h> 74#include <sys/ioctl.h> 75#include <sys/mbuf.h> 76#include <sys/socket.h> 77#include <sys/syslog.h> 78#include <sys/device.h> 79 80#include <net/if.h> 81#include <net/if_dl.h> 82#include <net/if_types.h> 83#include <net/if_ether.h> 84#include <net/if_media.h> 85 86#ifdef INET 87#include <netinet/in.h> 88#include <netinet/in_systm.h> 89#include <netinet/in_var.h> 90#include <netinet/ip.h> 91#include <netinet/if_inarp.h> 92#endif 93 94#ifdef NS 95#include <netns/ns.h> 96#include <netns/ns_if.h> 97#endif 98 99#include "bpfilter.h" 100#if NBPFILTER > 0 101#include <net/bpf.h> 102#include <net/bpfdesc.h> 103#endif 104 105#include <machine/bus.h> 106#include <machine/intr.h> 107 108#include <dev/ic/seeq8005reg.h> 109#include <dev/ic/seeq8005var.h> 110 111/*#define SEEQ_DEBUG*/ 112 113/* for debugging convenience */ 114#ifdef SEEQ8005_DEBUG 115#define SEEQ_DEBUG_MISC 1 116#define SEEQ_DEBUG_TX 2 117#define SEEQ_DEBUG_RX 4 118#define SEEQ_DEBUG_PKT 8 119#define SEEQ_DEBUG_TXINT 16 120#define SEEQ_DEBUG_RXINT 32 121int seeq8005_debug = 0; 122#define DPRINTF(f, x) { if (seeq8005_debug & (f)) printf x; } 123#else 124#define DPRINTF(f, x) 125#endif 126 127#define SEEQ_TX_BUFFER_SIZE 0x800 /* (> MAX_ETHER_LEN) */ 128 129/* 130 * prototypes 131 */ 132 133static int ea_init(struct ifnet *); 134static int ea_ioctl(struct ifnet *, u_long, caddr_t); 135static void ea_start(struct ifnet *); 136static void ea_watchdog(struct ifnet *); 137static void ea_chipreset(struct seeq8005_softc *); 138static void ea_ramtest(struct seeq8005_softc *); 139static int ea_stoptx(struct seeq8005_softc *); 140static int ea_stoprx(struct seeq8005_softc *); 141static void ea_stop(struct ifnet *, int); 142static void ea_await_fifo_empty(struct seeq8005_softc *); 143static void ea_await_fifo_full(struct seeq8005_softc *); 144static void ea_writebuf(struct seeq8005_softc *, u_char *, int, size_t); 145static void ea_readbuf(struct seeq8005_softc *, u_char *, int, size_t); 146static void ea_select_buffer(struct seeq8005_softc *, int); 147static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 148static void ea_read(struct seeq8005_softc *, int, int); 149static struct mbuf *ea_get(struct seeq8005_softc *, int, int, struct ifnet *); 150static void ea_txint(struct seeq8005_softc *); 151static void ea_rxint(struct seeq8005_softc *); 152static void eatxpacket(struct seeq8005_softc *); 153static int ea_writembuf(struct seeq8005_softc *, struct mbuf *, int); 154static void ea_mc_reset(struct seeq8005_softc *); 155static void ea_mc_reset_8004(struct seeq8005_softc *); 156static void ea_mc_reset_8005(struct seeq8005_softc *); 157static int ea_mediachange(struct ifnet *); 158static void ea_mediastatus(struct ifnet *, struct ifmediareq *); 159 160 161/* 162 * Attach chip. 163 */ 164 165void 166seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr, int *media, 167 int nmedia, int defmedia) 168{ 169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 170 u_int id; 171 172 KASSERT(myaddr != NULL); 173 printf(" address %s", ether_sprintf(myaddr)); 174 175 /* Stop the board. */ 176 177 ea_chipreset(sc); 178 179 /* Get the product ID */ 180 181 ea_select_buffer(sc, SEEQ_BUFCODE_PRODUCTID); 182 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN); 183 184 switch (id & SEEQ_PRODUCTID_MASK) { 185 case SEEQ_PRODUCTID_8004: 186 sc->sc_variant = SEEQ_8004; 187 switch (id & SEEQ_PRODUCTID_REV_MASK) { 188 case SEEQ_PRODUCTID_REV_80C04: 189 printf(", SEEQ 80C04\n"); 190 break; 191 case SEEQ_PRODUCTID_REV_80C04A: 192 printf(", SEEQ 80C04A\n"); 193 break; 194 default: 195 /* Unknown SEEQ 8004 variants */ 196 printf(", SEEQ 8004 rev %x\n", 197 id & SEEQ_PRODUCTID_REV_MASK); 198 break; 199 } 200 break; 201 default: /* XXX */ 202 sc->sc_variant = SEEQ_8005; 203 printf(", SEEQ 8005\n"); 204 break; 205 } 206 207 /* Both the 8004 and 8005 are designed for 64K Buffer memory */ 208 sc->sc_buffersize = SEEQ_MAX_BUFFER_SIZE; 209 210 /* 211 * Set up tx and rx buffers. 212 * 213 * We use approximately a quarter of the packet memory for TX 214 * buffers and the rest for RX buffers 215 */ 216 /* sc->sc_tx_bufs = sc->sc_buffersize / SEEQ_TX_BUFFER_SIZE / 4; */ 217 sc->sc_tx_bufs = 1; 218 sc->sc_tx_bufsize = sc->sc_tx_bufs * SEEQ_TX_BUFFER_SIZE; 219 sc->sc_rx_bufsize = sc->sc_buffersize - sc->sc_tx_bufsize; 220 sc->sc_enabled = 0; 221 222 /* Test the RAM */ 223 ea_ramtest(sc); 224 225 printf("%s: %dKB packet memory, txbuf=%dKB (%d buffers), rxbuf=%dKB", 226 sc->sc_dev.dv_xname, sc->sc_buffersize >> 10, 227 sc->sc_tx_bufsize >> 10, sc->sc_tx_bufs, sc->sc_rx_bufsize >> 10); 228 229 /* Initialise ifnet structure. */ 230 231 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 232 ifp->if_softc = sc; 233 ifp->if_start = ea_start; 234 ifp->if_ioctl = ea_ioctl; 235 ifp->if_init = ea_init; 236 ifp->if_stop = ea_stop; 237 ifp->if_watchdog = ea_watchdog; 238 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 239 if (sc->sc_variant == SEEQ_8004) 240 ifp->if_flags |= IFF_SIMPLEX; 241 IFQ_SET_READY(&ifp->if_snd); 242 243 /* Initialize media goo. */ 244 ifmedia_init(&sc->sc_media, 0, ea_mediachange, ea_mediastatus); 245 if (media != NULL) { 246 int i; 247 248 for (i = 0; i < nmedia; i++) 249 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 250 ifmedia_set(&sc->sc_media, defmedia); 251 } else { 252 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 253 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 254 } 255 256 /* Now we can attach the interface. */ 257 258 if_attach(ifp); 259 ether_ifattach(ifp, myaddr); 260 261 printf("\n"); 262} 263 264/* 265 * Media change callback. 266 */ 267static int 268ea_mediachange(struct ifnet *ifp) 269{ 270 struct seeq8005_softc *sc = ifp->if_softc; 271 272 if (sc->sc_mediachange) 273 return ((*sc->sc_mediachange)(sc)); 274 return (EINVAL); 275} 276 277/* 278 * Media status callback. 279 */ 280static void 281ea_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 282{ 283 struct seeq8005_softc *sc = ifp->if_softc; 284 285 if (sc->sc_enabled == 0) { 286 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 287 ifmr->ifm_status = 0; 288 return; 289 } 290 291 if (sc->sc_mediastatus) 292 (*sc->sc_mediastatus)(sc, ifmr); 293} 294 295/* 296 * Test the RAM on the ethernet card. 297 */ 298 299void 300ea_ramtest(struct seeq8005_softc *sc) 301{ 302 bus_space_tag_t iot = sc->sc_iot; 303 bus_space_handle_t ioh = sc->sc_ioh; 304 int loop; 305 u_int sum = 0; 306 307 /* 308 * Test the buffer memory on the board. 309 * Write simple pattens to it and read them back. 310 */ 311 312 /* Set up the whole buffer RAM for writing */ 313 314 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 315 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (SEEQ_MAX_BUFFER_SIZE >> 8) - 1); 316 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 317 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, SEEQ_MAX_BUFFER_SIZE - 2); 318 319#define SEEQ_RAMTEST_LOOP(value) \ 320do { \ 321 /* Set the write start address and write a pattern */ \ 322 ea_writebuf(sc, NULL, 0x0000, 0); \ 323 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 324 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (value)); \ 325 \ 326 /* Set the read start address and verify the pattern */ \ 327 ea_readbuf(sc, NULL, 0x0000, 0); \ 328 for (loop = 0; loop < SEEQ_MAX_BUFFER_SIZE; loop += 2) \ 329 if (bus_space_read_2(iot, ioh, SEEQ_BUFWIN) != (value)) \ 330 ++sum; \ 331} while (/*CONSTCOND*/0) 332 333 SEEQ_RAMTEST_LOOP(loop); 334 SEEQ_RAMTEST_LOOP(loop ^ (SEEQ_MAX_BUFFER_SIZE - 1)); 335 SEEQ_RAMTEST_LOOP(0xaa55); 336 SEEQ_RAMTEST_LOOP(0x55aa); 337 338 /* Report */ 339 340 if (sum > 0) 341 printf("%s: buffer RAM failed self test, %d faults\n", 342 sc->sc_dev.dv_xname, sum); 343} 344 345 346/* 347 * Stop the tx interface. 348 * 349 * Returns 0 if the tx was already stopped or 1 if it was active 350 */ 351 352static int 353ea_stoptx(struct seeq8005_softc *sc) 354{ 355 bus_space_tag_t iot = sc->sc_iot; 356 bus_space_handle_t ioh = sc->sc_ioh; 357 int timeout; 358 int status; 359 360 DPRINTF(SEEQ_DEBUG_TX, ("ea_stoptx()\n")); 361 362 sc->sc_enabled = 0; 363 364 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 365 if (!(status & SEEQ_STATUS_TX_ON)) 366 return 0; 367 368 /* Stop any tx and wait for confirmation */ 369 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 370 sc->sc_command | SEEQ_CMD_TX_OFF); 371 372 timeout = 20000; 373 do { 374 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 375 delay(1); 376 } while ((status & SEEQ_STATUS_TX_ON) && --timeout > 0); 377 if (timeout == 0) 378 log(LOG_ERR, "%s: timeout waiting for tx termination\n", 379 sc->sc_dev.dv_xname); 380 381 /* Clear any pending tx interrupt */ 382 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 383 sc->sc_command | SEEQ_CMD_TX_INTACK); 384 return 1; 385} 386 387 388/* 389 * Stop the rx interface. 390 * 391 * Returns 0 if the tx was already stopped or 1 if it was active 392 */ 393 394static int 395ea_stoprx(struct seeq8005_softc *sc) 396{ 397 bus_space_tag_t iot = sc->sc_iot; 398 bus_space_handle_t ioh = sc->sc_ioh; 399 int timeout; 400 int status; 401 402 DPRINTF(SEEQ_DEBUG_RX, ("ea_stoprx()\n")); 403 404 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 405 if (!(status & SEEQ_STATUS_RX_ON)) 406 return 0; 407 408 /* Stop any rx and wait for confirmation */ 409 410 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 411 sc->sc_command | SEEQ_CMD_RX_OFF); 412 413 timeout = 20000; 414 do { 415 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 416 } while ((status & SEEQ_STATUS_RX_ON) && --timeout > 0); 417 if (timeout == 0) 418 log(LOG_ERR, "%s: timeout waiting for rx termination\n", 419 sc->sc_dev.dv_xname); 420 421 /* Clear any pending rx interrupt */ 422 423 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 424 sc->sc_command | SEEQ_CMD_RX_INTACK); 425 return 1; 426} 427 428 429/* 430 * Stop interface. 431 * Stop all IO and shut the interface down 432 */ 433 434static void 435ea_stop(struct ifnet *ifp, int disable) 436{ 437 struct seeq8005_softc *sc = ifp->if_softc; 438 bus_space_tag_t iot = sc->sc_iot; 439 bus_space_handle_t ioh = sc->sc_ioh; 440 441 DPRINTF(SEEQ_DEBUG_MISC, ("ea_stop()\n")); 442 443 /* Stop all IO */ 444 ea_stoptx(sc); 445 ea_stoprx(sc); 446 447 /* Disable rx and tx interrupts */ 448 sc->sc_command &= (SEEQ_CMD_RX_INTEN | SEEQ_CMD_TX_INTEN); 449 450 /* Clear any pending interrupts */ 451 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 452 sc->sc_command | SEEQ_CMD_RX_INTACK | 453 SEEQ_CMD_TX_INTACK | SEEQ_CMD_DMA_INTACK | 454 SEEQ_CMD_BW_INTACK); 455 456 if (sc->sc_variant == SEEQ_8004) { 457 /* Put the chip to sleep */ 458 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 459 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 460 sc->sc_config3 | SEEQ_CFG3_SLEEP); 461 } 462 463 /* Cancel any watchdog timer */ 464 sc->sc_ethercom.ec_if.if_timer = 0; 465} 466 467 468/* 469 * Reset the chip 470 * Following this the software registers are reset 471 */ 472 473static void 474ea_chipreset(struct seeq8005_softc *sc) 475{ 476 bus_space_tag_t iot = sc->sc_iot; 477 bus_space_handle_t ioh = sc->sc_ioh; 478 479 DPRINTF(SEEQ_DEBUG_MISC, ("ea_chipreset()\n")); 480 481 /* Reset the controller. Min of 4us delay here */ 482 483 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, SEEQ_CFG2_RESET); 484 delay(4); 485 486 sc->sc_command = 0; 487 sc->sc_config1 = 0; 488 sc->sc_config2 = 0; 489 sc->sc_config3 = 0; 490} 491 492 493/* 494 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 495 * switching the FIFO from write to read. We also use it when changing 496 * the address for writes. 497 */ 498static void 499ea_await_fifo_empty(struct seeq8005_softc *sc) 500{ 501 bus_space_tag_t iot = sc->sc_iot; 502 bus_space_handle_t ioh = sc->sc_ioh; 503 int timeout; 504 505 timeout = 20000; 506 if ((bus_space_read_2(iot, ioh, SEEQ_STATUS) & 507 SEEQ_STATUS_FIFO_DIR) != 0) 508 return; /* FIFO is reading anyway. */ 509 while (--timeout > 0) 510 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 511 SEEQ_STATUS_FIFO_EMPTY) 512 return; 513 log(LOG_ERR, "%s: DMA FIFO failed to empty\n", sc->sc_dev.dv_xname); 514} 515 516/* 517 * Wait for the DMA FIFO to fill before reading from it. 518 */ 519static void 520ea_await_fifo_full(struct seeq8005_softc *sc) 521{ 522 bus_space_tag_t iot = sc->sc_iot; 523 bus_space_handle_t ioh = sc->sc_ioh; 524 int timeout; 525 526 timeout = 20000; 527 while (--timeout > 0) 528 if (bus_space_read_2(iot, ioh, SEEQ_STATUS) & 529 SEEQ_STATUS_FIFO_FULL) 530 return; 531 log(LOG_ERR, "%s: DMA FIFO failed to fill\n", sc->sc_dev.dv_xname); 532} 533 534/* 535 * write to the buffer memory on the interface 536 * 537 * The buffer address is set to ADDR. 538 * If len != 0 then data is copied from the address starting at buf 539 * to the interface buffer. 540 * BUF must be usable as a u_int16_t *. 541 * If LEN is odd, it must be safe to overwrite one extra byte. 542 */ 543 544static void 545ea_writebuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 546{ 547 bus_space_tag_t iot = sc->sc_iot; 548 bus_space_handle_t ioh = sc->sc_ioh; 549 550 DPRINTF(SEEQ_DEBUG_MISC, ("writebuf: st=%04x\n", 551 bus_space_read_2(iot, ioh, SEEQ_STATUS))); 552 553#ifdef DIAGNOSTIC 554 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 555 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 556 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 557 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 558#endif 559 560 /* Assume that copying too much is safe. */ 561 if (len % 2 != 0) 562 len++; 563 564 if (addr != -1) { 565 ea_await_fifo_empty(sc); 566 567 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 568 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 569 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 570 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr); 571 } 572 573 if (len > 0) 574 bus_space_write_multi_2(iot, ioh, SEEQ_BUFWIN, 575 (u_int16_t *)buf, len / 2); 576 /* Leave FIFO to empty in the background */ 577} 578 579 580/* 581 * read from the buffer memory on the interface 582 * 583 * The buffer address is set to ADDR. 584 * If len != 0 then data is copied from the interface buffer to the 585 * address starting at buf. 586 * BUF must be usable as a u_int16_t *. 587 * If LEN is odd, it must be safe to overwrite one extra byte. 588 */ 589 590static void 591ea_readbuf(struct seeq8005_softc *sc, u_char *buf, int addr, size_t len) 592{ 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 int runup; 596 597 DPRINTF(SEEQ_DEBUG_MISC, ("readbuf: st=%04x addr=%04x len=%d\n", 598 bus_space_read_2(iot, ioh, SEEQ_STATUS), addr, len)); 599 600#ifdef DIAGNOSTIC 601 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 602 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 603 if (__predict_false(addr >= SEEQ_MAX_BUFFER_SIZE)) 604 panic("%s: readbuf out of range", sc->sc_dev.dv_xname); 605#endif 606 607 /* Assume that copying too much is safe. */ 608 if (len % 2 != 0) 609 len++; 610 611 if (addr != -1) { 612 /* 613 * SEEQ 80C04 bug: 614 * Starting reading from certain addresses seems to cause 615 * us to get bogus results, so we avoid them. 616 */ 617 runup = 0; 618 if (sc->sc_variant == SEEQ_8004 && 619 ((addr & 0x00ff) == 0x00ea || 620 (addr & 0x00ff) == 0x00ee || 621 (addr & 0x00ff) == 0x00f0)) 622 runup = (addr & 0x00ff) - 0x00e8; 623 624 ea_await_fifo_empty(sc); 625 626 ea_select_buffer(sc, SEEQ_BUFCODE_LOCAL_MEM); 627 628 /* 629 * 80C04 bug workaround. I found this in the old arm32 "eb" 630 * driver. I've no idea what it does, but it seems to stop 631 * the chip mangling data so often. 632 */ 633 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 634 sc->sc_command | SEEQ_CMD_FIFO_WRITE); 635 ea_await_fifo_empty(sc); 636 637 bus_space_write_2(iot, ioh, SEEQ_DMA_ADDR, addr - runup); 638 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 639 sc->sc_command | SEEQ_CMD_FIFO_READ); 640 641 ea_await_fifo_full(sc); 642 while (runup > 0) { 643 (void)bus_space_read_2(iot, ioh, SEEQ_BUFWIN); 644 runup -= 2; 645 } 646 } 647 648 if (len > 0) 649 bus_space_read_multi_2(iot, ioh, SEEQ_BUFWIN, 650 (u_int16_t *)buf, len / 2); 651} 652 653static void 654ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 655{ 656 657 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 658 sc->sc_config1 | bufcode); 659} 660 661/* Must be called at splnet */ 662static void 663ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 664{ 665 int i; 666 667 ea_select_buffer(sc, SEEQ_BUFCODE_STATION_ADDR0 + which); 668 for (i = 0; i < ETHER_ADDR_LEN; ++i) 669 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 670 ea[i]); 671} 672 673/* 674 * Initialize interface. 675 * 676 * This should leave the interface in a state for packet reception and 677 * transmission. 678 */ 679 680static int 681ea_init(struct ifnet *ifp) 682{ 683 struct seeq8005_softc *sc = ifp->if_softc; 684 bus_space_tag_t iot = sc->sc_iot; 685 bus_space_handle_t ioh = sc->sc_ioh; 686 int s; 687 688 DPRINTF(SEEQ_DEBUG_MISC, ("ea_init()\n")); 689 690 s = splnet(); 691 692 /* First, reset the board. */ 693 694 ea_chipreset(sc); 695 696 /* Set up defaults for the registers */ 697 698 sc->sc_command = 0; 699 sc->sc_config1 = 0; 700#if BYTE_ORDER == BIG_ENDIAN 701 sc->sc_config2 = SEEQ_CFG2_BYTESWAP; 702#else 703 sc->sc_config2 = 0; 704#endif 705 sc->sc_config3 = 0; 706 707 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 708 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 709 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 710 if (sc->sc_variant == SEEQ_8004) { 711 ea_select_buffer(sc, SEEQ_BUFCODE_CONFIG3); 712 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, sc->sc_config3); 713 } 714 715 /* Write the station address - the receiver must be off */ 716 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 717 718 /* Split board memory into Rx and Tx. */ 719 ea_select_buffer(sc, SEEQ_BUFCODE_TX_EAP); 720 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, (sc->sc_tx_bufsize>> 8) - 1); 721 722 if (sc->sc_variant == SEEQ_8004) 723 sc->sc_config2 |= SEEQ_CFG2_RX_TX_DISABLE; 724 725 /* Configure rx. */ 726 ea_mc_reset(sc); 727 if (ifp->if_flags & IFF_PROMISC) 728 sc->sc_config1 = SEEQ_CFG1_PROMISCUOUS; 729 else if ((ifp->if_flags & IFF_ALLMULTI) || sc->sc_variant == SEEQ_8004) 730 sc->sc_config1 = SEEQ_CFG1_MULTICAST; 731 else 732 sc->sc_config1 = SEEQ_CFG1_BROADCAST; 733 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR0; 734 bus_space_write_2(iot, ioh, SEEQ_CONFIG1, sc->sc_config1); 735 736 /* Setup the Rx pointers */ 737 sc->sc_rx_ptr = sc->sc_tx_bufsize; 738 739 bus_space_write_2(iot, ioh, SEEQ_RX_PTR, sc->sc_rx_ptr); 740 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 741 742 743 /* Place a NULL header at the beginning of the receive area */ 744 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 745 746 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 747 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 748 749 750 /* Configure TX. */ 751 DPRINTF(SEEQ_DEBUG_MISC, ("Configuring tx...\n")); 752 753 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 754 755 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 756 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 757 758 /* Reset tx buffer pointers */ 759 sc->sc_tx_cur = 0; 760 sc->sc_tx_used = 0; 761 sc->sc_tx_next = 0; 762 763 /* Place a NULL header at the beginning of the transmit area */ 764 ea_writebuf(sc, NULL, 0x0000, 0); 765 766 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 767 bus_space_write_2(iot, ioh, SEEQ_BUFWIN, 0x0000); 768 769 sc->sc_command |= SEEQ_CMD_TX_INTEN; 770 bus_space_write_2(iot, ioh, SEEQ_COMMAND, sc->sc_command); 771 772 /* Turn on Rx */ 773 sc->sc_command |= SEEQ_CMD_RX_INTEN; 774 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 775 sc->sc_command | SEEQ_CMD_RX_ON); 776 777 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 778 779 780 /* Set flags appropriately. */ 781 ifp->if_flags |= IFF_RUNNING; 782 ifp->if_flags &= ~IFF_OACTIVE; 783 sc->sc_enabled = 1; 784 785 /* And start output. */ 786 ea_start(ifp); 787 788 splx(s); 789 return 0; 790} 791 792/* 793 * Start output on interface. Get datagrams from the queue and output them, 794 * giving the receiver a chance between datagrams. Call only from splnet or 795 * interrupt level! 796 */ 797 798static void 799ea_start(struct ifnet *ifp) 800{ 801 struct seeq8005_softc *sc = ifp->if_softc; 802 int s; 803 804 s = splnet(); 805 DPRINTF(SEEQ_DEBUG_TX, ("ea_start()...\n")); 806 807 /* 808 * Don't do anything if output is active. seeq8005intr() will call 809 * us (actually eatxpacket()) back when the card's ready for more 810 * frames. 811 */ 812 if (ifp->if_flags & IFF_OACTIVE) 813 return; 814 815 /* Mark interface as output active */ 816 817 ifp->if_flags |= IFF_OACTIVE; 818 819 /* tx packets */ 820 821 eatxpacket(sc); 822 splx(s); 823} 824 825 826/* 827 * Transfer a packet to the interface buffer and start transmission 828 * 829 * Called at splnet() 830 */ 831 832void 833eatxpacket(struct seeq8005_softc *sc) 834{ 835 bus_space_tag_t iot = sc->sc_iot; 836 bus_space_handle_t ioh = sc->sc_ioh; 837 struct mbuf *m0; 838 struct ifnet *ifp; 839 840 ifp = &sc->sc_ethercom.ec_if; 841 842 /* Dequeue the next packet. */ 843 IFQ_DEQUEUE(&ifp->if_snd, m0); 844 845 /* If there's nothing to send, return. */ 846 if (!m0) { 847 ifp->if_flags &= ~IFF_OACTIVE; 848 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 849 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 850 DPRINTF(SEEQ_DEBUG_TX, ("tx finished\n")); 851 return; 852 } 853 854#if NBPFILTER > 0 855 /* Give the packet to the bpf, if any. */ 856 if (ifp->if_bpf) 857 bpf_mtap(ifp->if_bpf, m0); 858#endif 859 860 DPRINTF(SEEQ_DEBUG_TX, ("Tx new packet\n")); 861 862 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 863 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 864 865 ea_writembuf(sc, m0, 0x0000); 866 m_freem(m0); 867 868 bus_space_write_2(iot, ioh, SEEQ_TX_PTR, 0x0000); 869 870 /* Now transmit the datagram. */ 871 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 872 sc->sc_command | SEEQ_CMD_TX_ON); 873 874 /* Make sure we notice if the chip goes silent on us. */ 875 ifp->if_timer = 5; 876 877 DPRINTF(SEEQ_DEBUG_TX, 878 ("st=%04x\n", bus_space_read_2(iot, ioh, SEEQ_STATUS))); 879 DPRINTF(SEEQ_DEBUG_TX, ("tx: queued\n")); 880} 881 882/* 883 * Copy a packet from an mbuf to the transmit buffer on the card. 884 * 885 * Puts a valid Tx header at the start of the packet, and a null header at 886 * the end. 887 */ 888static int 889ea_writembuf(struct seeq8005_softc *sc, struct mbuf *m0, int bufstart) 890{ 891 struct mbuf *m; 892 int len, nextpacket; 893 u_int8_t hdr[4]; 894 895 /* 896 * Copy the datagram to the packet buffer. 897 */ 898 len = 0; 899 for (m = m0; m; m = m->m_next) { 900 if (m->m_len == 0) 901 continue; 902 ea_writebuf(sc, mtod(m, caddr_t), bufstart + 4 + len, 903 m->m_len); 904 len += m->m_len; 905 } 906 907 len = max(len, ETHER_MIN_LEN); 908 909 /* Follow it with a NULL packet header */ 910 memset(hdr, 0, 4); 911 ea_writebuf(sc, hdr, bufstart + 4 + len, 4); 912 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 913 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_BUFWIN, 0x0000); 914 915 /* Ok we now have a packet len bytes long in our packet buffer */ 916 DPRINTF(SEEQ_DEBUG_TX, ("ea_writembuf: length=%d\n", len)); 917 918 /* Write the packet header */ 919 nextpacket = len + 4; 920 hdr[0] = (nextpacket >> 8) & 0xff; 921 hdr[1] = nextpacket & 0xff; 922 hdr[2] = SEEQ_PKTCMD_TX | SEEQ_PKTCMD_DATA_FOLLOWS | 923 SEEQ_TXCMD_XMIT_SUCCESS_INT | SEEQ_TXCMD_COLLISION_INT; 924 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 925 ea_writebuf(sc, hdr, 0x0000, 4); 926 927 return len; 928} 929 930/* 931 * Ethernet controller interrupt. 932 */ 933 934int 935seeq8005intr(void *arg) 936{ 937 struct seeq8005_softc *sc = arg; 938 bus_space_tag_t iot = sc->sc_iot; 939 bus_space_handle_t ioh = sc->sc_ioh; 940 int status, handled; 941 942 handled = 0; 943 944 /* Get the controller status */ 945 status = bus_space_read_2(iot, ioh, SEEQ_STATUS); 946 947 /* Tx interrupt ? */ 948 if (status & SEEQ_STATUS_TX_INT) { 949 handled = 1; 950 951 /* Acknowledge the interrupt */ 952 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 953 sc->sc_command | SEEQ_CMD_TX_INTACK); 954 955 ea_txint(sc); 956 } 957 958 959 /* Rx interrupt ? */ 960 if (status & SEEQ_STATUS_RX_INT) { 961 handled = 1; 962 963 /* Acknowledge the interrupt */ 964 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 965 sc->sc_command | SEEQ_CMD_RX_INTACK); 966 967 /* Processes the received packets */ 968 ea_rxint(sc); 969 } 970 971 return handled; 972} 973 974static void 975ea_txint(struct seeq8005_softc *sc) 976{ 977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 978 bus_space_tag_t iot = sc->sc_iot; 979 bus_space_handle_t ioh = sc->sc_ioh; 980 u_int8_t txhdr[4]; 981 u_int txstatus; 982 983 ea_readbuf(sc, txhdr, 0x0000, 4); 984 985 DPRINTF(SEEQ_DEBUG_TX, ("txstatus=%02x %02x %02x %02x\n", 986 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 987 txstatus = txhdr[3]; 988 989 /* 990 * If SEEQ_TXSTAT_COLLISION is set then we received at least 991 * one collision. On the 8004 we can find out exactly how many 992 * collisions occurred. 993 * 994 * The SEEQ_PKTSTAT_DONE will be set if the transmission has 995 * completed. 996 * 997 * If SEEQ_TXSTAT_COLLISION16 is set then 16 collisions 998 * occurred and the packet transmission was aborted. 999 * This situation is untested as present. 1000 * 1001 * The SEEQ_TXSTAT_BABBLE should never be set and is untested 1002 * as we should never xmit oversized packets. 1003 */ 1004 if (txstatus & SEEQ_TXSTAT_COLLISION) { 1005 switch (sc->sc_variant) { 1006 case SEEQ_8004: { 1007 int colls; 1008 1009 /* 1010 * The 8004 contains a 4 bit collision count 1011 * in the status register. 1012 */ 1013 1014 /* This appears to be broken on 80C04.AE */ 1015/* ifp->if_collisions += 1016 (txstatus >> SEEQ_TXSTAT_COLLISIONS_SHIFT) 1017 & SEEQ_TXSTAT_COLLISION_MASK;*/ 1018 1019 /* Use the TX Collision register */ 1020 ea_select_buffer(sc, SEEQ_BUFCODE_TX_COLLS); 1021 colls = bus_space_read_1(iot, ioh, SEEQ_BUFWIN); 1022 ifp->if_collisions += colls; 1023 break; 1024 } 1025 case SEEQ_8005: 1026 /* We known there was at least 1 collision */ 1027 ifp->if_collisions++; 1028 break; 1029 } 1030 } else if (txstatus & SEEQ_TXSTAT_COLLISION16) { 1031 printf("seeq_intr: col16 %x\n", txstatus); 1032 ifp->if_collisions += 16; 1033 ifp->if_oerrors++; 1034 } else if (txstatus & SEEQ_TXSTAT_BABBLE) { 1035 ifp->if_oerrors++; 1036 } 1037 1038 /* Have we completed transmission on the packet ? */ 1039 if (txstatus & SEEQ_PKTSTAT_DONE) { 1040 /* Clear watchdog timer. */ 1041 ifp->if_timer = 0; 1042 ifp->if_flags &= ~IFF_OACTIVE; 1043 1044 /* Update stats */ 1045 ifp->if_opackets++; 1046 1047 /* Tx next packet */ 1048 1049 eatxpacket(sc); 1050 } 1051} 1052 1053void 1054ea_rxint(struct seeq8005_softc *sc) 1055{ 1056 bus_space_tag_t iot = sc->sc_iot; 1057 bus_space_handle_t ioh = sc->sc_ioh; 1058 u_int addr; 1059 int len; 1060 int ctrl; 1061 int ptr; 1062 int pack; 1063 int status; 1064 u_int8_t rxhdr[4]; 1065 struct ifnet *ifp; 1066 1067 ifp = &sc->sc_ethercom.ec_if; 1068 1069 1070 /* We start from the last rx pointer position */ 1071 addr = sc->sc_rx_ptr; 1072 sc->sc_config2 &= ~SEEQ_CFG2_OUTPUT; 1073 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1074 1075 do { 1076 /* Read rx header */ 1077 ea_readbuf(sc, rxhdr, addr, 4); 1078 1079 /* Split the packet header */ 1080 ptr = (rxhdr[0] << 8) | rxhdr[1]; 1081 ctrl = rxhdr[2]; 1082 status = rxhdr[3]; 1083 1084 DPRINTF(SEEQ_DEBUG_RX, 1085 ("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 1086 addr, ptr, ctrl, status)); 1087 1088 /* Zero packet ptr ? then must be null header so exit */ 1089 if (ptr == 0) break; 1090 1091 /* Sanity-check the next-packet pointer and flags. */ 1092 if (__predict_false(ptr < sc->sc_tx_bufsize || 1093 (ctrl & SEEQ_PKTCMD_TX))) { 1094 ++ifp->if_ierrors; 1095 log(LOG_ERR, 1096 "%s: Rx chain corrupt at %04x (ptr = %04x)\n", 1097 sc->sc_dev.dv_xname, addr, ptr); 1098 ea_init(ifp); 1099 return; 1100 } 1101 1102 /* Get packet length */ 1103 len = (ptr - addr) - 4; 1104 1105 if (len < 0) 1106 len += sc->sc_rx_bufsize; 1107 DPRINTF(SEEQ_DEBUG_RX, ("len=%04x\n", len)); 1108 1109 /* Has the packet rx completed ? if not then exit */ 1110 if ((status & SEEQ_PKTSTAT_DONE) == 0) 1111 break; 1112 1113 /* 1114 * Did we have any errors? then note error and go to 1115 * next packet 1116 */ 1117 if (__predict_false(status & SEEQ_RXSTAT_ERROR_MASK)) { 1118 ++ifp->if_ierrors; 1119 /* XXX oversize packets may be OK */ 1120 log(LOG_WARNING, 1121 "%s: rx packet error at %04x (err=%02x)\n", 1122 sc->sc_dev.dv_xname, addr, status & 0x0f); 1123 /* XXX shouldn't need to reset if it's genuine. */ 1124 ea_init(ifp); 1125 return; 1126 } 1127 /* 1128 * Is the packet too big ? - this will probably be trapped 1129 * above as a receive error. If it's not, this is indicative 1130 * of buffer corruption. 1131 */ 1132 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1133 ++ifp->if_ierrors; 1134 log(LOG_ERR, 1135 "%s: rx packet size error at %04x (len=%d)\n", 1136 sc->sc_dev.dv_xname, addr, len); 1137 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1138 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, 1139 sc->sc_config2); 1140 ea_init(ifp); 1141 return; 1142 } 1143 1144 ifp->if_ipackets++; 1145 /* Pass data up to upper levels. */ 1146 ea_read(sc, addr + 4, len); 1147 1148 addr = ptr; 1149 ++pack; 1150 } while (len != 0); 1151 1152 sc->sc_config2 |= SEEQ_CFG2_OUTPUT; 1153 bus_space_write_2(iot, ioh, SEEQ_CONFIG2, sc->sc_config2); 1154 1155 DPRINTF(SEEQ_DEBUG_RX, ("new rx ptr=%04x\n", addr)); 1156 1157 /* Store new rx pointer */ 1158 sc->sc_rx_ptr = addr; 1159 bus_space_write_2(iot, ioh, SEEQ_RX_END, sc->sc_rx_ptr >> 8); 1160 1161 /* Make sure the receiver is on */ 1162 bus_space_write_2(iot, ioh, SEEQ_COMMAND, 1163 sc->sc_command | SEEQ_CMD_RX_ON); 1164} 1165 1166 1167/* 1168 * Pass a packet up to the higher levels. 1169 */ 1170 1171static void 1172ea_read(struct seeq8005_softc *sc, int addr, int len) 1173{ 1174 struct mbuf *m; 1175 struct ifnet *ifp; 1176 1177 ifp = &sc->sc_ethercom.ec_if; 1178 1179 /* Pull packet off interface. */ 1180 m = ea_get(sc, addr, len, ifp); 1181 if (m == 0) 1182 return; 1183 1184#if NBPFILTER > 0 1185 /* 1186 * Check if there's a BPF listener on this interface. 1187 * If so, hand off the raw packet to bpf. 1188 */ 1189 if (ifp->if_bpf) 1190 bpf_mtap(ifp->if_bpf, m); 1191#endif 1192 1193 (*ifp->if_input)(ifp, m); 1194} 1195 1196/* 1197 * Pull read data off a interface. Len is length of data, with local net 1198 * header stripped. We copy the data into mbufs. When full cluster sized 1199 * units are present we copy into clusters. 1200 */ 1201 1202struct mbuf * 1203ea_get(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1204{ 1205 struct mbuf *top, **mp, *m; 1206 int len; 1207 u_int cp, epkt; 1208 1209 cp = addr; 1210 epkt = cp + totlen; 1211 1212 MGETHDR(m, M_DONTWAIT, MT_DATA); 1213 if (m == 0) 1214 return 0; 1215 m->m_pkthdr.rcvif = ifp; 1216 m->m_pkthdr.len = totlen; 1217 m->m_len = MHLEN; 1218 top = 0; 1219 mp = ⊤ 1220 1221 while (totlen > 0) { 1222 if (top) { 1223 MGET(m, M_DONTWAIT, MT_DATA); 1224 if (m == 0) { 1225 m_freem(top); 1226 return 0; 1227 } 1228 m->m_len = MLEN; 1229 } 1230 len = min(totlen, epkt - cp); 1231 if (len >= MINCLSIZE) { 1232 MCLGET(m, M_DONTWAIT); 1233 if (m->m_flags & M_EXT) 1234 m->m_len = len = min(len, MCLBYTES); 1235 else 1236 len = m->m_len; 1237 } else { 1238 /* 1239 * Place initial small packet/header at end of mbuf. 1240 */ 1241 if (len < m->m_len) { 1242 if (top == 0 && len + max_linkhdr <= m->m_len) 1243 m->m_data += max_linkhdr; 1244 m->m_len = len; 1245 } else 1246 len = m->m_len; 1247 } 1248 if (top == 0) { 1249 /* Make sure the payload is aligned */ 1250 caddr_t newdata = (caddr_t) 1251 ALIGN(m->m_data + sizeof(struct ether_header)) - 1252 sizeof(struct ether_header); 1253 len -= newdata - m->m_data; 1254 m->m_len = len; 1255 m->m_data = newdata; 1256 } 1257 ea_readbuf(sc, mtod(m, u_char *), 1258 cp < SEEQ_MAX_BUFFER_SIZE ? cp : cp - sc->sc_rx_bufsize, 1259 len); 1260 cp += len; 1261 *mp = m; 1262 mp = &m->m_next; 1263 totlen -= len; 1264 if (cp == epkt) 1265 cp = addr; 1266 } 1267 1268 return top; 1269} 1270 1271/* 1272 * Process an ioctl request. Mostly boilerplate. 1273 */ 1274static int 1275ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1276{ 1277 struct seeq8005_softc *sc = ifp->if_softc; 1278 int s, error = 0; 1279 1280 s = splnet(); 1281 switch (cmd) { 1282 1283 default: 1284 error = ether_ioctl(ifp, cmd, data); 1285 if (error == ENETRESET) { 1286 /* 1287 * Multicast list has changed; set the hardware filter 1288 * accordingly. 1289 */ 1290 ea_mc_reset(sc); 1291 error = 0; 1292 } 1293 break; 1294 } 1295 1296 splx(s); 1297 return error; 1298} 1299 1300/* Must be called at splnet() */ 1301 1302static void 1303ea_mc_reset(struct seeq8005_softc *sc) 1304{ 1305 1306 switch (sc->sc_variant) { 1307 case SEEQ_8004: 1308 ea_mc_reset_8004(sc); 1309 return; 1310 case SEEQ_8005: 1311 ea_mc_reset_8005(sc); 1312 return; 1313 } 1314} 1315 1316static void 1317ea_mc_reset_8004(struct seeq8005_softc *sc) 1318{ 1319 struct ethercom *ec = &sc->sc_ethercom; 1320 struct ifnet *ifp = &ec->ec_if; 1321 struct ether_multi *enm; 1322 u_int8_t *cp, c; 1323 u_int32_t crc; 1324 int i, len; 1325 struct ether_multistep step; 1326 u_int8_t af[8]; 1327 1328 /* 1329 * Set up multicast address filter by passing all multicast addresses 1330 * through a crc generator, and then using bits 2 - 7 as an index 1331 * into the 64 bit logical address filter. The high order bits 1332 * selects the word, while the rest of the bits select the bit within 1333 * the word. 1334 */ 1335 1336 if (ifp->if_flags & IFF_PROMISC) { 1337 ifp->if_flags |= IFF_ALLMULTI; 1338 for (i = 0; i < 8; i++) 1339 af[i] = 0xff; 1340 return; 1341 } 1342 for (i = 0; i < 8; i++) 1343 af[i] = 0; 1344 ETHER_FIRST_MULTI(step, ec, enm); 1345 while (enm != NULL) { 1346 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1347 sizeof(enm->enm_addrlo)) != 0) { 1348 /* 1349 * We must listen to a range of multicast addresses. 1350 * For now, just accept all multicasts, rather than 1351 * trying to set only those filter bits needed to match 1352 * the range. (At this time, the only use of address 1353 * ranges is for IP multicast routing, for which the 1354 * range is big enough to require all bits set.) 1355 */ 1356 ifp->if_flags |= IFF_ALLMULTI; 1357 for (i = 0; i < 8; i++) 1358 af[i] = 0xff; 1359 break; 1360 } 1361 cp = enm->enm_addrlo; 1362 crc = 0xffffffff; 1363 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1364 c = *cp++; 1365 for (i = 8; --i >= 0;) { 1366 if (((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01)) { 1367 crc <<= 1; 1368 crc ^= 0x04c11db6 | 1; 1369 } else 1370 crc <<= 1; 1371 c >>= 1; 1372 } 1373 } 1374 /* Just want the 6 most significant bits. */ 1375 crc = (crc >> 2) & 0x3f; 1376 1377 /* Turn on the corresponding bit in the filter. */ 1378 af[crc >> 3] |= 1 << (crc & 0x7); 1379 1380 ETHER_NEXT_MULTI(step, enm); 1381 } 1382 ifp->if_flags &= ~IFF_ALLMULTI; 1383 1384 ea_select_buffer(sc, SEEQ_BUFCODE_MULTICAST); 1385 for (i = 0; i < 8; ++i) 1386 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1387 SEEQ_BUFWIN, af[i]); 1388} 1389 1390static void 1391ea_mc_reset_8005(struct seeq8005_softc *sc) 1392{ 1393 struct ether_multi *enm; 1394 struct ether_multistep step; 1395 int naddr, maxaddrs; 1396 1397 naddr = 0; 1398 maxaddrs = 5; 1399 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1400 while (enm != NULL) { 1401 /* Have we got space? */ 1402 if (naddr >= maxaddrs || 1403 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1404 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1405 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1406 return; 1407 } 1408 ea_set_address(sc, 1 + naddr, enm->enm_addrlo); 1409 sc->sc_config1 |= SEEQ_CFG1_STATION_ADDR1 << naddr; 1410 naddr++; 1411 ETHER_NEXT_MULTI(step, enm); 1412 } 1413 for (; naddr < maxaddrs; naddr++) 1414 sc->sc_config1 &= ~(SEEQ_CFG1_STATION_ADDR1 << naddr); 1415 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SEEQ_CONFIG1, 1416 sc->sc_config1); 1417} 1418 1419/* 1420 * Device timeout routine. 1421 */ 1422 1423static void 1424ea_watchdog(struct ifnet *ifp) 1425{ 1426 struct seeq8005_softc *sc = ifp->if_softc; 1427 1428 log(LOG_ERR, "%s: lost Tx interrupt (status = 0x%04x)\n", 1429 sc->sc_dev.dv_xname, 1430 bus_space_read_2(sc->sc_iot, sc->sc_ioh, SEEQ_STATUS)); 1431 ifp->if_oerrors++; 1432 1433 /* Kick the interface */ 1434 1435 ea_init(ifp); 1436 1437 ifp->if_timer = 0; 1438} 1439 1440/* End of if_ea.c */ 1441