rtwreg.h revision 1.9
1/* $NetBSD: rtwreg.h,v 1.9 2005/01/02 04:29:36 dyoung Exp $ */ 2/*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32/* Macros for bit twiddling. */ 33/* TBD factor w/ dev/ic/atwreg.h. */ 34 35#ifndef _BIT_TWIDDLE 36#define _BIT_TWIDDLE 37/* nth bit, BIT(0) == 0x1. */ 38#define BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n))) 39 40/* bits m through n, m < n. */ 41#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 42 43/* find least significant bit that is set */ 44#define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 45 46/* for x a power of two and p a non-negative integer, is x a greater 47 * power than 2**p? 48 */ 49#define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 50 51#define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 52 53#define MASK_TO_SHIFT4(m) \ 54 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 55 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 56 : MASK_TO_SHIFT2((m))) 57 58#define MASK_TO_SHIFT8(m) \ 59 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 60 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 61 : MASK_TO_SHIFT4((m))) 62 63#define MASK_TO_SHIFT16(m) \ 64 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 65 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 66 : MASK_TO_SHIFT8((m))) 67 68#define MASK_TO_SHIFT(m) \ 69 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 70 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 71 : MASK_TO_SHIFT16((m))) 72 73#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 74#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 75#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 76#define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 77 78#endif /* _BIT_TWIDDLE */ 79 80/* RTL8180L Host Control and Status Registers */ 81 82#define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 83 * Auto-loaded from EEPROM. Read by byte, 84 * by word, or by double word, but write 85 * only by double word. 86 */ 87#define RTW_IDR1 0x04 88 89#define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 90#define RTW_MAR1 0x0c 91 92#define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 93 * Register, low word, 32b, read-only. 94 */ 95#define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 96#define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 97 * Address, 32b, 256-byte alignment. 98 */ 99#define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 100 * Address, 32b, 256-byte alignment. 101 */ 102#define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 103 * Address, 32b, 256-byte alignment. 104 */ 105 106#define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 107#define RTW_BRSR_BPLCP BIT(8) /* 1: use short PLCP header for CTS/ACK packet, 108 * 0: use long PLCP header 109 */ 110#define RTW_BRSR_MBR8180_MASK BITS(1,0) /* Maximum Basic Service Rate */ 111#define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR8180_MASK) 112#define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR8180_MASK) 113#define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR8180_MASK) 114#define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR8180_MASK) 115 116/* 8181 and 8180 docs conflict! */ 117#define RTW_BRSR_MBR8181_1MBPS BIT(0) 118#define RTW_BRSR_MBR8181_2MBPS BIT(1) 119#define RTW_BRSR_MBR8181_5MBPS BIT(2) 120#define RTW_BRSR_MBR8181_11MBPS BIT(3) 121 122#define RTW_BSSID 0x2e 123/* BSSID, 6 bytes */ 124#define RTW_BSSID16 0x2e /* first two bytes */ 125#define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 126#define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 127#define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 128#define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 129#define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 130#define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 131#define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 132 133#define RTW_CR 0x37 /* Command Register, 8b */ 134#define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable 135 * transmitter & receiver, reinitialize FIFO. 136 * RTL8180L sets to 0 to signal completion. 137 */ 138#define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver 139 * by writing 1. RTL8180L indicates receiver 140 * is active with 1. After power-up, host 141 * must wait for reset before writing. 142 */ 143#define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter 144 * by writing 1. RTL8180L indicates transmitter 145 * is active with 1. After power-up, host 146 * must wait for reset before writing. 147 */ 148#define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables, 149 * 0 disables. XXX RTL8180, only? 150 */ 151 152#define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 153#define RTW_ISR 0x3e /* Interrupt status register, 16b */ 154 155#define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO Overflow */ 156#define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates 157 * RTW_TSFTR[0:31] = RTW_TINT 158 */ 159#define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to 160 * prepare beacon: 161 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 162 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 163 */ 164#define RTW_INTR_ATIMINT BIT(12) 165 /* ATIM Time Out: ATIM interval will pass, 166 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 167 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 168 */ 169#define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error: 170 * beacon transmission aborted because 171 * frame Rx'd 172 */ 173#define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */ 174#define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error: 175 * reached short/long retry limit 176 */ 177#define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */ 178#define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error: 179 * reached short/long retry limit 180 */ 181#define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */ 182#define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below) 183 * or PCI bus too slow/busy 184 */ 185#define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */ 186#define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error 187 * reached short/long retry limit 188 */ 189#define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */ 190#define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */ 191#define RTW_INTR_ROK BIT(0) /* Rx OK */ 192 193/* Convenient interrupt conjunctions. */ 194#define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK) 195#define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 196 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK) 197#define RTW_INTR_BEACON (RTW_INTR_TBDER|RTW_INTR_TBDOK|RTW_INTR_BCNINT) 198#define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 199 200#define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 201#define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */ 202#define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number, 203 * 0: hardware assigns sequence number 204 */ 205/* Hardware version ID, read-only */ 206#define RTW_TCR_HWVERID_MASK BITS(29, 25) 207#define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK) 208#define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK) 209#define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F 210 211/* Set ACK/CTS Timeout (EIFS). 212 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 213 * 0: ACK rate = 1Mbps 214 */ 215#define RTW_TCR_SAT BIT(24) 216/* Max DMA Burst Size per Tx DMA Burst */ 217#define RTW_TCR_MXDMA_MASK BITS(23,21) 218#define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 219#define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 220#define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 221#define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 222#define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 223#define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 224#define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 225#define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 226 227#define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */ 228 229#define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to 230 * WEP packets 231 */ 232 233/* Loopback Test: disables TXI/TXQ outputs. */ 234#define RTW_TCR_LBK_MASK BITS(18,17) 235#define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 236#define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 237#define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 238#define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 239 240#define RTW_TCR_CRC BIT(16) /* 0: RTL8180 appends CRC32 241 * 1: host appends CRC32 242 * 243 * (I *think* this is right. 244 * The docs have a mysterious 245 * description in the 246 * passive voice.) 247 */ 248#define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */ 249#define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */ 250 251#define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 252#define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets 253 * longer than 1536 bytes 254 */ 255#define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */ 256#define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */ 257#define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */ 258#define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set 259 * "Link On" when received BSSID 260 * matches RTW_BSSID and received 261 * ToDS/FromDS are appropriate 262 * according to RTW_MSR_NETYPE. 263 */ 264#define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */ 265#define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE == 266 * RTW_MSR_NETYPE_INFRA_OK, accept 267 * broadcast/multicast packets whose 268 * 3rd address matches RTL8180's MAC. 269 */ 270#define RTW_RCR_AMF BIT(20) /* accept management frames */ 271#define RTW_RCR_ACF BIT(19) /* accept control frames */ 272#define RTW_RCR_ADF BIT(18) /* accept data frames */ 273/* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 274 * bytes are received 275 */ 276#define RTW_RCR_RXFTH_MASK BITS(15,13) 277#define RTW_RCR_RXFTH_64 LSHIFT(2, RTW_RCR_RXFTH_MASK) 278#define RTW_RCR_RXFTH_128 LSHIFT(3, RTW_RCR_RXFTH_MASK) 279#define RTW_RCR_RXFTH_256 LSHIFT(4, RTW_RCR_RXFTH_MASK) 280#define RTW_RCR_RXFTH_512 LSHIFT(5, RTW_RCR_RXFTH_MASK) 281#define RTW_RCR_RXFTH_1024 LSHIFT(6, RTW_RCR_RXFTH_MASK) 282#define RTW_RCR_RXFTH_WHOLE LSHIFT(7, RTW_RCR_RXFTH_MASK) 283 284#define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */ 285 286/* Max DMA Burst Size per Rx DMA Burst */ 287#define RTW_RCR_MXDMA_MASK BITS(10,8) 288#define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 289#define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 290#define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 291#define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 292#define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 293#define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 294#define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 295#define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 296 297/* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 298#define RTW_RCR_9356SEL BIT(6) 299 300#define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */ 301#define RTW_RCR_AB BIT(3) /* accept broadcast frames */ 302#define RTW_RCR_AM BIT(2) /* accept multicast frames */ 303/* accept physical match frames. XXX means PLCP header ok? */ 304#define RTW_RCR_APM BIT(1) 305#define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */ 306 307#define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 308#define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 309 * 32b, 256-byte alignment 310 */ 311#define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 312#define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */ 313#define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 314/* Load the EEPROM. Reset registers to defaults. 315 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 316 * XXX RTL8180 only? 317 */ 318#define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 319/* Disable network & bus-master operations and enable 320 * _EECS, _EESK, _EEDI, _EEDO. 321 * XXX RTL8180 only? 322 */ 323#define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 324/* Enable RTW_CONFIG[0123] registers. */ 325#define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 326/* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 327 * XXX RTL8180 only? 328 */ 329#define RTW_9346CR_EECS BIT(3) 330#define RTW_9346CR_EESK BIT(2) 331#define RTW_9346CR_EEDI BIT(1) 332#define RTW_9346CR_EEDO BIT(0) /* read-only */ 333 334#define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 335#define RTW_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP, 336 * XXX RTL8180 only? 337 */ 338#define RTW_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP, 339 * from EEPROM, read-only 340 * XXX RTL8180 only? 341 */ 342#define RTW_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control 343 * LED[01] pins. 344 * 0: LED behavior defined by 345 * RTW_CONFIG1_LEDS10_MASK 346 * XXX RTL8180 only? 347 */ 348/* auxiliary power is present, read-only */ 349#define RTW_CONFIG0_AUXPWR BIT(3) 350/* Geographic Location, read-only */ 351#define RTW_CONFIG0_GL_MASK BITS(1,0) 352/* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_* 353 * work. 354 */ 355#define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK) 356#define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK) 357#define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK) 358#define RTW_CONFIG0_GL_USA LSHIFT(0, RTW_CONFIG0_GL_MASK) 359/* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 360 361#define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 362 363/* LED configuration. From EEPROM. Read/write. 364 * 365 * Setting LED0 LED1 366 * ------- ---- ---- 367 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 368 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 369 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 370 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 371 */ 372#define RTW_CONFIG1_LEDS_MASK BITS(7,6) 373#define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 374#define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 375#define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 376#define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 377 378/* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 379 * 380 * RTW_CONFIG1_LWACT 381 * 0 1 382 * RTW_CONFIG4_LWPTN 0 active high active low 383 * 1 positive pulse negative pulse 384 */ 385#define RTW_CONFIG1_LWACT BIT(4) 386 387#define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */ 388#define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */ 389#define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets 390 * 0x40-0x7f in EEPROM are at 391 * registers 0x60-0x67 of PCI 392 * Configuration Space (XXX huh?) 393 */ 394#define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */ 395 396#define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 397#define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only: 398 * Tx frequency & symbol clocks 399 * are derived from the same OSC 400 */ 401#define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */ 402#define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable 403 * test mode. 404 */ 405#define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */ 406#define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */ 407 408#define RTW_ANAPARM 0x54 /* Analog parameter, 32b */ 409#define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits 410 * which appear to 411 * control the power 412 * state of the RF 413 * components 414 */ 415#define RTW_ANAPARM_RFPOW_MASK \ 416 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 417 418#define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC, 419 * 0: enable 420 */ 421#define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits 422 * which appear to 423 * control the power 424 * state of the RF 425 * components 426 */ 427 428/* 429 * Maxim On/Sleep/Off control 430 */ 431#define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 432 433/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 434#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 435 436/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 437#define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 438 439/* 440 * RFMD On/Sleep/Off control 441 */ 442#define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK) 443 444/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 445#define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 446 447/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 448#define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 449 450/* 451 * Philips On/Sleep/Off control 452 */ 453#define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 454 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 455#define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 456 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK) 457 458/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 459#define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 460 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 461 462/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 463#define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 464 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 465 466#define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 467 468#define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented 469 * card-specific 470 * bits from the 471 * EEPROM. 472 */ 473 474#define RTW_MSR 0x58 /* Media Status Register, 8b */ 475/* Network Type and Link Status */ 476#define RTW_MSR_NETYPE_MASK BITS(3,2) 477/* AP, XXX RTL8181 only? */ 478#define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 479/* infrastructure link ok */ 480#define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 481/* ad-hoc link ok */ 482#define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 483/* no link */ 484#define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 485 486#define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 487#define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */ 488#define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and 489 * RTW_9346CR_EEM_CONFIG to 490 * allow RTW_ANAPARM writes. 491 */ 492#define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is 493 * set. If set, RTL8180 wakes up 494 * OS when Magic Packet is Rx'd. 495 */ 496#define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers 497 * and functions are enabled, 498 * read-only. XXX RTL8180 only. 499 */ 500#define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only. 501 * XXX RTL8180 only. 502 */ 503#define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled, 504 * read-only. XXX RTL8180 only. 505 */ 506#define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled, 507 * read-only. 508 */ 509#define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 510#define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down 511 * 0: normal operation 512 * (power-on default) 513 * 1: power-down VCO, RF front-end, 514 * and most RTL8180 components. 515 */ 516#define RTW_CONFIG4_PWROFF BIT(6) /* Power Off 517 * 0: normal operation 518 * (power-on default) 519 * 1: power-down RF front-end, 520 * and most RTL8180 components, 521 * but leave VCO on. 522 * 523 * XXX RFMD front-end only? 524 */ 525#define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management 526 * 0: normal operation 527 * (power-on default) 528 * 1: set Tx packet's PWRMGMT bit. 529 */ 530#define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only 531 * 0: LWAKE & PMEB asserted 532 * simultaneously 533 * 1: LWAKE asserted only if 534 * both PMEB is asserted and 535 * ISOLATEB is low. 536 * XXX RTL8180 only. 537 */ 538#define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT 539 * XXX RTL8180 only. 540 */ 541/* Radio Front-End Programming Method */ 542#define RTW_CONFIG4_RFTYPE_MASK BITS(1,0) 543#define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 544#define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 545#define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 546 547#define RTW_TESTR 0x5B /* TEST mode register, 8b */ 548 549#define RTW_PSR 0x5e /* Page Select Register, 8b */ 550#define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */ 551#define RTW_PSR_GPI BIT(6) /* Status of pin 64. */ 552#define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if 553 * RTW_CONFIG0_LEDGPOEN is set. 554 */ 555#define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if 556 * RTW_CONFIG0_LEDGPOEN is set. 557 */ 558#define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */ 559#define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */ 560 561#define RTW_SCR 0x5f /* Security Configuration Register, 8b */ 562#define RTW_SCR_KM_MASK BITS(5,4) /* Key Mode */ 563#define RTW_SCR_KM_WEP104 LSHIFT(1, RTW_SCR_KM_MASK) 564#define RTW_SCR_KM_WEP40 LSHIFT(0, RTW_SCR_KM_MASK) 565#define RTW_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if 566 * neither RTW_CONFIG0_WEP40 nor 567 * RTW_CONFIG0_WEP104 is set. 568 */ 569#define RTW_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if 570 * neither RTW_CONFIG0_WEP40 nor 571 * RTW_CONFIG0_WEP104 is set. 572 */ 573 574#define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 575#define RTW_BCNITV_BCNITV_MASK BITS(9,0) /* TU between TBTT, written 576 * by host. 577 */ 578#define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 579#define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU, 580 * written by host. 581 */ 582 583#define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 584#define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with 585 * RTW_INTR_BCNINT at BINTRITV 586 * microseconds before TBTT 587 */ 588#define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 589#define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with 590 * RTW_INTR_ATIMINT at ATIMTRITV 591 * microseconds before end of 592 * ATIM Window 593 */ 594 595#define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 596#define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference 597 * driver 598 */ 599#define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between 600 * MAC and RF front-end 601 */ 602#define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 603#define RTW_CRCOUNT_MAGIC 0x4c 604 605#define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 606 607#define RTW_BB 0x7c /* Baseband interface, 32b */ 608/* used for writing RTL8180's integrated baseband processor */ 609#define RTW_BB_RD_MASK BITS(23,16) /* data to read */ 610#define RTW_BB_WR_MASK BITS(15,8) /* data to write */ 611#define RTW_BB_WREN BIT(7) /* write enable */ 612#define RTW_BB_ADDR_MASK BITS(6,0) /* address */ 613 614#define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 615#define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 616#define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 617 618#define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 619#define RTW_PHYCFG_MAC_POLL BIT(31) /* if !RTW_PHYCFG_HST, 620 * host sets. MAC clears 621 * after banging bits. 622 */ 623#define RTW_PHYCFG_HST BIT(30) /* 1: host bangs bits 624 * 0: MAC bangs bits 625 */ 626#define RTW_PHYCFG_MAC_RFTYPE_MASK BITS(29,28) 627#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK) 628#define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK) 629#define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD 630#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK) 631#define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24) 632#define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0) 633#define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24) 634#define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8) 635#define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0) 636#define RTW_PHYCFG_HST_EN BIT(2) 637#define RTW_PHYCFG_HST_CLK BIT(1) 638#define RTW_PHYCFG_HST_DATA BIT(0) 639 640#define RTW_MAXIM_HIDATA_MASK BITS(11,4) 641#define RTW_MAXIM_LODATA_MASK BITS(3,0) 642 643/** 644 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 645 **/ 646 647#define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 648#define RTW_WAKEUP0H 0x88 /* 32b */ 649 650#define RTW_WAKEUP1L 0x8c 651#define RTW_WAKEUP1H 0x90 652 653#define RTW_WAKEUP2LL 0x94 654#define RTW_WAKEUP2LH 0x98 655 656#define RTW_WAKEUP2HL 0x9c 657#define RTW_WAKEUP2HH 0xa0 658 659#define RTW_WAKEUP3LL 0xa4 660#define RTW_WAKEUP3LH 0xa8 661 662#define RTW_WAKEUP3HL 0xac 663#define RTW_WAKEUP3HH 0xb0 664 665#define RTW_WAKEUP4LL 0xb4 666#define RTW_WAKEUP4LH 0xb8 667 668#define RTW_WAKEUP4HL 0xbc 669#define RTW_WAKEUP4HH 0xc0 670 671#define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 672#define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 673#define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 674#define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 675#define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 676 677/** 678 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 679 **/ 680 681/* Default Key Registers, each 128b 682 * 683 * If RTW_SCR_KM_WEP104, 104 lsb are the key. 684 * If RTW_SCR_KM_WEP40, 40 lsb are the key. 685 */ 686#define RTW_DK0 0x90 /* Default Key 0 Register, 128b */ 687#define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */ 688#define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */ 689#define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */ 690 691#define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 692#define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */ 693#define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */ 694#define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle 695 * and raise AGCRESET pin. 696 * 0: lower AGCRESET pin 697 */ 698#define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */ 699#define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal, 700 * from EEPROM 701 */ 702#define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset 703 * reset PME_Status 704 * 0: only software resets PME_Status 705 * 706 * From EEPROM. 707 */ 708 709#define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 710 * write-only. 711 */ 712#define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon 713 * Tx. Host writes have no effect. 714 */ 715#define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of 716 * high-priority Tx packets, RTL8180 clears 717 * to after high-priority Tx is complete. 718 */ 719#define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set, 720 * host writes 1 to notify RTL8180 of 721 * normal-priority Tx packets, RTL8180 clears 722 * after normal-priority Tx is complete. 723 * 724 * If RTW_CONFIG2_DPS is clear, host writes 725 * have no effect. RTL8180 clears after 726 * normal-priority Tx is complete. 727 */ 728#define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of 729 * low-priority Tx packets, RTL8180 clears 730 * after low-priority Tx is complete. 731 */ 732#define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to 733 * stop beacon DMA. This bit is invalid 734 * when RTW_CONFIG2_DPS is set. 735 */ 736#define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to 737 * stop high-priority DMA. 738 */ 739#define RTW_TPPOLL_SNPQ BIT(2) /* Host writes 1 to tell RTL8180 to 740 * stop normal-priority DMA. This bit is invalid 741 * when RTW_CONFIG2_DPS is set. 742 */ 743#define RTW_TPPOLL_SLPQ BIT(2) /* Host writes 1 to tell RTL8180 to 744 * stop low-priority DMA. 745 */ 746#define RTW_TPPOLL_FSWINT BIT(0) /* Force software interrupt. From 747 * reference driver. 748 */ 749 750 751#define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 752/* Contention Window: indicates number of contention windows before Tx 753 */ 754#define RTW_CWR_CW BITS(9,0) 755 756/* Retry Count Register, 16b, read-only */ 757#define RTW_RETRYCTR 0xde 758/* Retry Count: indicates number of retries after Tx */ 759#define RTW_RETRYCTR_RETRYCT BITS(7,0) 760 761#define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 762 * 32b, 256-byte alignment. 763 */ 764/* Function Event Register, 32b, Cardbus only. Only valid when 765 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 766 */ 767#define RTW_FER 0xf0 768#define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 769#define RTW_FER_GWAKE BIT(4) /* General Wakeup */ 770/* Function Event Mask Register, 32b, Cardbus only. Only valid when 771 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 772 */ 773#define RTW_FEMR 0xf4 774#define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */ 775#define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */ 776#define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */ 777/* Function Present State Register, 32b, read-only, Cardbus only. 778 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 779 * are set. 780 */ 781#define RTW_FPSR 0xf8 782#define RTW_FPSR_INTR BIT(15) /* TBD */ 783#define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */ 784/* Function Force Event Register, 32b, write-only, Cardbus only. 785 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 786 * are set. 787 */ 788#define RTW_FFER 0xfc 789#define RTW_FFER_INTR BIT(15) /* TBD */ 790#define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */ 791 792/* Serial EEPROM offsets */ 793#define RTW_SR_ID 0x00 /* 16b */ 794#define RTW_SR_VID 0x02 /* 16b */ 795#define RTW_SR_DID 0x04 /* 16b */ 796#define RTW_SR_SVID 0x06 /* 16b */ 797#define RTW_SR_SMID 0x08 /* 16b */ 798#define RTW_SR_MNGNT 0x0a 799#define RTW_SR_MXLAT 0x0b 800#define RTW_SR_RFCHIPID 0x0c 801#define RTW_SR_CONFIG3 0x0d 802#define RTW_SR_MAC 0x0e /* 6 bytes */ 803#define RTW_SR_CONFIG0 0x14 804#define RTW_SR_CONFIG1 0x15 805#define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 806#define RTW_SR_CONFIG2 0x18 807#define RTW_SR_CONFIG4 0x19 808#define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 809#define RTW_SR_TESTR 0x1e 810#define RTW_SR_CONFIG5 0x1f 811#define RTW_SR_TXPOWER1 0x20 812#define RTW_SR_TXPOWER2 0x21 813#define RTW_SR_TXPOWER3 0x22 814#define RTW_SR_TXPOWER4 0x23 815#define RTW_SR_TXPOWER5 0x24 816#define RTW_SR_TXPOWER6 0x25 817#define RTW_SR_TXPOWER7 0x26 818#define RTW_SR_TXPOWER8 0x27 819#define RTW_SR_TXPOWER9 0x28 820#define RTW_SR_TXPOWER10 0x29 821#define RTW_SR_TXPOWER11 0x2a 822#define RTW_SR_TXPOWER12 0x2b 823#define RTW_SR_TXPOWER13 0x2c 824#define RTW_SR_TXPOWER14 0x2d 825#define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 826#define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 827#define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 828#define RTW_SR_CISPOINTER 0x30 /* 16b */ 829#define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 830#define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */ 831#define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */ 832#define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */ 833#define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 834#define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 835#define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 836#define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 837 838/* 839 * RTL8180 Transmit/Receive Descriptors 840 */ 841 842/* the first descriptor in each ring must be on a 256-byte boundary */ 843#define RTW_DESC_ALIGNMENT 256 844 845/* Tx descriptor */ 846struct rtw_txdesc { 847 uint32_t td_ctl0; 848 uint32_t td_ctl1; 849 uint32_t td_buf; 850 uint32_t td_len; 851 uint32_t td_next; 852 uint32_t td_rsvd[3]; 853}; 854 855#define td_stat td_ctl0 856 857#define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */ 858#define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */ 859#define RTW_TXCTL0_FS BIT(29) /* first segment */ 860#define RTW_TXCTL0_LS BIT(28) /* last segment */ 861 862#define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */ 863#define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK) 864#define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK) 865#define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK) 866#define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK) 867 868#define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */ 869 870#define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */ 871#define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK) 872#define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK) 873#define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK) 874#define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK) 875 876#define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */ 877#define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */ 878#define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble 879 * and header 880 */ 881#define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */ 882#define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */ 883#define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size 884 * in bytes 885 */ 886 887#define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 888#define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 889#define RTW_TXSTAT_FS RTW_TXCTL0_FS 890#define RTW_TXSTAT_LS RTW_TXCTL0_LS 891#define RTW_TXSTAT_RSVD1_MASK BITS(27,16) 892#define RTW_TXSTAT_TOK BIT(15) 893#define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */ 894#define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */ 895 896#define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH 897 * in packets sent 5.5Mb/s or 898 * faster 899 */ 900#define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */ 901#define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration 902 * (microseconds) 903 */ 904 905#define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */ 906 907/* Rx descriptor */ 908struct rtw_rxdesc { 909 uint32_t rd_ctl; 910 uint32_t rd_rsvd0; 911 uint32_t rd_buf; 912 uint32_t rd_rsvd1; 913}; 914 915#define rd_stat rd_ctl 916#define rd_rssi rd_rsvd0 917#define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 918#define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 919 920#define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */ 921#define RTW_RXCTL_EOR BIT(30) /* end of ring */ 922#define RTW_RXCTL_FS BIT(29) /* first segment */ 923#define RTW_RXCTL_LS BIT(28) /* last segment */ 924#define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */ 925#define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */ 926 927#define RTW_RXSTAT_OWN RTW_RXCTL_OWN 928#define RTW_RXSTAT_EOR RTW_RXCTL_EOR 929#define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 930#define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 931#define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */ 932#define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means 933 * FIFO exhausted? 934 */ 935#define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble 936 * and PLCP header 937 */ 938#define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */ 939#define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */ 940#define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 941#define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 942#define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 943#define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 944#define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */ 945#define RTW_RXSTAT_MAR BIT(18) /* is multicast */ 946#define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */ 947#define RTW_RXSTAT_BAR BIT(16) /* is broadcast */ 948#define RTW_RXSTAT_RES BIT(15) /* error summary. valid when 949 * RTW_RXSTAT_LS set. indicates 950 * that either RTW_RXSTAT_CRC32 951 * or RTW_RXSTAT_ICV is set. 952 */ 953#define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */ 954#define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from 955 * reference driver 956 */ 957#define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */ 958#define RTW_RXSTAT_ICV BIT(12) /* ICV error */ 959#define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including 960 * CRC32 961 */ 962 963/* Convenient status conjunction. */ 964#define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 965/* Convenient status disjunctions. */ 966#define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 967#define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 968 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 969 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 970 RTW_RXSTAT_ICV) 971 972 973#define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */ 974/* for Philips RF front-ends */ 975#define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */ 976/* for RF front-ends by Intersil, Maxim, RFMD */ 977#define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */ 978#define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */ 979#define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */ 980 981#define RTW_READ8(regs, ofs) \ 982 bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs)) 983 984#define RTW_READ16(regs, ofs) \ 985 bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs)) 986 987#define RTW_READ(regs, ofs) \ 988 bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs)) 989 990#define RTW_WRITE8(regs, ofs, val) \ 991 bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 992 993#define RTW_WRITE16(regs, ofs, val) \ 994 bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 995 996#define RTW_WRITE(regs, ofs, val) \ 997 bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val)) 998 999#define RTW_ISSET(regs, reg, mask) \ 1000 (RTW_READ((regs), (reg)) & (mask)) 1001 1002#define RTW_CLR(regs, reg, mask) \ 1003 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 1004 1005/* bus_space(9) lied? */ 1006#ifndef BUS_SPACE_BARRIER_SYNC 1007#define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1008#endif 1009 1010#ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1011#define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1012#endif 1013 1014#ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1015#define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1016#endif 1017 1018#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1019#define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1020#endif 1021 1022#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1023#define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1024#endif 1025 1026/* 1027 * Bus barrier 1028 * 1029 * Complete outstanding read and/or write ops on [reg0, reg1] 1030 * ([reg1, reg0]) before starting new ops on the same region. See 1031 * acceptable bus_space_barrier(9) for the flag definitions. 1032 */ 1033#define RTW_BARRIER(regs, reg0, reg1, flags) \ 1034 bus_space_barrier((regs)->r_bh, (regs)->r_bt, \ 1035 MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags) 1036 1037/* 1038 * Barrier convenience macros. 1039 */ 1040/* sync */ 1041#define RTW_SYNC(regs, reg0, reg1) \ 1042 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1043 1044/* write-before-write */ 1045#define RTW_WBW(regs, reg0, reg1) \ 1046 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1047 1048/* write-before-read */ 1049#define RTW_WBR(regs, reg0, reg1) \ 1050 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1051 1052/* read-before-read */ 1053#define RTW_RBR(regs, reg0, reg1) \ 1054 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1055 1056/* read-before-read */ 1057#define RTW_RBW(regs, reg0, reg1) \ 1058 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1059 1060#define RTW_WBRW(regs, reg0, reg1) \ 1061 RTW_BARRIER(regs, reg0, reg1, \ 1062 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1063 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1064 1065/* 1066 * Registers for RTL8180L's built-in baseband modem. 1067 */ 1068#define RTW_BBP_SYS1 0x00 1069#define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1070#define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation 1071 * threshold 1072 */ 1073#define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF) 1074 * auto-gain control (AGC) initial value 1075 */ 1076#define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1077#define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for 1078 * IF AGC loop 1079 */ 1080 1081#define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1082#define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1083#define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1084#define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1085#define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1086#define RTW_BBP_ANTATTEN_DFLANTB 0x40 1087#define RTW_BBP_ANTATTEN_CHAN14 0x0c 1088 1089#define RTW_BBP_TRL 0x11 /* guess: transmit/receive 1090 * switch latency 1091 */ 1092#define RTW_BBP_SYS2 0x12 1093#define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1094#define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate? 1095 * 0: 1Mbps 1096 * 1: 2Mbps 1097 * 2: 5.5Mbps 1098 * 3: 11Mbps 1099 */ 1100#define RTW_BBP_SYS3 0x13 1101/* carrier-sense threshold */ 1102#define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3) 1103#define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect 1104 * threshold 1105 */ 1106#define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality 1107 * threshold 1108 */ 1109